JP2006093816A - Solid-state imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology of enhancing a deteriorated reduction effect of an overall read time due to a horizontal blanking time in speeding up a reading speed of a row scanning type CMOS sensor by means of multi-channel parallel reading. <P>SOLUTION: Although the reading speed of the row scanning type CMOS sensor can easily be increased by the multi-channel parallel reading, since the so-called horizontal blanking time for storing image data at (n+1)th row to a row memory cannot be reduced, the overall read time cannot h be much reduced regardless of increased number of channels. In order to solve such the problem in this embodiment, the operation of storing the image data at the (n+1)th row having been executed for the horizontal blanking time to the row memory, is executed during column scanning reading of image data at the n-th row from the row memory to substantially eliminate the blanking time thereby realizing effective high speed reading. Further, intrusion of noise to the column scanning reading can be reduced by carrying out the both at the same time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device such as a digital still camera.

  In recent years, there has been a strong demand for solid-state imaging devices to have higher pixels and higher speed. In a digital still camera, a high pixel count of several megapixels to several tens of megapixels can be seen. There is also a demand for products with a speed of about 10 frames per second.

  On the other hand, products that can read out 2 million pixels at 30 frames per second by 2ch parallel reading using a CCD to read a screen divided into right and left parts using a CCD are beginning to come out.

  In such a need, a solid-state imaging device has been attracting attention as a CMOS sensor that can easily perform a multi-channel parallel output in order to output a large amount of pixels in a short time.

  The CMOS sensor reads the pixel output to the readout output line via the selection switch, but the wiring is arranged in a grid around the pixel, so the wiring resistance and the wiring capacitance are large and read out for each pixel. Then, it takes time to charge the wiring capacity of the read output line, and as a result, it may become impossible to read at high speed.

  Therefore, it is general to adopt a row scanning type reading method in which the balance between the circuit size and the high speed is taken.

  In the row scanning type readout, a memory for row scanning is provided on the upper and lower sides of the two-dimensionally arranged image sensor, and the image data of the nth row is transferred to the memory collectively during the horizontal blanking period, Thereafter, the column is sequentially scanned from the memory and data of each pixel is output.

  FIG. 2 is a diagram showing a method for speeding up a conventional row scanning type CMOS sensor.

  Thblnk represents the CT transfer time, and Tread represents the horizontal pixel readout time.

  The CT transfer time is a time for collecting two rows of image sensor pixels in a two-dimensional array and transferring them to the row memory capacity group CT at this timing, and is generally performed at the timing of horizontal blanking.

  Tread is a timing at which pixel signals are sequentially read out from the output terminal by scanning in the column direction from the row memory group CT. If multi-channel output is used for speeding up, Tread is fractional for the number of channels. Time is reduced.

  For example, with 2 channels, Tread can be halved compared with 1 channel, and with 4 channels, it can be shortened to 1/4.

  Thus, one horizontal scanning time is expressed as Thblnk + Tread, and this is repeated by the number of vertical rows, and one image is read out. In addition to this, the Tvblnk accumulation time (≈exposure time) is included in the sequence of one frame.

  When trying to increase the continuous frame speed, Tread can be shortened by increasing the number of channels, but Thblnk and Tvblnk cannot be shortened.

  The accumulation time Tvblnk is an indispensable element in consideration of sensor sensitivity and subject brightness, but it also gives up. However, only Thblnk can be shortened somewhat by devising the circuit. However, the CT transfer for one row takes a certain amount of time because the vertical wiring is driven and the CT capacitor is charged with the signal charge. At this time, a pixel FPN (a read transistor of the readout transistor) peculiar to the CMOS sensor is required. Since there is a sequence for removing (though VTH variation is dominant), it cannot be shortened significantly.

  FIG. 3 is a graph showing the number of frames per second when the number of read channels is increased. If the number of pixels is 10 million pixels, the aspect ratio is 2: 3, the accumulation time is 20 ms, the readout frequency is 16 MHZ, the row transfer time to the row memory Ct, that is, the horizontal blanking time is 15 us, 8 ch parallel reading is 7 frames per second. Thus, even with 16 channels, the speed can be increased only to about 10 frames per second. At this time, the horizontal blanking time and the reading time are almost the same, and it can be seen how the reading efficiency is deteriorated even if the number of channels is increased.

  In more detail, 10 million pixels and 3: 2 horizontal pixels are about 4000 pixels, vertical pixels are about 2600 pixels, 16 channels are read out at 16 MHZ, Full screen Thread ≈ 40 ms, Full screen Thblnk ≈ 40 ms , Tvblnk≈20 ms, and one frame is 100 ms.

  In order to increase the frame speed in this way, the specific gravity of Thblnk increases as the speed increases, and some countermeasure is desired.

  Next, the operation of the conventional circuit will be specifically described with reference to FIG.

  FIG. 4 is an equivalent circuit diagram of a conventional CMOS solid-state imaging device. 6 is a schematic mounting plan view of the horizontal transfer switches N511 to N513, the reset switch N514, the horizontal scanning circuit block 5, and the differential amplifier circuit 51 of FIG. FIG. 6 shows a state in which the above-described parts are connected by two wiring layers of the first wiring layer and the second wiring layer.

  In FIG. 4, a pixel unit 1, a vertical scanning circuit block 2, a horizontal scanning circuit block 5, an input MOS transistor N51, load MOS transistors N52 to N54, clamp capacitors C01 to C03, and a clamp switch described below are shown. N55 to N57, transfer switches N58 to N510, signal holding capacitors CT1 to CT3, horizontal transfer switches N511 to 513, a reset switch N514, and a differential amplifier circuit 51 are provided.

  Photodiodes D11 to D33 provided in the pixel unit 1 generate optical signal charges. Here, the anode side is grounded. The cathode sides of the photodiodes D11 to D33 are connected to the gates of the amplification MOS transistors M311 to M333 via the transfer MOS transistors M111 to M133.

  The sources of reset MOS transistors M211 to M233 for resetting the amplification MOS transistors M311 to M333 are connected to the gates, and the drains of the reset MOS transistors M211 to M233 are connected to a reset power source.

  Furthermore, the drains of the amplification MOS transistors M311 to M333 are connected to the power source, and the sources are connected to the drains of the selection MOS transistors M411 to M433. The gate of the transfer MOS transistor M111 is connected to a first row selection line (vertical scanning line) PTX1 arranged extending in the horizontal direction.

  The gates of similar transfer MOS transistors M121 and M131 of other pixel cells arranged in the same row are also commonly connected to the first row selection line PTX1. The gate of the reset MOS transistor M211 is connected to a second row selection line (vertical scanning line) PRES1 that extends in the horizontal direction.

  The gates of similar reset MOS transistors M221 and M231 of other pixel cells arranged in the same row are also commonly connected to the second row selection line PRES1. The gate of the selection MOS transistor M411 is connected to a third row selection line (vertical scanning line) PSEL1 arranged extending in the horizontal direction.

  Gates of similar selection MOS transistors M421 and M431 of other pixel cells arranged in the same row are also commonly connected to the third row selection line PSEL1. These first to third row selection lines are connected to the vertical scanning circuit block 2 and supplied with a signal voltage based on an operation timing described later.

  In the remaining rows shown in FIG. 4, pixel cells having the same configuration and row selection lines are provided. PTX2 to PTX3, PRES2 to PRES3, and PSEL2 to PSEL3 formed by the vertical scanning circuit block 2 are supplied to these row selection lines. The source of the selection MOS transistor M411 is connected to the vertical signal line V1 arranged extending in the vertical direction.

  Sources of similar selection MOS transistors M412 and M413 of pixel cells arranged in the same column are also connected to the vertical signal line V1. The vertical signal line V1 is connected to a load MOS transistor N52 which is a load means.

  In the remaining vertical signal lines V2 to V3 shown in FIG. 4, selection MOS transistors and load MOS transistors are similarly connected.

  Further, the sources of the load MOS transistors N52 to N54 are connected to the common GND line 4, and the gates are connected in common to the gate and drain of the input MOS transistor N51 and to the voltage input terminal Vbias.

  The vertical signal line V1 is connected to a capacitor CT1 for temporarily holding a signal via a clamp capacitor C01 and a transfer switch N58, and an inverting input terminal (horizontal output line) of the differential amplifier circuit 51 via a horizontal transfer switch N511. Connected to.

  The non-inverting input terminal of the differential amplifier circuit 51 is connected to the reset voltage Vres of the horizontal output line, and the inverting input terminal is connected to the reset voltage Vres of the horizontal output line via the reset switch N514. The terminal on the opposite side of the signal holding capacitor CT1 is grounded.

  A connection point between the clamp capacitor C01 and the transfer switch N58 is connected to a clamp power source via the clamp switch N55. The gate of the horizontal transfer switch N511 is connected to the signal line H1 and connected to the horizontal scanning circuit block 5.

  In the remaining columns V2 to V3 shown in FIG. 4, readout circuits having the same configuration are provided. Further, the gates of the clamp switches N55 to N57 and the gates of the transfer switches N58 to N510 connected to each column are connected in common to the clamp signal input terminal PC0R and the transfer signal input terminal PT, respectively, and based on the operation timing described later. Each is supplied with a signal voltage.

  FIG. 5 is a timing chart showing the operation of the CMOS type solid-state imaging device shown in FIG. Prior to reading of the optical signal charges from the photodiodes D11 to D33, the gates PRES1 of the reset MOS transistors M211 to M231 are set to the high level.

  As a result, the gates of the amplification MOS transistors M311 to M331 are reset to the reset power source. After the gates PRES1 of the reset MOS transistors M211 to M231 return to the low level and the gates PC0R of the clamp switches N55 to N57 become high level, the gates PSEL1 of the selection MOS transistors M411 to M431 become high level.

  As a result, the reset signal (noise signal) on which the reset noise is superimposed is read to the vertical signal lines V1 to V3 and clamped to the clamp capacitors C01 to C03. At the same time, the gates PT of the transfer switches N58 to N510 become high level, and the signal holding capacitors CT1 to CT3 are reset to the clamp voltage.

  Next, the gate PC0R of the clamp switches N55 to N57 returns to the low level. Next, the gates PTX1 of the transfer MOS transistors M111 to M131 are set to the high level, and the optical signal charges of the photodiodes D11 to D31 are transferred to the gates of the amplification MOS transistors M311 to M331. Read to V3.

  Next, after the gate PTX1 of the transfer MOS transistors M111 to M131 returns to the low level, the gate PT of the transfer switches N58 to N510 goes to the low level. As a result, the change (optical signal) from the reset signal is read out to the signal holding capacitors CT1 to CT3.

  With the operations so far, the optical signals of the pixel cells connected to the first row are held in the signal holding capacitors CT1 to CT3 connected to the respective columns.

  Next, the gates PRES1 of the reset MOS transistors M211 to M231 and the gates PTX1 of the transfer MOS transistors M111 to M131 become high level, and the optical signal charges of the photodiodes D11 to D31 are reset.

  Thereafter, the gates of the horizontal transfer switches N511 to N513 in each column are sequentially set to a high level by signals supplied from the horizontal scanning circuit block 5 and transmitted through the signal lines H1 to H3, and are held in the signal holding capacitors CT1 to CT3. The voltage is sequentially read out to the horizontal output line and sequentially output to the output terminal OUT.

  The horizontal output line is reset to the reset voltage Vres by the reset switch N514 between the signal readings of each column. Thus, reading of the pixel cells connected to the first row is completed. Similarly, the signals of the pixel cells connected in the second and subsequent rows are sequentially read by signals from the vertical scanning circuit block, and the reading of all the pixel cells is completed.

As described above, the conventional circuit of FIG. 4 takes a time like Thblnk of FIG. 2 at the timing shown in “first half of first row and first half of second row (1) to (9)” of FIG. Therefore, there was a limit to speeding up.
JP-A-10-155100

  Therefore, as shown in FIG. 7, if Thblnk is performed behind the Tread (background) so that the actual Tread time can be made zero, 10 frames per second can be achieved in 8 channels even with 10 million pixels as in the above example. Become so.

  For example, if Thblnk can be executed in the background, even with 8 channels, Tread of the entire screen is approximately 80 ms and Tvblnk is approximately 20 ms, so that one frame is 100 ms.

  For this purpose, basically, as shown in FIG. 8, CT is provided for a plurality of rows, and signals from the pixel portion are transferred to the other CT row in a row while one CT row is being read sequentially. To reduce the horizontal blanking time. Details will be described later with reference to FIG. 1, but the outline will be described with reference to FIG.

  Two sets of memory units CT for odd-numbered rows and even-numbered rows are provided for the two-dimensionally arranged pixel units, and the vertical selection SR (shift register) is sequentially scanned from the top of the screen in the vertical direction and transferred to the CT unit. Select the power line. For example, if the odd-numbered n-th row data is already in the CT section (for odd-numbered rows) and the pixel output is sequentially read out while scanning in the horizontal direction with the horizontal selection SR (shift register), In the background), the signals of the even number n + 1 rows are collectively transferred to the even-number CT section. By doing this, two sets of CT sections are required for odd rows and even rows, but since the size of the CT portion is small compared to the chip size of the pixel portion, the chip size becomes much larger even if it is extra. Rather, the benefits of speeding up are greater.

  However, in order to shorten the time of FIG. 8, the output type of the type of FIG. Current noise violently shakes the power supply and ground of the sensor chip substrate in a short time, and the common-mode noise jumps into the Tread pixel readout signal. It is essential to take measures against this. As shown in FIG. 6, the negative input of the output amplifier is directly affected by the voltage fluctuation of the power supply and ground around the aluminum wiring, but is connected to the reference voltage Vres of the positive input. Similarly, noise is not applied due to the difference in length. Therefore, noise jumps in the power supply and ground caused by current noise generated by collective charge transfer to the (n + 1) th row CT differs between the negative and positive inputs of the output amplifier. As a result, the output amplifier outputs the correct pixel signal. It becomes impossible to put out.

  4 will be described in more detail with reference to the type of the input section of the output amplifier 51 in FIG. 4. In the conventional technique, the horizontal output lines to which the sources of the horizontal transfer switches N511 to N513 are commonly connected are connected to the gates of the horizontal transfer switches N511 to N513. The signal lines H1 to H3 that drive the gate terminals are capacitively coupled via the inter-source capacitance.

  The horizontal output line overlaps with the wiring of the signal lines H1 to H3 from the horizontal scanning circuit block 5 and is capacitively coupled. Signals passing through the signal lines H1 to H3 are supplied from the power supply and GND of the horizontal scanning circuit block 5, and as a result, are capacitively coupled to the power supply and GND of the horizontal scanning circuit block 5.

  Further, the wiring of the horizontal output line is provided on the semiconductor substrate and is capacitively coupled to the semiconductor substrate. Like the driving method described with reference to FIG. 5, the input terminal is in a high impedance (floating) state at the timing when a signal is read out to the horizontal output line, and is easily affected by disturbance noise due to capacitive coupling.

  In general, the power supply and GND of the horizontal scanning circuit block 5 are often superposed with spike-like noise due to the influence of the through current of the digital circuit, and this noise affects the horizontal output line. As a result, there is a problem that the output waveform (sensor output waveform) of the differential amplifier circuit 51 is affected, and the original subject image cannot be obtained. The circuit feature of being weak against disturbance noise exposes the worsening of noise by performing Thblnk and Thread in parallel.

  Therefore, an object of the present invention is to achieve both high speed and low noise by providing a solid-state imaging device that does not affect the output of a differential amplifier circuit such as noise.

  In order to solve the above-described problem, in an imaging device using a row scanning solid-state imaging device, at least two row memory groups are provided, and the first row memory group in which the image data of the nth row is stored is sequentially While the image data of each pixel is being output while scanning the columns, the image data of the (n + 1) th row is stored in the second row memory group in parallel, thereby reducing the total readout time. The light from the subject is converted into a signal charge by a plurality of photoelectric conversion elements, and the signal charge converted by each photoelectric conversion element is amplified by a differential amplifier circuit to which a reference signal is supplied. In a solid-state imaging device that generates an image signal, a coupling capacitor between a first output line that sequentially outputs a signal from each of the photoelectric conversion elements to the differential amplifier circuit and a desired signal line, and the differential amplifier circuit And combining the coupling capacitance between the desired signal line and the second output line for supplying the reference signal.

  That is, according to the present invention, a dummy antenna line is put on the input signal to the differential amplifier circuit, and noise or the like is superimposed on both inputs in the same manner, so that the difference or the like is differentiated by the differential amplifier circuit. Noise and the like are removed from the output signal of the dynamic amplification circuit.

  According to the present invention, the dummy common-mode noise detection antenna line is placed on the input signal to the differential amplifier circuit that amplifies the signal charge converted by each photoelectric conversion element, and noise or the like is applied in the same manner as the signal line. Since they are superposed, noise or the like is differentiated by the differential amplifier circuit, and noise or the like is removed from the output signal. For this reason, while reducing the transfer of noise from CT transfer caused by simultaneously transferring data from the pixel portion to the row memory group CT (corresponding to conventional horizontal blanking) and reading from the row memory group by horizontal scanning in parallel. It was possible to achieve both high speed and low noise.

  This has made it possible to break a large wall that has been a hindrance to speeding up by the multi-channel CMOS image sensor.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to examples.

  FIG. 1 is an equivalent circuit diagram of the solid-state imaging device according to the first embodiment of the present invention. The pixel unit 1, input MOS transistor N51, load MOS transistors N52 to N54, clamp capacitors C01 to C03, clamp switches N55 to N57, transfer switches N58 to N510, and signal holding capacitors CT1 to CT3 in FIG. 1 are the same as those in FIG. It is a configuration. In FIG. 1, parts that are the same as the parts shown in FIG.

  Capacitors CT1 to CT3 for temporarily holding signals are connected to the inverting input terminal (horizontal output line) of the differential amplifier circuit 51 via horizontal transfer switches N511 to N513, and the horizontal output line is connected via a reset switch N514. Connected to the reset voltage Vres.

  The gates of the horizontal transfer switches N511 to N513 are connected to the signal lines H1 to H3 and connected to the horizontal scanning circuit block 5.

  Switches N11 to N13 whose drains are connected to the reset voltage Vres are connected to the non-inverting input terminal of the differential amplifier circuit 51, and the gates of the switches N11 to N13 are the signal lines H1 to H5, like the horizontal transfer switches N511 to N513. Connected to H3.

  Further, the normal input terminal is connected to the reset voltage Vres via the reset switch N514.

  Although not particularly limited, it is desirable that the horizontal transfer switches N511 to N513 and the switches N11 to N13 and the reset switches N514 and N14 are switches having the same shape.

  Further, in FIG. 1, for the sake of simplicity, a two-dimensional pixel array of 3 rows and 3 columns is used. However, it is not limited to this size, and it is needless to say that a similar configuration can be adopted for a one-dimensional linear sensor. .

  Next, the operation of the solid-state imaging device of this embodiment will be described. The operation until the signal holding capacitors CT1 to CT3 hold them is the same as the description based on FIG.

  The signals held in the signal holding capacitors CT1 to CT3 are supplied from the horizontal scanning circuit block 5 and transmitted through the signal lines H1 to H3, so that the gates of the horizontal transfer switches N511 to N513 in each column are sequentially set to the high level. Read out to output line.

  Further, the gates of the switches N11 to N13 are sequentially turned to a high level by the signals supplied from the horizontal scanning circuit block 5 and transmitted through the signal lines H1 to H3, and the non-inverting input terminal of the differential amplifier circuit 51 is connected to the horizontal output line. The reset voltage Vres is read in synchronization with the timing at which the signal is read.

  The reset switches N514 and N14 reset the horizontal output line and the normal input terminal of the differential amplifier circuit 51 to the reset voltage Vres of the horizontal output line between signal readings of each column. A difference signal between the normal input signal and the inverted input signal is amplified to a desired gain and output to the output terminal OUT.

  In such an operation, for example, a signal leaked from the horizontal scanning circuit block 5 and transmitted through the signal lines H1 to H3 or a horizontal output line reset signal PCHRES occurs in the horizontal output line. The horizontal output line is capacitively coupled to the signal lines H1 to H3 by the gate-source capacitances of the horizontal transfer switches N511 to N513.

  Since the signals supplied from the horizontal scanning circuit block 5 and transmitted through the signal lines H1 to H3 are sequentially at a high level, the low level supplied from the GND of the horizontal scanning circuit block 5 is output for most of the period.

  By the way, in the present embodiment, the reset switch N14 and switches N11 to N13 in which the same signal as that of the horizontal transfer switch is input to the gate are connected to the normal input terminal of the differential amplifier circuit 51 as well as the horizontal output line. Therefore, the normal input terminal is also affected by clock leaks and spike-like noise in the same manner as the inverting input terminal.

  These noise components are in-phase components between the inverting input terminal and the non-inverting input terminal, and are removed by the differential amplifier circuit 51, and therefore do not affect the output terminal OUT.

  The circuit block 52 indicates a block including a CT, a horizontal readout scanning unit, and a readout differential amplifier. The internal configuration around this is almost the same as the conventional circuit of FIG. 4 except for the input format of the amplifier. In addition to this, in FIG. 1, another set of these 52 blocks is provided in order to increase the speed. This is the circuit block 62. The configuration requirements of the circuit block 62 are exactly the same as those of the circuit block 52, and only the input signal is different. When both are compared, PT2 is PT with respect to PT, and OUT2 with respect to OUT. If 52 circuit blocks are circuit blocks for odd rows, 62 circuit blocks are circuit blocks for even rows.

Next, FIG. 9 will be described.
This is also basically the same as the timing described with reference to FIG. 5, but reading by the horizontal scanning unit and transfer to the CT group by the vertical scanning unit are performed simultaneously in parallel. In FIG. 5, the first row is divided into the first half and the second half, and signals such as PRES1, PSEL1, PTX1, PC0R, and PT change drastically in the first half, and signal charges are passed from the pixel portion to the CT group through the vertical output line group. H1, H2, H3, PCHRES, and the like change drastically in the transfer timing and the latter half, and reading is performed by the operation of the horizontal scanning unit. Both of them are performed alternately in each row.

  On the other hand, in FIG. 9, both of them are performed in parallel. For example, when the timings (1) to (9) in the second row in FIG. 9 are seen, PRES2, PSEL2, PTX2, PC0R, and PT2 move violently. H1, H2, H3, and PCHRES are moving violently at the same time. This is because the pixel data of the first row is included in the circuit block 52 in parallel while the pixel signals of the second row are being transferred to the CT group for even rows included in the 62 circuit blocks. That is, it is read out from the OUT terminal while being horizontally scanned from the row CT group.

  Conversely, at the timing of the third row (1) to (9) in FIG. 9, H61, H62, H63, and PCHRES are simultaneously moving violently while PRES3, PSEL3, PTX3, PC0R, and PT are moving violently. This is because the pixel data of the second row is included in the circuit block 62 in parallel while the pixel signal of the third row is transferred to the CT group for odd rows included in the circuit block of 52. That is, it is read from the OUT2 terminal while being horizontally scanned from the CT group for rows.

By repeating these operations one after another, it can be seen that the state is halved in FIG. 9 as compared to FIG.
In this example, there are two sets of blocks of odd rows and even rows, but if the reading of the horizontal scanning unit is further speeded up by multi-channeling, it is possible to have two sets or more.

1 is an equivalent circuit diagram of a solid-state imaging device according to an embodiment of the present invention. It is a schematic timing diagram of the conventional CMOS type solid-state imaging device. It is the graph showing the frame speed taken for multi-channeling of the conventional CMOS type solid-state imaging device. (Solid line Conventional frame speed, broken line Frame speed proposed by the present invention) It is an equivalent circuit diagram of a conventional CMOS solid-state imaging device. 5 is a timing chart showing an operation of the CMOS type solid-state imaging device shown in FIG. 5 is a schematic plan view of the horizontal transfer switches N511 to N513, the reset switch N514, the horizontal scanning circuit block 5, and the differential amplifier circuit 51 of FIG. FIG. 3 is a schematic timing diagram aimed at by the present invention. 1 is a schematic circuit block diagram aimed at by the present invention. FIG. 3 is a timing chart showing the operation of the CMOS solid-state imaging device of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel part 2 Vertical scanning circuit block 4 GND line 5 Horizontal scanning circuit block 51 Differential amplifier circuit C01-C03 Clamp capacity | capacitance CT1-CT3 Signal holding capacity | capacitance N51 Input MOS transistor N52-N54 Load MOS transistor N55-N57 Clamp switch N58-N510 Transfer switch N511-513 Horizontal transfer switch N514 Reset switch 52 Circuit block for odd rows 62 Circuit block for even rows

Claims (2)

  In an imaging device using a row scanning type solid-state imaging device, each pixel is sequentially scanned from the first row memory group having at least two row memory groups and storing image data of the nth row. A solid-state imaging device characterized by shortening the total readout time by simultaneously storing the image data of the (n + 1) th row in the second row memory group in parallel with the output of the image data.   The column scanning readout circuit from the first row memory group is adjacent to the first row memory group in order to prevent electrical noise associated with the store operation to the second row memory group performed in parallel. A second dummy output line having a role of a noise detection antenna for picking up surrounding noise is provided adjacent to the first output line for reading provided adjacent to the first output line, and the first and second output lines are provided. A solid-state imaging device that reduces common-mode noise by taking a differential signal.