JP2006093590A - Semiconductor manufacturing method and mask material - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which enables transfer with higher precision ultra-fine resist pattern by reducing light reflectivity of lower-layer metal and secures selection ratio of masks and metal to form ultra-fine metallizing by implementing the metal etching via a hard mask of an oxide film. <P>SOLUTION: The semiconductor device manufacturing method comprises of the steps of forming, on a metal laminated film, an oxide film layer including a plurality of layers of plasma SiON films 6, 7 of different refractive indices as a reflection preventing film for controlling light reflection from the lower-layer, forming a resist mask 8 to which a metallizing pattern is implemented on the plasma SiON film 7 with the exposure process, forming a metallizing pattern on the oxide film layer with the etching via the resist mask 8, and forming a metallizing pattern to the metal laminated film with the etching process with the oxide film layer to which the metallizing pattern is formed used as the mask material. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a semiconductor device having an improved hard mask structure for forming metal wiring and a mask material suitably used for the method.

  In order to form a fine metal wiring, it is necessary to form a fine and thin resist pattern directly on the metal due to optical diffraction limits and the like. However, since a sufficient etching selection ratio cannot be obtained between the resist and the metal, the thin resist pattern may disappear during the etching, resulting in a defective shape of the metal wiring. In addition, during exposure, the resist is thinned or lost due to reflection caused by the unevenness of the underlying metal, and therefore, in order to form a fine resist pattern, it is necessary to reduce the light reflectance of the underlying metal.

In order to solve such a problem, for example, a wiring forming method as disclosed in Patent Document 1 has been proposed. In this method, a TiN film layer is provided on a metal wiring layer, a P-SiON (plasma SiON) film and a P-SiO ₂ (plasma SiO ₂ ) film are formed thereon, and a photoresist is provided as a mask. Used as The TiN film, the P—SiON film, and the P—SiO ₂ film are used by being laminated on the metal wiring layer, thereby functioning as an inorganic antireflection film and suppressing halation caused by unevenness of the underlying metal.

  Further, when the above-described photoresist underlayer film is dry-etched, the etching selectivity with respect to the photoresist can be adjusted by changing the composition of the etching gas.

JP 2000-216161 A

In the mask structure disclosed in Patent Document 1, the adhesion between the photoresist and P-SiO ₂ is poor, and in the worst case, the photoresist pattern is peeled off and the fine resist pattern is transferred with high accuracy. May not be possible.

  Further, the P—SiON film has a small etching selectivity with respect to the metal (including TiN film layer) laminated film. For example, there is a possibility that the shape defect of the metal wiring may occur due to the shaving of the resist pattern.

  The present invention has been made to solve the above-described problems. It reduces the light reflectivity of the underlying metal to transfer a fine resist pattern with high accuracy, and performs metal etching using a hard mask of an oxide film. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a fine metal wiring while ensuring a mask-to-metal etching selectivity, and to obtain a mask material suitably used therefor.

  According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: providing a mask material on a metal laminated film; and forming a metal wiring pattern on the metal laminated film by etching through the mask material. Forming an oxide laminated film including a plurality of plasma SiON films having different refractive indexes as an antireflection film for suppressing reflection on the metal laminated film; and exposing the metal on the plasma SiON film of the oxide laminated film by an exposure process. A step of forming a resist mask with a wiring pattern, a step of forming a metal wiring pattern on the oxide multilayer film by etching through the resist mask, and an oxide multilayer film on which the metal wiring pattern is formed as a mask material Forming a metal wiring pattern on the metal laminated film by etching.

  According to the present invention, in a method of manufacturing a semiconductor device in which a mask material is provided on a metal laminated film and a metal wiring pattern is formed on the metal laminated film by etching through the mask material, the reflection that suppresses light reflection from the base A step of forming an oxide laminated film including a plurality of plasma SiON films having different refractive indexes as a prevention film on the metal laminated film, and a metal wiring pattern was applied on the plasma SiON film of the oxide laminated film by exposure processing A step of forming a resist mask, a step of forming a metal wiring pattern on the oxide multilayer film by etching through the resist mask, and a metal multilayer film by etching using the oxide multilayer film on which the metal wiring pattern is formed as a mask material Forming a metal wiring pattern on the substrate, so that the light reflectivity of the underlying metal is reduced and finer The resist pattern is transferred with high accuracy, and metal etching is performed through a hard mask of an oxide film, so that an etching selection ratio between the mask and the metal can be secured and a fine metal wiring can be formed. .

Embodiment 1 FIG.
FIG. 1 is a schematic cross-sectional view of a device in each manufacturing process in the method for manufacturing a semiconductor device according to the first embodiment of the present invention, from the manufacturing process shown in (a) to the manufacturing process shown in (c). Shall proceed. As shown in FIG. 1A, a metal laminated film is formed on the interlayer insulating film 1. First, the barrier metal layer 2 is formed on the interlayer insulating film 1, and the conductor layer 3 is formed thereon. As a material of the conductor layer 3, a case where an aluminum material (AlCu) generally used as a metal wiring material is used will be described as an example.

  In this case, as the barrier metal layer 2, for example, a TiN / Ti laminated film is used. This is because the lowermost Ti layer in the TiN / Ti laminated film has the effect of improving the film quality (crystal size, crystal orientation, etc.) of the AlCu film formed as the conductor layer 3 on the upper layer. In addition, the TiN film layer interposed between the Ti layer and the AlCu film layer has an effect of suppressing the diffusion of Ti from the Ti layer to the AlCu film layer.

  In the first embodiment, the film thickness of the conductor layer 3 made of an aluminum material is assumed to be 150 to 220 nm. The reason why the thickness is increased is to reduce the wiring resistance. The film thickness upper limit value of 220 nm indicates the upper limit of application of the hard mask structure according to the present embodiment (the dry etching possible range). In addition, the thinner one can be adjusted by increasing the amount of metal etching over-etching, increasing the degree of freedom.

  Further, the TiN / Ti laminated film 4 is also formed on the conductor layer 3. This is because the TiN / Ti laminated film 4 suppresses the occurrence of electromigration (hereinafter abbreviated as EM) when via holes are connected to the AlCu film serving as the conductor layer 3 and improves the reliability thereof. . In an EM test in which the upper aluminum wiring and the lower aluminum wiring are connected by via holes, EM is generally generated in the AlCu layer of the aluminum wiring immediately below the via holes, but no EM is generated in the TiN and Ti layers. Therefore, electrical conduction can be ensured by the TiN / Ti layer even after EM is generated in the AlCu layer serving as the conductor layer 3.

  Subsequently, a P-SiO film (plasma oxide film) 5 having a thickness of 90 to 110 nm is formed on the metal laminated film (TiN / Ti / AlCu / TiN / Ti film in the illustrated example) laminated as described above. Form.

A first P-SiON (for example, refractive index n = 2.10, absorption coefficient k = 1.20) film 6 is formed on the upper layer of the P-SiO film 5 to a thickness of about 47 to 53 nm. A P-SiON (for example, refractive index n = 2.00, absorption coefficient k = 0.35) film 7 is formed to a thickness of about 27 to 33 nm. The P-SiON films 6 and 7 can have different film qualities and different refractive indexes n by changing the gas flow rate ratio of SiH ₄ / N ₂ O during film formation. Thereafter, a photoresist is applied to the upper layer of the P-SiON film 7, and exposure and development are performed to form a resist pattern 8.

Thus, in the present embodiment, unlike the configuration disclosed in Patent Document 1, the resist pattern 8 is formed not on the P-SiO ₂ film but on the P-SiON film 7. This is a configuration unique to the present invention that solves the problem of adhesion (adhesiveness) between the base and the photoresist, which is a problem in the conventional manufacturing method represented by Patent Document 1.

One of the factors affecting the adhesion to the photoresist is the surface condition of the substrate. For example, the moisture absorption of the substrate and the adsorption of inorganic ions cause the adhesion to the photoresist to deteriorate. Here, in the conventional P—SiO ₂ (P—SiO) film, the surface thereof is hydrogen-terminated, and has high hygroscopicity because it exhibits hydrophilicity.

In contrast, in the present invention, since a hydrophobic P-SiON film having a surface terminated with oxygen or nitrogen is used, it is hard to absorb moisture as compared with the P-SiO ₂ film, and the adhesion to the photoresist. Can be significantly improved.

Conventionally, an anti-reflective layer (ARL) is formed by combining a P-SiO ₂ film and a P-SiON film having different refractive indexes made of different materials. In order to use the hydrophobic P-SiON film as described above, the two layers of P-SiON films are made to function as antireflection films by changing their film qualities to have different refractive indexes.

  With the two-layer antireflection film composed of the P—SiON films 6 and 7 having different refractive indexes n, the light reflectance of the base metal becomes approximately 0% during exposure. Thereby, the influence of scattered light from the base metal is reduced, and a fine pattern (in the example shown, a 0.2 μm pitch) can be formed.

  Next, in the process shown in FIG. 1B, the P-SiON / P-SiON / P-SiO film is etched out of the laminated film described above using the resist pattern 8 formed in the above-described process as a mask. FIG. 1B shows a configuration when the resist pattern 8 is removed after this etching process.

  Subsequently, in the step shown in FIG. 1C, the P-SiON / P-SiON / P-SiO film (oxide stacked film) patterned by the resist pattern 8 formed in the above-described step is used as a hard mask. Then, the lower metal laminated film (TiN / Ti laminated film / AlCu film / TiN / Ti laminated film) (metal laminated film) is etched. When this etching is completed, the P-SiON / P-SiON film having a small etching selection ratio with respect to the aluminum material of the three-layer hard mask described above disappears, and only the P-SiO film remains (see FIG. 1C). ).

  As described above, when metal etching is performed using a hard mask made of a three-layer oxide film, variations in the film thickness of the lowermost P-SiO film cause variations in the light reflectance of the underlying layer during exposure. Therefore, in the present invention, even if the film thickness of the lowermost P-SiO film is varied by adjusting the refractive index by changing the film quality of the upper two P-SiON films, there is an influence at the time of exposure. It is possible to suppress variations in the light reflectivity of the base to a level that does not exist.

  In the metal etching described above, considering the embedding of an oxide film or the like between the metal layers after etching, it is better that the remaining film of the P-SiO film is smaller. However, if the amount is too small, a problem of shoulder shaving of the metal wiring occurs. In the configuration shown in the drawing, it is desirable to leave about 20 to 40 nm of the P-SiO film in consideration of embedding of an oxide film between the metal layers after etching and the shoulder cutting of the metal wiring during the metal etching.

  In this way, the oxide film constituting the three-layer hard mask disappears leaving one layer and the film thickness is reduced, so that the aspect ratio of the wiring pattern is reduced, and from the conductor layer 3 which is a subsequent process. It is possible to easily embed an interlayer insulating film between the metal wiring layers.

  As described above, according to the first embodiment, an oxide film layer (P-SiON / P) containing a plurality of plasma SiON films 6 and 7 having different refractive indexes as antireflection films for suppressing light reflection from the base. (P-SiON / P-SiO) (oxide laminated film) is formed on the metal laminated film (TiN / Ti / AlCu / TiN / Ti) (metal laminated film) and on the plasma SiON film 7 by exposure treatment. A step of forming a resist mask 8 provided with a metal wiring pattern; a step of forming a metal wiring pattern on an oxide film layer by etching through the resist mask 8; and an oxide film layer on which the metal wiring pattern is formed as a mask material Forming a metal wiring pattern on the metal laminated film by performing the etching, and reducing the light reflectivity of the underlying metal to form a fine resist A turn while transferring with high accuracy, it is possible to form a fine metal wire to secure the etching selectivity of the mask and the metal by carrying through a hard mask oxide film metal etch.

  As a modification of the structure shown in the above embodiment, a P-TEOS (Tetra-Ethyl-Orso-Silicite) film formed by plasma CVD or an HDP-CVD (High Density Plasma-) is used as the lowermost layer of the three-layer hard mask. The same effect can be obtained even when the USG film is changed to the CVD method. These oxide films are selected because the film formation temperature is 300 to 450 ° C. and the film stress (stress) is similar, so that the heat and stress applied to the metal wiring are relatively close.

  In the above embodiment, an example in which the antireflection film is formed by two layers of P-SiON films has been shown. However, if light reflection from the base metal can be prevented, three or more layers of P-SiON films are formed. An antireflection film may be used.

Embodiment 2. FIG.
FIG. 2 is a schematic cross-sectional view of the device in each manufacturing process in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, and the process proceeds from the manufacturing process shown in (a) to the manufacturing process shown in (d). Shall be. As shown in FIG. 2A, a metal laminated film is formed on the interlayer insulating film 1. First, the barrier metal layer 2 is formed on the interlayer insulating film 1, and the conductor layer 3 is formed thereon. As a material of the conductor layer 3, a case where an aluminum material (AlCu) generally used as a metal wiring material is used will be described as an example.

  In the second embodiment, the film thickness of the conductor layer 3 made of aluminum material is assumed to be 150 to 220 nm. The reason why the thickness is increased is to reduce the wiring resistance. The film thickness upper limit value of 220 nm indicates the upper limit of application of the hard mask structure according to the present embodiment (the dry etching possible range). In addition, the thinner one can be adjusted by increasing the amount of metal etching over-etching, increasing the degree of freedom.

  As the barrier metal layer 2, for example, a TiN / Ti laminated film is used. A TiN / Ti laminated film 4 is also formed on the conductor layer 3. A P-SiON film (refractive index n = 2.10, absorption coefficient k = 1.20) 6a on the metal laminated film (TiN / Ti / AlCu / TiN / Ti film in the example shown) formed in this way 6a Is formed with a film thickness of about 47 to 53 nm. Further, a P-SiO film (plasma oxide film) 5a is formed on the upper layer with a thickness of about 90 to 110 nm, and further P-SiON (refractive index n = 2.00, absorption coefficient k = 0.35) is formed on the upper layer. ) The film 7 is formed with a film thickness of about 27 to 33 nm. Thereafter, a photoresist is applied to the upper layer of the P-SiON film 7, and exposure and development are performed to form a resist pattern 8.

Thus, also in the present embodiment, unlike the configuration disclosed in Patent Document 1, the resist pattern 8 is formed not on the P—SiO ₂ film but on the P—SiON film 7. This is a configuration unique to the present invention that solves the problem of adhesion (adhesiveness) between the base and the photoresist, which is a problem in the conventional manufacturing method represented by Patent Document 1. That is, also in this embodiment, the adhesion with the photoresist is improved by using a hydrophobic P-SiON film whose surface is terminated with oxygen or nitrogen.

  The two layers of anti-reflective layers (ARL: Anti-Reflective Layer) composed of P-SiON films 6a and 7 having different refractive indexes n make the light reflectivity of the underlying metal almost 0% during exposure. Thereby, the influence of scattered light from the base metal is reduced, and a fine pattern (in the example shown, a 0.2 μm pitch) can be formed.

  Next, in the process shown in FIG. 2B, the P-SiON / P-SiO / P-SiON film is etched out of the laminated film described above using the resist pattern 8 formed in the above-described process as a mask. FIG. 2B shows a configuration when the resist pattern 8 is removed after this etching process.

  Subsequently, in the process shown in FIG. 2C, the P-SiON / P-SiO / P-SiON film patterned by the resist pattern 8 formed in the above-described process is used as the (oxide stacked film) hard mask. Then, the lower metal laminated film (TiN / Ti laminated film / AlCu film / TiN / Ti laminated film) is etched.

  When this etching is completed, the P-SiON film 7 having a small etching selection ratio with respect to the aluminum material of the three-layer hard mask described above disappears, and the intermediate P-SiON film 5a and the lowermost P-SiON film 6a. Remains (see FIG. 2C). In the illustrated example, the intermediate P-SiO film 5a is left at about 20 to 40 nm, and the lowermost P-SiON film 6a is left at the original film thickness of about 47 to 53 nm.

  2D, a metal interlayer insulating film (for example, HDP-USG) 9 and a metal interlayer insulating film (for example, P-TEOS) 10 are formed on the metal wiring layer formed in the above-described process. Form a film. Thereafter, etching (oxide film etching) for forming a hole (hereinafter referred to as a via hole) 11 for connecting the upper wiring and the lower metal wiring of the interlayer insulating film 10 is performed.

  At this time, the etching is temporarily performed up to the P-SiON film 6a on the metal wiring (TiN / Ti / AlCu / TiN / Ti film) using the difference in etching rate (etching selection ratio) between P-SiO and P-SiON. Stop. Thereafter, the etching step is switched to etch the P-SiON film 6a so that the bottom of the via hole can be easily stopped by the TiN layer in the lower metal wiring, and the reliability of the via hole (electromigration resistance) is improved. Can do.

  If the via hole etching by the oxide film etching is stopped on the TiN of the metal wiring from the beginning without providing the P-SiON film 6a immediately above the TiN layer of the metal wiring, the variation in the thickness of the oxide film is caused by the TiN layer. Must be adjusted to absorb. For this reason, in a region where the oxide film is thin, the via hole 11 may penetrate the TiN layer.

  Therefore, in the present invention, the P-SiON film 6a is formed on the TiN layer of the metal wiring, and the oxide film etching is temporarily stopped by the P-SiON film 6a to cancel (correct) the variation in the thickness of the oxide film. By switching the etching steps and etching the P-SiON film 6a, the bottom of the via hole is stopped with TiN on the lower layer wiring.

  As described above, according to the second embodiment, in addition to the effects of the first embodiment, the thickness of the P-SiON film used as a hard mask when forming the via hole 11 for connecting the wiring layers is increased. By using it as a cushion for absorbing variations in the thickness of the via hole, it is possible to easily stop the via hole bottom with TiN of the metal wiring, and to improve the reliability (electromigration resistance) of the via hole.

  As a modification of the structure according to the above-described embodiment, even if the three hard mask intermediate layers are changed to a P-TEOS film by plasma CVD or a USG film by HDP-CVD (High Density Plasma-CVD). The effect of can be obtained. For example, P-SiON / P-TEOS / P-SiON / metal wiring layer, each oxide film having a thickness of 30 nm, 100 nm, 50 nm, P-SiON / USG / P-SiON / metal wiring layer, It can be considered that each oxide film has a thickness of 30 nm, 100 nm, and 50 nm, respectively.

1 is a schematic cross-sectional view of a device in each manufacturing step in a method for manufacturing a semiconductor device according to a first embodiment of the present invention. It is a schematic sectional drawing of the apparatus in each manufacturing process in the manufacturing method of the semiconductor device by Embodiment 2 of this invention.

Explanation of symbols

  1 interlayer insulating film, 2 barrier metal layer, 3 conductor layer, 4 TiN / Ti laminated film, 5,5a P-SiO film, 6,6a P-SiON film, 7 P-SiON film, 8 photoresist, 9 interlayer Insulating film, 10 interlayer insulating film, 11 via hole.

Claims (4)

In a method for manufacturing a semiconductor device, a mask material is provided on a metal laminated film, and a metal wiring pattern is formed on the metal laminated film by etching through the mask material.
Forming an oxide multilayer film including a plurality of plasma SiON films having different refractive indexes on the metal multilayer film as an antireflection film for suppressing light reflection from the base;
Forming a resist mask having the metal wiring pattern on the plasma SiON film of the oxide laminated film by an exposure process;
Forming the metal wiring pattern in the oxide multilayer film by etching through the resist mask;
Forming a metal wiring pattern on the metal multilayer film by etching using the oxide multilayer film on which the metal wiring pattern is formed as the mask material.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the oxide multilayer film is formed by forming a plasma SiO film on an intermediate layer sandwiched between plasma SiON films or a lowermost layer of the multilayer film composed of the plasma SiON films. Forming an interlayer insulating film while leaving the mask material after forming the metal wiring pattern on the metal laminated film by etching using the oxide laminated film on which the metal wiring pattern is formed as a mask material;
In forming a via hole from the upper layer to the metal wiring of the lower metal laminated film via the interlayer insulating film by etching, the formation of the via hole is temporarily stopped at the oxide laminated film of the mask material on the metal wiring. 2. The semiconductor device according to claim 1, further comprising a step of switching the etching step so as to correct a variation in the thickness of the oxide film in the oxide laminated film to form the via hole up to the metal wiring. Manufacturing method. In a mask material for forming a metal wiring pattern on a metal laminated film of a semiconductor device by etching,
An antireflection film composed of a plurality of plasma SiON films each having a different refractive index and suppressing light reflection from the underlayer, and an intermediate layer sandwiched between the plasma SiON films constituting the antireflection film or a laminated film composed of the plasma SiON films Consisting of an oxide film provided on the bottom layer of
A mask material in which a resist mask having the metal wiring pattern formed thereon by an exposure process is formed on the plasma SiON film, and the metal wiring pattern is formed by etching through the resist mask.

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