JP2006093244A - Semiconductor package and its design method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package of a BGA method which can be operated at high speed by relaxing the timing restriction of a signal. <P>SOLUTION: The semiconductor package 10 is provided with a semiconductor chip 11 having a plurality of pads 13 arranged in a row and a package substrate 12 wherein a plurality of signal balls 20a are connected with the pads 13 via signal wires 16, respectively, and they are arranged in an array. The center 34 of a signal ball array is located displaced by a specified quantity (L) from the center 31 of the semiconductor chip 11 in the arrangement direction of the pad 13. Among a specific signal wiring group included in the signal wiring, the length of the longest signal wiring that becomes largest when assuming that the center 31 of the semiconductor chip 11 and the center 34 of the signal ball array do not deviate, and becomes smaller than that in the assumed case that the centers do not deviate, because the center 34 of the signal ball array are displaced from the center 31 of the semiconductor chip 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor package and a design method thereof, and more particularly to a technique for improving electrical characteristics of a BGA type semiconductor package.

  One method for attaching a semiconductor package containing a semiconductor chip to a mounting board is a BGA system in which connection pins are made of metal balls and arranged in an array. The BGA method has features such that it is easy to increase the number of pins, and the semiconductor package attached to the mounting substrate can be made as small as the chip size. For this reason, it is frequently used in portable electronic devices such as cellular phones, for which high-density mounting is particularly required.

  A ball array in a BGA type semiconductor package may be composed of only a signal ball connected to a pad of a semiconductor chip via a signal wiring, or may have a support ball in addition to such a signal ball. The support balls are disposed in a peripheral region of the semiconductor package where no signal ball is disposed in order to ensure the bending strength of the semiconductor package.

  FIGS. 11A and 11B show the front surface of the semiconductor package and the connection surface (rear surface) to the mounting substrate, respectively, for the BGA type semiconductor package in which the ball array is composed only of signal balls. FIG. 12 shows a back surface of a semiconductor package of a BGA type semiconductor package in which a ball array is composed of signal balls and support balls. In general, in the semiconductor packages 51 and 52, the center 31 of the semiconductor chip 11, the center 32 of the package substrate 12, and the center 33 of the array of ball arrays are matched from the viewpoint of strength. The semiconductor package shown in FIGS. 11 and 12 is a BGA type semiconductor package that is particularly miniaturized, and is also referred to as a μBGA type semiconductor package.

The arrangement position of the support ball 20b is defined in the DDR2 standard of JEDEC (Joint Electron Device Engineering Council). In the standard, for example, when the standard ball interval (pitch) is 0.8 mm and the bit length of the data signal of the semiconductor chip of the standard is 4 bits (x4) and 8 bits (x8), adjacent signal balls In the case of 16 bits (x16), it is arranged at a position of 2.4 mm from the adjacent signal ball 20a, that is, at a position of 3 pitches.
Japanese Patent Laying-Open No. 2003-7971 (FIG. 1)

  The present inventor gives a signal delay time of a specific signal wiring group such as an address signal line and a data signal line to the timing design of the semiconductor device in the process of improving the electrical characteristics of the BGA type semiconductor package. Focusing on the constraints, we focused on reducing the timing constraints by shortening the length of the longest signal wiring in the signal wiring group, which has particularly severe timing constraints in design.

  In view of the above, an object of the present invention is to provide a semiconductor package capable of high-speed operation by relaxing signal timing constraints in a BGA semiconductor package.

In order to achieve the above object, a semiconductor package according to the present invention includes a semiconductor chip including a plurality of pads arranged in a row,
In a semiconductor package comprising a package substrate having a signal ball array including a plurality of signal balls connected to the pads via signal wirings and arranged in an array,
The center of the signal ball array is displaced from the center of the semiconductor chip by a predetermined shift amount (L) along the arrangement direction of the pads or in a direction orthogonal to the arrangement direction,
Of the specific signal wiring group included in the signal wiring, the length of the longest signal wiring that is the longest when it is assumed that the center of the semiconductor chip and the center of the signal ball array are not shifted is the signal ball. Since the center of the array is deviated from the center of the semiconductor chip, it is shorter than a case where it is assumed that it is not deviated.

The semiconductor package designing method according to the present invention includes a semiconductor chip having a plurality of pads arranged in a row, and a plurality of signals connected to the pads via signal wirings and arranged in an array. In a method of designing a semiconductor package comprising a package substrate having a signal ball array including balls,
In arranging the semiconductor chip and the package substrate,
In a state where the center of the signal ball array and the center of the semiconductor chip are matched, the longest signal wiring that is the longest among the specific signal wiring groups included in the signal wiring is extracted,
The center of the signal ball array is shifted from the center of the semiconductor chip by a predetermined shift amount (L) so that the length of the longest signal wiring is shortened.

  According to the semiconductor package of the present invention, compared to the case where the center of the signal ball array is not shifted from the center of the semiconductor chip, the length of the longest signal wiring belonging to the specific signal wiring group is shortened, and the maximum signal delay is achieved. The value can be suppressed. As a result, the timing constraint can be relaxed, and a semiconductor package that operates at high speed can be obtained.

  In a preferred embodiment of the semiconductor package of the present invention, the shift amount L is an integral multiple of the arrangement pitch of the signal balls or an integral multiple of 1/2 of the arrangement pitch. When the support balls are provided, the support ball arrangement can be matched with the signal ball arrangement. In this case, when the shift amount L is 0.5, 1, or 1.5 times the arrangement pitch of the signal balls, the length of the longest signal wiring in the wiring group can be shortened. Preferably, the shift amount L is selected so that the longest signal wiring is the shortest, so that the maximum value of the signal delay belonging to the wiring group can be further suppressed.

  In a preferred embodiment of the semiconductor package of the present invention, the package substrate has a support ball in addition to the signal ball. The support ball is separated from the ball array, and the center of the ball array is the semiconductor chip. Is disposed at a position opposite to the direction deviated from the center of the ball array, and is separated from the signal ball disposed at the end of the ball array by a distance of 2L. In the region of the semiconductor package where the signal ball is not disposed, the bending strength of the semiconductor package can be increased. As a result, the mounting reliability of the semiconductor package can be improved.

  In a preferred embodiment of the semiconductor package of the present invention, the distance between the end face of the semiconductor chip and the end face of the package substrate is 0.1 mm or more. By securing an appropriate margin for the dimensions of the semiconductor chip and the package substrate, the mounting reliability of the semiconductor package can be improved.

  In the semiconductor package of the present invention, the semiconductor package is a DRAM, and the signal wiring group is any one of a data signal line group, a clock signal line group, an address signal line group, and a control signal line group. I can do it. For example, in a DRAM, particularly when the delay time of a data signal is a problem in design, paying attention to the data signal line group, the length of the longest signal wiring belonging to the data signal line is minimized. Shift the center of the semiconductor chip. In this way, timing constraints can be relaxed, and high-speed semiconductor device design is facilitated.

  According to the semiconductor package design method of the present invention, it is possible to design the semiconductor package of the present invention that exhibits the above effects. In the present invention, the signal ball is a ball made of metal or the like connected to a signal wiring used for transmission of an electrical signal, and is a concept compared with a support ball that is arranged from the viewpoint of strength and is not connected to the signal wiring. is there. Therefore, the signal ball includes a ball connected to a power supply line or a ground line. The signal wiring includes a power supply line and a ground line.

  Prior to the present invention, the present inventor has considered the following. The inventor first optimizes the length of the signal wiring in the BGA type semiconductor package by appropriately shifting the center of the signal ball array from the center of the semiconductor chip in the direction of pad arrangement or in the direction orthogonal thereto. I came up with what I can do. Here, according to JEDEC's DDR2 standard, the center of the signal ball array is shifted and the support ball is disposed, and the center of the ball array including the signal ball and the support ball is set to coincide with the center of the semiconductor chip and the package substrate. It is possible.

  However, when the present inventor conducted a simulation to examine the relationship between the amount L of the center of the signal ball array and the length of the signal wiring for many BGA semiconductor packages, the signal wiring was optimized. The deviation L at the center of the signal ball array did not match the deviation L according to the JEDEC DDR2 standard. The optimization of the signal wiring can be obtained, for example, by shortening the length of the longest signal wiring that is the longest in a specific signal wiring group by this shift amount L. For example, when the number of signal balls is 60 and the bit length of the signal is 4 bits (x4) and 8 bits (x8), the signal ball shift amount L when the length of the longest signal wiring is the shortest is as follows. When the pitch was larger than 0 pitch and smaller than 2 pitch, the number of signal balls was 84, and the signal bit length was 16 bits (x16), the pitch was larger than 0 pitch and smaller than 1.5 pitch.

  Based on the result of the simulation, the present inventor decided to determine the BGA type semiconductor package as follows. That is, a simulation for obtaining the wiring pattern at that time is performed by shifting the center of the signal ball array to the center of the semiconductor chip at various positions in the pad arrangement direction or the orthogonal direction thereof. The length of the longest signal wiring belonging to a specific wiring group for which the signal delay is most desired to be reduced among the wiring groups such as the data signal line group, the clock signal line group, the address signal line group, and the control signal line group. The positional relationship between the signal ball and the pad is determined so that the length becomes the shortest.

  By appropriately shifting the center of the signal ball array from the center of the semiconductor chip in the pad arrangement direction or the direction orthogonal thereto, the shift amount L of the center of the signal ball array is determined so that the length of the longest signal wiring is minimized. In many cases, the length of the longest signal wiring is almost equal to the length of the second longest signal wiring. Therefore, the difference between the length of the longest signal wiring and the length of the second longest signal wiring can be determined as a deviation amount that falls within a predetermined range. For example, it can be determined that the difference is within 3%, preferably within 1.5% of the length of the longest signal wiring.

  By making the length of the longest signal wiring belonging to the specific wiring group the shortest by the shift amount L of the center of the signal ball array, the maximum value of the signal delay of the signal type can be reduced. As a result, timing constraints necessary for design can be relaxed, and a semiconductor package capable of high-speed operation can be obtained.

  Further, the support ball is disposed in the vicinity of the end of the package substrate opposite to the direction in which the signal ball is shifted, and twice the shift amount L from the signal ball to the center of the signal ball array. The position was decided. Thereby, the center of the ball array including the signal ball and the support ball can be aligned with the center of the semiconductor chip, and good mounting reliability of the semiconductor package with respect to the mounting substrate can be obtained.

  Hereinafter, with reference to the drawings, the present invention will be described in more detail based on embodiments according to the present invention. FIG. 1 shows a partially broken perspective view of a semiconductor package according to a first embodiment of the present invention. 2 is a cross-sectional view taken along the line II-II in FIG. The semiconductor package 10 is a μBGA type semiconductor package, and includes a package substrate 12 including a ball array composed of a plurality of metal balls 20 arranged in an array, and a semiconductor chip 11 disposed on the package substrate 12. And a mold resin 19 that entirely covers the semiconductor chip 11. The semiconductor chip 11 is, for example, a DRAM having a capacity of 512 Mbytes and a signal bit length of 8 bits (x8), and includes pads 13 arranged in rows. The semiconductor chip 11 is disposed such that the back surface on which the pads 13 are disposed is in contact with the top surface of the package substrate 12 and the arrangement direction of the pads 13 coincides with the longitudinal direction of the ball array.

  The package substrate 12 includes an elastomer layer 14 that exposes the pad 13 in the opening 14 a and a TAB tape 17, and includes land portions 15 that are arranged in an array on the TAB tape 17. The land portion 15 includes a signal land portion 15a where the signal ball 20a is disposed and a support land portion (15b) where the support ball 20b is disposed. On the TAB tape 17, signal wiring 16 configured as a wiring pattern is also formed. The land portion 15 and the signal wiring 16 are made of Cu, and extend as they are from the wiring pattern in the opening 14a to form the inner lead 16a.

  On the TAB tape 17 on which the signal wiring 16 is formed, an elastomer layer 14 that supports the TAB tape 17 is formed. On the signal land portion 15a and the support land portion 15b exposed from the TAB tape 17, a signal ball 20a and a support ball 20b are respectively disposed. A sealing resin 18 is embedded in the opening 14a.

  FIG. 3 is a schematic plan view of the semiconductor package of FIG. 1 viewed from the back side. Reference numeral 35 indicates a center line on each side of the package substrate 12. In the semiconductor package 10, the center 31 of the semiconductor chip 11 coincides with the center 32 of the package substrate 12. The center 34 of the signal ball array is shifted by one pitch of the arrangement of the signal balls 20 a from the centers 31 and 32 of the semiconductor chip 11 and the package substrate 12 in the direction A parallel to the arrangement direction of the pads 13. In the figure, the smallest rectangle surrounding the entire signal ball array is indicated by reference numeral 34a. The center 34 of the signal ball array is defined as the center of this rectangle 34a.

  In the example of the figure, if the data signal line (DQ line) and the address signal line in the signal wiring 16 are a wiring group, the length of the longest DQ6 line belonging to the wiring group is 3.47 mm, and the second belonging to the wiring group. The length of the long DQ7 line is 3.46 mm, and both lengths are substantially equal. In this case, the length of the longest signal wiring included in the wiring group is the shortest compared to the case where the center 34 of the signal ball array is shifted by a pitch other than one pitch of the arrangement of the signal balls 20a. In the figure, data signal lines and address signal lines are indicated by dotted lines.

  The support balls 20b are disposed at positions separated from the direction A by the two pitches of the arrangement of the signal balls 20a from the adjacent signal balls 20a. The center 33 of the ball array including the signal balls 20 a and the support balls 20 b coincides with the centers 31 and 32 of the semiconductor chip 11 and the package substrate 12. In the figure, the smallest rectangle surrounding the ball array is indicated by reference numeral 33a. The center 33 of the ball array is defined as the center of this rectangle 33a. In the semiconductor package 10 of the present embodiment, one pitch of the arrangement of the signal balls 20a is set to 0.8 mm.

  In the semiconductor package 10 of the present embodiment, the length of the longest signal wiring belonging to the wiring group is compared with the case where the center 34 of the signal ball array is shifted from the center 31 of the semiconductor chip 11 by a pitch other than 1 pitch. The maximum signal delay can be suppressed by shortening the length. As a result, the timing constraint can be relaxed, and a semiconductor package that operates at high speed can be obtained. Further, the support ball 20b is disposed at a position away from the adjacent signal ball 20a by two pitches of the arrangement of the signal balls 20a in the direction opposite to the direction A, so that the bending strength of the semiconductor package 10 is increased. It can be ensured and good mounting reliability with respect to the mounting substrate can be obtained.

  A method for designing a semiconductor package according to a second embodiment of the present invention will be described. FIGS. 4A to 4C and FIGS. 5D and 5E show procedures for designing the semiconductor package 10 of the first embodiment. First, a semiconductor package in which the center 31 of the semiconductor chip 11 and the center 32 of the package substrate 12 are matched is assumed. Next, a simulation for obtaining a wiring pattern by shifting the semiconductor chip 11 in the arrangement direction of the pads 13 is performed, and the position where the length of the longest signal wiring belonging to the wiring group composed of the data signal line and the address signal line is the shortest is obtained. In this case, in order to match the arrangement of the support balls 20b with the arrangement of the signal balls 20a, the shift amount L of the semiconductor chip 11 is obtained as an integral multiple of ½ of the pitch of the arrangement of the signal balls 20a. In the simulation, it can be obtained as a position when the length of the longest signal wiring belonging to the wiring group is substantially equal to the length of the second longest signal wiring belonging to the wiring group.

  Next, as shown in FIG. 4A, the semiconductor chip 11 is shifted to a position obtained by simulation. In the figure, reference numeral 36 indicates the position of the semiconductor chip 11 before the center position is shifted.

Subsequently, the degree of fit of each side of the semiconductor chip 11 with respect to each side of the package substrate 12 is examined. When each side of the semiconductor chip 11 is accommodated inside each side of the package substrate 12 and a margin M ₁ where the side of the package substrate 12 protrudes from the side of the semiconductor chip 11 is sufficient from the viewpoint of mounting reliability. Leave as it is. If the margin M ₁ is insufficient, the package substrate 12 is expanded so that the margin M ₁ becomes an appropriate value as shown in FIG. When the semiconductor chip 11 is projected (overhang) on the outside of the package substrate 12, as shown in FIG. 4 (c), the end portion 21 of the side overhanging the package substrate 12, is appropriate margin M ₁ Expand to a value. Reference numerals 37 in FIGS. 4B and 4C indicate end portions before expansion, and M ₁ ′ in FIG. 4B indicates a margin before expansion.

When the margin M ₂ of the semiconductor chip 11 with respect to the package substrate 12 at the other end 22 of the package substrate 12 is excessive, the margin M ₂ is set to an appropriate value as shown in FIG. to shrink. The margins M ₁ and M ₂ are preferably set to 0.5 mm or more. Reference numeral 38 in the figure indicates the end 21 before reduction.

  Subsequently, the support ball 20b is disposed outside the signal ball 20a at the end in the same direction as the direction B in which the semiconductor chip 11 is shifted. The support ball 20b is disposed at a distance 2L that is twice the amount L of deviation of the semiconductor chip 11 from the adjacent signal ball 20a. As described above, the semiconductor package 10 of the first embodiment shown in FIG. 5E (or FIG. 3) can be designed. In the present embodiment, in the simulation of shifting the semiconductor chip 11 in the arrangement direction of the pads 13, the shift amount L of the semiconductor chip 11 is obtained in units of ½ of the arrangement pitch of the signal balls 20 a. However, it can also be obtained with an arbitrary value. In this case, the length of the longest signal wiring belonging to the wiring group can be optimized to be further shortened.

  A method for designing a semiconductor package according to a third embodiment of the present invention will be described. FIGS. 6A to 6C show a procedure for designing the semiconductor package according to the first embodiment. First, a semiconductor package in which the center 31 of the semiconductor chip 11 and the center 32 of the package substrate 12 are matched is assumed. Next, a simulation for obtaining a wiring pattern by shifting the center 34 of the signal ball array in the arrangement direction of the pads 13 is performed to obtain a position where the length of the longest signal wiring belonging to a specific wiring group is the shortest. Next, as shown in FIG. 6A, the center of the signal ball array is shifted to the position obtained by the simulation. In the figure, reference numeral 39 indicates a signal ball before the position is shifted. FIG. 6B shows the relative displacement between the center 34 of the signal ball array and the package center line 35 after shifting.

  Subsequently, as shown in FIG. 6C, the support ball 20b is disposed outside the signal ball 20a on the side opposite to the direction A in which the center 34 of the signal ball array is shifted. The support ball 20b is disposed at a distance 2L that is twice the amount L of deviation from the adjacent signal ball 20a to the center 34 of the signal ball array. In the present embodiment, it is assumed that the shift amount L obtained by the simulation is 0.5 pitch of the arrangement of the signal balls 20a, and the interval between the support balls 20b and the adjacent signal balls 20a is set to 1 of the arrangement of the signal balls 20a. The pitch.

In the second and third embodiments, it is desirable to secure a necessary amount for ensuring the mounting reliability for the margin M _{3 in} which the side of the package substrate 12 protrudes from the ball array. The margin M ₃ is preferably set to 1.3 mm or more, for example. If the size of the semiconductor chip 11 in the arrangement direction of the pads 13 greatly exceeds the arrangement size of the ball array, the support balls 20b can be arranged at both ends of the package substrate 12 in the arrangement direction of the pads 13. In this case, for example, instead of the position of the support ball 20b in the second and third embodiments, the semiconductor package 10 can be appropriately disposed at a position where the mounting reliability can be ensured.

  In order to confirm the effect of the present invention, in the μBGA type semiconductor package, the support ball 20b is not disposed, and the semiconductor package 11 and the center 31 of the signal ball array are aligned with the center 34, and A semiconductor package in which the center 34 of the signal ball array was shifted in accordance with the JEDEC DDR2 standard was designed as the semiconductor package of Comparative Example 1 and Comparative Example 2, respectively.

  The configurations of the semiconductor packages of Comparative Examples 1 and 2 are schematically shown in FIGS. In the semiconductor package of the comparative example 2, the center 34 of the signal ball array is arranged in one direction A parallel to the arrangement direction of the pads 13 in the arrangement of the signal balls 20a more than the centers 31 and 32 of the semiconductor chip 11 and the package substrate 12. It is shifted by 2 pitches. Further, the support balls 20b are arranged at positions separated from the direction A in the direction opposite to the direction A by four pitches of the arrangement of the signal balls 20a from the adjacent signal balls 20a.

  In the semiconductor package of Comparative Example 1, the DQ5 line is the longest in the wiring group, and the length is 3.97 mm. The DQ7 line is the second longest and has a length of 3.76 mm. In the semiconductor package of Comparative Example 2, the length of the DQ6 line in the wiring group is 4.08 mm. The length of the DQ7 line is 4.27 mm.

  A simulation for obtaining inductance (L), capacitance (C), and resistance (R) was performed on the DQ line and the A10 line of the semiconductor packages of Comparative Example 1, First Embodiment, and Comparative Example 2. 9A to 9D show the wiring length of the DQ line and the inductance, capacitance, and resistance obtained by simulation, respectively. In the figure, graphs (i) to (iii) show data of the semiconductor packages of Comparative Example 1, the first embodiment, and Comparative Example 2, respectively. From these figures, in the semiconductor package of the first embodiment, the wiring length, inductance, capacitance, and resistance in the DQ line are all about 13% as compared with the semiconductor package of the comparative example 1, and the semiconductor package of the comparative example 2 It can be seen that each is reduced or reduced by about 15%.

  FIGS. 10A to 10D show the wiring length of the A10 line and the inductance, capacitance, and resistance obtained by simulation, respectively. In the figure, graphs (i) to (iii) show data of the semiconductor packages of Comparative Example 1, the first embodiment, and Comparative Example 2, respectively. From these figures, in the semiconductor package of the first embodiment, the wiring length, inductance, capacitance, and resistance in the A10 line are all about 12% as compared with the semiconductor package of the comparative example 1, and the semiconductor package of the comparative example 2 It can be seen that each of them is shortened or reduced by about 14%.

  In the first to third embodiments, the case of the center pad arrangement in which one row of pads 13 is arranged in the center of the semiconductor chip 11 has been described. However, the edge pad arrangement in which two rows of pads are arranged at both ends of the semiconductor chip. In this case, the present invention can be similarly applied. Further, although the case of the long side arrangement in which the pads are arranged in parallel to the long side direction of the semiconductor chip has been described, the present invention is similarly applied to the case of the short side arrangement in which the pads are arranged in parallel to the short side direction of the semiconductor chip. The invention can be applied.

  In the first to third embodiments, the case where the center 34 of the signal ball array is shifted in the arrangement direction of the pads 13 has been described, but the signal ball array may be shifted in the orthogonal direction. Preferably, when the pads are arranged in only one direction on the semiconductor chip, the length of the longest signal wiring can be easily optimized by shifting the signal ball array in the arrangement direction of the pads 13. .

  In the first to third embodiments, the example in which the pad forming surface of the semiconductor chip 11 is disposed to face the package substrate 12 has been described. However, the back surface of the semiconductor chip 11 is disposed to face the package substrate 12. The same applies to the above. As for the connection between the pad 13 and the signal land portion 15a, in addition to the wiring pattern, this connection can also be used when connecting using a bonding wire or other signal wiring such as a combination of the bonding wire and the wiring pattern. The invention is equally applicable.

  As described above, the present invention has been described based on the preferred embodiment. However, the semiconductor package and the design method thereof according to the present invention are not limited to the configuration of the above-described embodiment, and various modifications can be made from the configuration of the above-described embodiment. The semiconductor package and the design method thereof modified and changed as described above are also included in the scope of the present invention.

1 is a perspective view showing a partially broken structure of a semiconductor package according to a first embodiment of the present invention. It is sectional drawing which shows the cross section which follows the II-II line | wire of FIG. It is the typical top view which looked at the semiconductor package of FIG. 1 from the back surface side. FIGS. 4A to 4C are plan views showing a procedure for designing a semiconductor package according to the second embodiment of the present invention. 5D and 5E are plan views respectively showing a procedure subsequent to FIG. 4 for designing the semiconductor package according to the second embodiment of the present invention. FIGS. 6A to 6C are plan views showing a procedure for designing a semiconductor package according to the third embodiment of the present invention. FIG. 7 is a schematic plan view of the semiconductor package of Comparative Example 1 viewed from the back side. FIG. 8 is a schematic plan view of the semiconductor package of Comparative Example 2 viewed from the back side. FIGS. 9A to 9D are graphs showing the wiring length, inductance, capacitance, and resistance for the DQ lines in the semiconductor packages of Comparative Example 1, the first embodiment, and Comparative Example 2, respectively. FIGS. 10A to 10D are graphs showing the wiring length, inductance, capacitance, and resistance, respectively, for the A10 line in the semiconductor packages of Comparative Example 1, First Embodiment, and Comparative Example 2. FIG. FIGS. 11A and 11B are plan views showing a front surface and a back surface of a conventional μBGA type semiconductor package in which a ball array is composed only of signal balls, respectively. It is a top view which shows the back surface of a semiconductor package about the conventional μBGA type semiconductor package which comprised the ball array by the signal ball | bowl and the support ball | bowl.

Explanation of symbols

10: Semiconductor package 11: Semiconductor chip 12: Package substrate 13: Pad 14: Elastomer layer 14a: Opening 15: Land portion 15a: Signal land portion 15b: Support land portion 16: Signal wiring 16a: Inner lead 17: TAB tape 18: Sealing resin 19: Mold resin 20: Metal ball 20a: Signal ball 20b: Support balls 21, 22: End portion (of package substrate) 31: Semiconductor chip center 31a: Diagonal line 32 in semiconductor chip rectangle 32: Package substrate center 33: Ball array center 33a: Minimum rectangle 33b surrounding the entire metal ball 33b: Diagonal line 34 in the smallest rectangle surrounding the entire metal ball 34: Signal ball array center 34a: Minimum rectangle 34b surrounding the entire signal ball: The smallest rectangle that encloses the entire signal ball Diagonal line 35: Center line 35 'on each side of the package substrate outer shape: Center line 36 on each side of the package substrate outer shape before changing the end surface of the package substrate 36: Semiconductor chip position 37 before shifting the center position: Position 38 of the end surface of the package substrate before extending the package substrate: Position 39 of the end surface of the package substrate before reducing the package substrate: Signal balls 51, 52 before shifting the position: Conventional semiconductor package

Claims (12)

A semiconductor chip comprising a plurality of pads arranged in rows;
In a semiconductor package comprising a package substrate having a signal ball array including a plurality of signal balls connected to the pads via signal wirings and arranged in an array,
The center of the signal ball array is displaced from the center of the semiconductor chip by a predetermined shift amount (L) along the arrangement direction of the pads or in a direction orthogonal to the arrangement direction,
Of the specific signal wiring group included in the signal wiring, the length of the longest signal wiring that is the longest when it is assumed that the center of the semiconductor chip and the center of the signal ball array are not shifted is the signal ball. A semiconductor package characterized in that the center of the array is deviated from the center of the semiconductor chip, so that the array is shorter than if it is not deviated.   2. The semiconductor package according to claim 1, wherein the shift amount L is an integral multiple of an arrangement pitch of signal balls or an integral multiple of ½ of the arrangement pitch.   The semiconductor package according to claim 2, wherein the shift amount L is 0.5, 1, or 1.5 times the arrangement pitch of the signal balls.   4. The semiconductor package according to claim 2, wherein the shift amount L is selected so that the longest signal wiring is the shortest.   The package substrate has a support ball in addition to the signal ball, and the support ball starts from the signal ball disposed at the end of the signal ball array, and the center of the signal ball array is the semiconductor chip. The semiconductor package according to any one of claims 1 to 4, wherein the semiconductor package is disposed at a position separated by a distance 2L in a direction opposite to a direction deviated from the center.   The semiconductor package according to claim 1, wherein a distance between an end face of the semiconductor chip and an end face of the package substrate is 0.1 mm or more.   7. The semiconductor package according to claim 1, wherein the semiconductor package is a DRAM, and the signal wiring group is any one of a data signal line group, a clock signal line group, an address signal line group, and a control signal line group. Semiconductor package. A semiconductor chip having a plurality of pads arranged in a row, and a package substrate having a signal ball array including a plurality of signal balls respectively connected to the pads via signal wirings and arranged in an array. In a method of designing a semiconductor package,
In arranging the semiconductor chip and the package substrate,
In a state where the center of the signal ball array and the center of the semiconductor chip are matched, the longest signal wiring that is the longest among the specific signal wiring groups included in the signal wiring is extracted,
A method of designing a semiconductor package, wherein the center of the signal ball array is shifted from the center of the semiconductor chip by a predetermined shift amount (L) so that the length of the longest signal wiring is shortened.   The method of designing a semiconductor package according to claim 8, wherein the shift amount L is an integral multiple of an arrangement pitch of signal balls or an integral multiple of ½ of the arrangement pitch.   The method of designing a semiconductor package according to claim 9, wherein the shift amount L is set to 0.5, 1, or 1.5 times the arrangement pitch of the signal balls.   The method of designing a semiconductor package according to claim 9 or 10, wherein the shift amount L is selected so that the longest signal wiring is shortest.   In addition to the signal balls, support balls are disposed on the package substrate, and the support balls are arranged from the signal balls disposed at the end portions of the signal ball array so that the center of the signal ball array is the center of the semiconductor chip. The method of designing a semiconductor package according to any one of claims 8 to 11, wherein the semiconductor package is disposed at a position separated by a distance 2L in a direction opposite to a direction shifted from the center.

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