JP2006092483A - Switched capacitor circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce occurrences of a power source voltage fluctuation and unnecessary radiation accompanying potential movement at the time of charging or discharging a sampling capacitor, and to perform precise sampling operation. <P>SOLUTION: When a transistor switch for controlling the charge timing of the sampling capacitor is serially connected to a transistor switch for controlling charge speed, a transition duration when a transistor for controlling charge speed changes from an off-state to a complete on-state is made longer than a transition duration when the transistor switch for controlling the charge timing changes from the off-state to the complete on-state. On the other hand, when a transistor switch for controlling the discharge timing of the sampling capacitor is serially connected to a transistor switch for controlling discharge speed, a transition duration when a transistor for controlling discharge speed changes from the off-state to the complete on-state is made longer than a transition duration when the transistor switch for controlling discharge timing changes from the off-state into the complete on-state. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a switched capacitor circuit as a semiconductor integrated circuit manufactured by a semiconductor integrated circuit manufacturing technique.

  In recent years, audio semiconductor integrated circuits such as AD converters and DA converters have strong needs for recording and reproducing music with high sound quality, and switching capacitor circuits used in many integrated circuits have low noise ( In other words, the capacitance value of the sampling capacitor is increased in order to increase the SN ratio.

  Switched capacitor circuits move charge during charging or discharging (ie, current flows), but as the capacitance value of the sampling capacitor increases, a larger amount of charge is moved, resulting in greater power supply voltage fluctuations and unnecessary. Radiation will occur. In addition, the more rapidly the charge moves (that is, a large current), the greater the fluctuation of the power supply voltage and the unnecessary radiation.

  The fluctuations in the power supply voltage may cause noise to enter an analog circuit or analog device operating with a voltage originating from the same power supply, resulting in malfunction or audible noise even if malfunction does not occur. Further, unnecessary radiation propagates as electromagnetic waves through the air, and peripheral devices may malfunction or generate noise.

  In order to explain the operation of such a switched capacitor circuit, an integrator using the switched capacitor circuit is shown in FIG.

  In this example, the CAP 21 is a sampling capacitor that charges and discharges charges. The N-type MOS transistors TS20 and TS21 are charge timing control transistor switches. N-type MOS transistors TS22 and TS23 are discharge timing control transistor switches.

  The integrating capacitor CAP22 is connected to the operational amplifier 23 in a feedback manner, and the input thereof is connected to the TS23. The integrating capacitor CAP22 is an integrator that integrates the input signal with the period of the two-phase non-overlap clock signals CK1 and CK2.

  That is, when CK1 is H (that is, high level), the CAP21 is charged between the voltage of the input signal and the AGND voltage, and when CK2 is H, the charge charged in the CAP21 is transferred (that is, integrated) to the CAP22.

  FIG. 16 shows the timing of CK1 and CK2 and the state of the amount of current supplied from the input signal.

  When CK1 changes from L (ie, low level) to H and TS20 and TS21 change from the off state to the on state, charging of the CAP21 starts, and thus a current flows rapidly. At this timing, the input signal is driven by a large current, and sudden power supply voltage fluctuations and unnecessary radiation are generated.

  As a switched capacitor circuit for reducing the occurrence of undesirable fluctuations in power supply voltage and unnecessary radiation as described above, Patent Document 1 discloses a circuit as shown in FIG.

  The circuit shown in FIG. 17 is composed of a capacitor and a plurality of MOS transistors connected in parallel. The MOS switching means for discharging the capacitor, and a clock pulse are input to each of the MOS switching means. In order to turn on the MOS transistors in order, there is provided a timing generating means for outputting with a slight delay of the rising timing of the ON signal.

  In this circuit, it is possible to move charges using MOS transistor switches divided in parallel at the beginning of the movement of charges, and to reduce the generation of unnecessary charge radiation compared to the case where the original large (or all) MOS transistor switches are used. Has been made.

  FIG. 18 shows the state of current supplied from the clocks CK1, CK2, CK1d, CK2d and the input signal.

Japanese Patent Laid-Open No. 05-037300

  However, in the circuit shown in FIG. 17, for example, when the period when CK1 charging the capacitor CAP210 is H is taken as an example, the moment when the transistor switches TS201 and TS211 that turn on first turn on and the CAP210 starts to charge, and the transistor that turns on later When the switches TS202 and TS212 are turned on and charging of the uncharged capacitor starts to be performed, a large amount of charge moves to generate power supply voltage fluctuations and unnecessary radiation.

  Here, the part where the voltage change is to be suppressed is not the voltage between both terminals of the capacitor but the output voltage of the power supply itself / the signal source itself.

  The place where the fluctuation of the power supply voltage which becomes a problem in FIG. 17 occurs is the terminal part of “input signal” and “AGND” indicated by ▽. These voltage changes adversely affect other circuits connected to the same terminal (mixing noise or malfunctioning).

  Further, since the portion where the defective radiation is generated is a path through which a current flows, in FIG. 17, it corresponds to a path from the terminal of “input signal” to this circuit and a path from “AGND” to this circuit.

  In addition, when the transistor switch is turned off at the most critical sampling end time in the switched capacitor circuit (that is, when CK1 changes from H to L), it is desired to turn off two transistor switches controlled by CK1 and CK1d at the same time. However, it is extremely difficult to turn off the two transistors simultaneously.

  Since two sets of transistor switches do not turn off instantaneously and simultaneously, the other turns off later and turns off later with the potential of the terminals connected to both ends of the switch fluctuating due to feedthrough noise caused by one of them turning off. Since the amount of charge sampled at the timing of the transistor is fixed, the sampling every time becomes unstable and accurate sampling cannot be performed.

  Furthermore, the above-described power supply voltage fluctuations, unnecessary radiation, and the inability to perform accurate sampling can also be said for the operation of discharging a capacitor.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a switched capacitor circuit that can accurately perform sampling by satisfactorily reducing fluctuations in power supply voltage and generation of unnecessary radiation due to charge movement during charging or discharging of a sampling capacitor. is there.

The present invention includes a sampling capacitor that charges and discharges charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor,
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor, and driving timing of the charge timing control transistor switch for charging the sampling capacitor to a desired voltage in the first period. Means for controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in the second period, and one of the charge timing control transistor switch A charge-discharge speed control transistor switch connected in series to a terminal or one terminal of the discharge timing control transistor switch, wherein the charge-discharge speed control transistor switch is a charge speed control transistor switch; Or a charge / discharge rate control means configured to include a discharge rate control transistor switch, connected to an input control terminal of the charge / discharge rate control transistor switch, and controlling a signal input to the input control terminal. Thus, a switched capacitor circuit is configured.

  The present invention includes a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and two connected between both terminals of the sampling capacitor. A plurality of discharge timing control transistor switches, and a plurality of sets of circuits each including the sampling capacitor, two charge timing control transistor switches, and two charge timing control transistor switches are connected in parallel. Means for controlling the drive timing of the charge timing control transistor switch for charging the sampling capacitor to a desired voltage in the first period, and discharging the charge stored in the sampling capacitor in the second period. And the discharge tag And a common connection terminal of the charge timing control transistor switch connected in parallel, or a common connection of the discharge timing control transistor switch connected in parallel. A transistor switch for charge / discharge rate control connected in series to the terminal, wherein the transistor switch for charge / discharge rate control is constituted by a transistor switch for charge rate control or a transistor switch for discharge rate control. A switched capacitor circuit is configured by including charge / discharge rate control means connected to the input control terminal of the discharge rate control transistor switch and controlling a signal input to the input control terminal.

  The present invention includes a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and two connected between both terminals of the sampling capacitor. Discharge timing control transistor switch, and a plurality of parallel circuits each including the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches as one set Means for controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in the first period, and discharging the charge stored in the sampling capacitor in the second period To do before Means for controlling the drive timing of the discharge timing control transistor switch, and one connection terminal of each of the sets of charge timing control transistors connected in parallel, or each of the sets of discharge timing control transistors connected in parallel A plurality of charge / discharge speed control transistor switches connected in series to one terminal of the switch, wherein the charge / discharge speed control transistor switch is a charge speed control transistor switch or a discharge speed control transistor; A plurality of charging / discharging rate control means for controlling signals input to the respective input control terminals, each of which is configured by a switch and connected to each of the input control terminals of each set of charge / discharge rate controlling transistor switches; Thus, a switched capacitor circuit is configured.

  The present invention includes a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and two connected between both terminals of the sampling capacitor. Discharge timing control transistor switch, and a plurality of parallel circuits each including the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches as one set Means for controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in the first period, and discharging the charge stored in the sampling capacitor in the second period To do before Means for controlling the drive timing of the discharge timing control transistor switch, and one connection terminal of each of the sets of charge timing control transistors connected in parallel, or each of the sets of discharge timing control transistors connected in parallel A plurality of charge / discharge speed control transistor switches connected in series to one terminal of the switch, wherein the charge / discharge speed control transistor switch is a charge speed control transistor switch or a discharge speed control transistor; And a charge / discharge rate control means for controlling a signal input to each of the input control terminals, the switch being configured to be connected in common to the input control terminals of the charge / discharge rate control transistor switches of each set. Thus, a switched capacitor circuit is configured.

  When the charge / discharge speed control transistor switch is configured as a charge speed control transistor switch connected to the charge timing control transistor switch, the charge / discharge speed control means includes the charge speed control transistor switch. Is turned on in the first period and turned off in the second period, and the transition time for changing from the off state to the fully on state is changed from the off state to the fully on state of the charge timing control transistor switch. You may control the voltage of the input control terminal of this transistor switch for charge speed control so that it may become longer than time.

  When the charge / discharge speed control transistor switch is configured as a discharge speed control transistor switch connected to the discharge timing control transistor switch, the charge / discharge speed control means includes the discharge speed control transistor switch. Is turned off in the first period and turned on in the second period, and the transition time for changing from the OFF state to the fully ON state is changed from the OFF state to the fully ON state of the discharge timing control transistor switch. The voltage at the input control terminal of the discharge speed control transistor switch may be controlled to be longer than the time.

  The charge / discharge speed control means is determined by a circuit element including a resistor and a capacitor when the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state. The input control signal terminal of the charge rate control transistor switch or the discharge rate control transistor switch may be controlled by a signal that changes with a time constant.

  The charge / discharge speed control means is determined by a circuit element including a current source element and a capacitor when the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state. An input control signal terminal of the charge rate control transistor switch or the discharge rate control transistor switch may be controlled by a signal having a change rate.

  When the charge rate control transistor switch or the discharge rate control transistor switch changes from an off state to an on state, the charge / discharge rate control means has the highest change rate during the state change immediately after the start of the state change. The input control signal terminal of the charging speed control transistor switch or the discharging speed control transistor switch may be controlled by a signal having a fast portion.

  The present invention relates to a switch switching method for a switched capacitor circuit, which is a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and the sampling capacitor. Connected in series to two discharge timing control transistor switches and one terminal of the charge timing control transistor switch, or one terminal of the discharge timing control transistor switch connected between the two terminals. A charge / discharge rate control transistor switch, wherein the charge / discharge rate control transistor switch is a charge rate control transistor switch or a circuit configured by the discharge rate control transistor switch in the first period. Controlling the drive timing of the charge timing control transistor switch to charge the storage capacitor to a desired voltage; and discharging the charge stored in the sampling capacitor in the second period. Switching of the switched capacitor circuit by comprising a step of controlling the drive timing of the transistor switch for charge and a charge / discharge rate control step of controlling the signal input to the input control terminal of the transistor switch for charge / discharge rate control Provide a method.

  The present invention relates to a switch switching method for a switched capacitor circuit, which is a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and the sampling capacitor. A pair of two discharge timing control transistor switches connected between the two terminals, the sampling capacitor, two charge timing control transistor switches, and two charge timing control transistor switches. A plurality of sets of circuits configured in parallel and connected to one common connection terminal of the charge timing control transistor switch connected in parallel, or one common connection terminal of the discharge timing control transistor switch connected in parallel Series connected charge An electric speed control transistor switch, and the charge / discharge speed control transistor switch is a charge speed control transistor switch or a discharge speed control transistor switch in the circuit configured by the charge speed control transistor switch in the first period. A step of controlling a drive timing of the charge timing control transistor switch for charging to a desired voltage; and a discharge timing control transistor switch for discharging the charge stored in the sampling capacitor in a second period. And a charge / discharge speed control process for controlling a signal input to an input control terminal of the charge / discharge speed control transistor switch, thereby providing a switch switching method for the switched capacitor circuit. To.

  The present invention relates to a switch switching method for a switched capacitor circuit, which is a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and the sampling capacitor. Two discharge timing control transistor switches connected between the two terminals, wherein the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are Plural sets of circuits configured as one set are connected in parallel, and one connection terminal of each of the charge timing control transistor switches connected in parallel, or each set of discharge timing control transistor switches connected in parallel Connect directly to one of the terminals. A plurality of charge / discharge speed control transistor switches connected, wherein the charge / discharge speed control transistor switch is a charge speed control transistor switch or a circuit configured by a discharge speed control transistor switch; Controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in a period, and discharging the charge stored in the sampling capacitor in a second period. A step of controlling the drive timing of the discharge timing control transistor switch; and a plurality of charge / discharge rate control steps of controlling signals input to the input control terminals of the charge / discharge rate control transistor switches of each set. By It provides a switching method of switching-capacitor circuit.

  The present invention relates to a switch switching method for a switched capacitor circuit, which is a sampling capacitor for charging and discharging electric charge, two charge timing control transistor switches connected between both terminals of the sampling capacitor, and the sampling capacitor. Two discharge timing control transistor switches connected between the two terminals, wherein the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are Plural sets of circuits configured as one set are connected in parallel, and one connection terminal of each of the charge timing control transistor switches connected in parallel, or each set of discharge timing control transistor switches connected in parallel Connect directly to one of the terminals. A plurality of charge / discharge speed control transistor switches connected to each other, the charge / discharge speed control transistor switch being constituted by a charge speed control transistor switch or a discharge speed control transistor switch; Controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage; and discharging the charge stored in the sampling capacitor in a second period. A step of controlling the drive timing of the transistor switch for charge and a charge / discharge rate control step of controlling a signal input in common to the input control terminal of each set of charge / discharge rate control transistor switches, Switched capacitor circuit To provide a switch switching method.

  In the charge / discharge rate control step, when the transistor switch for charge / discharge rate control is configured as a transistor switch for charge rate control connected to the transistor switch for charge timing control, the transistor switch for charge rate control Is turned on in the first period and turned off in the second period, and the transition time for changing from the off state to the fully on state is changed from the off state to the fully on state of the charge timing control transistor switch. You may control the voltage of the input control terminal of this transistor switch for charge speed control so that it may become longer than time.

  In the charge / discharge rate control step, when the transistor switch for charge / discharge rate control is configured as a transistor switch for discharge rate control connected to the transistor switch for discharge timing control, the transistor switch for discharge rate control Is turned off in the first period and turned on in the second period, and the transition time for changing from the OFF state to the fully ON state is changed from the OFF state to the fully ON state of the discharge timing control transistor switch. The voltage at the input control terminal of the discharge speed control transistor switch may be controlled to be longer than the time.

  The charge / discharge speed control step is determined by a circuit element including a resistor and a capacitor when the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state. The input control signal terminal of the charge rate control transistor switch or the discharge rate control transistor switch may be controlled by a signal that changes with a time constant.

  The charge / discharge speed control step is determined by a circuit element including a current source element and a capacitor when the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state. An input control signal terminal of the charge rate control transistor switch or the discharge rate control transistor switch may be controlled by a signal having a change rate.

In the charge / discharge rate control step, when the charge rate control transistor switch or the discharge rate control transistor switch changes from an off state to an on state,
The input control signal terminal of the charge speed control transistor switch or the discharge speed control transistor switch may be controlled by a signal having a portion with the fastest change speed in the middle of the state change immediately after the start of the state change.

  In the present invention, when the charge / discharge speed control transistor switch is configured as a charge speed control transistor switch connected to the charge timing control transistor switch, the charge speed control transistor switch is turned on in the first period. The charging time is turned on and turned off in the second period, and the transition time for changing from the off state to the fully on state is made longer than the transition time for changing the charge timing control transistor switch from the off state to the fully on state. When the voltage of the input control terminal of the speed control transistor switch is controlled, while the charge / discharge speed control transistor switch is configured as a discharge speed control transistor switch connected to the discharge timing control transistor switch, The discharge speed control transistor switch H is turned off in the first period and turned on in the second period, and the transition time for changing from the off state to the fully on state is changed from the transition time for changing the discharge timing control transistor switch from the off state to the fully on state. Since the voltage at the input control terminal of the transistor switch for controlling the discharge rate is controlled so as to lengthen the voltage, fluctuations in the power supply voltage and generation of unnecessary radiation accompanying the movement of the charge during sampling capacitor charging or discharging. Accurate sampling can be performed while reducing well.

Hereinafter, embodiments of the present invention will be described in detail with reference to examples.
[First example]
A first embodiment of the present invention will be described with reference to FIGS.
<Configuration>
The switched capacitor circuit according to the present invention includes a sampling capacitor that charges and discharges charge, a charge timing control transistor switch that controls a timing at which both ends of the sampling capacitor are charged to a desired voltage in the first period, and a second period. A discharge timing control transistor switch for controlling the timing at which the charge stored in the sampling capacitor is discharged, and at least a charge speed control transistor switch connected in series to the charge timing control transistor switch, or the discharge One of the discharge speed control transistor switches connected in series to the timing control transistor switch and input control terminal voltage control means.

Here, the input control terminal voltage control means will be described.
If this input control terminal voltage control means has a transistor switch for charge rate control, it turns on the transistor switch for charge rate control in the first period and turns it off in the second period, and from the off state to the fully on state. The input control terminal voltage of the charging speed control transistor switch may be controlled such that the transition time during which the charging timing control transistor switch changes from the OFF state to the fully ON state is longer than the transition time during which the charging timing control transistor switch changes from the OFF state to the fully ON state.

  If the input control terminal voltage control means has a discharge speed control transistor switch, the input control terminal voltage control means turns off the discharge speed control transistor switch in the first period and turns it on in the second period. The input control terminal voltage of the discharge speed control transistor switch may be controlled such that the transition time for changing to the state is longer than the transition time for changing from the OFF state of the discharge timing control transistor switch to the fully ON state. .

(Concrete example)
FIG. 1 shows a configuration example of a switched capacitor circuit.
In this example, a switched capacitor circuit is shown as a configuration example integrated on a semiconductor substrate using MOS transistors.
The CAP 11 is a sampling capacitor that charges and discharges charges.
N-type MOS transistors TS10 and TS11 are charge timing control transistor switches.
The N-type MOS transistors TS12 and TS13 are discharge timing control transistor switches.
RS14 which is an N-type MOS transistor is a transistor switch for charge speed control.

  The integration capacitor CAP12 is connected to the operational amplifier 13 in a feedback manner, and its input is connected to the TS13. The integration capacitor CAP12 is an integrator that integrates the input signal with the period of the two-phase non-overlap clock signals CK1 and CK2.

FIG. 2 shows a circuit configuration example of a first example of the input control terminal voltage control means.
The input control terminal voltage control means changes with a time constant determined by a circuit element including a resistor and a capacitor when the charge rate control transistor switch or the discharge rate control transistor switch changes from an off state to an on state. The input control signal terminal of the charge rate control transistor switch or the discharge rate control transistor switch is controlled by the signal to be transmitted.

  This circuit is a circuit that generates a signal CK1d with a slow change rate with respect to CK1.

  The input CK1 outputs CK1d that changes potential according to a time constant created by the resistor R72 and the capacitor CAP71.

<Circuit operation>
The operation of this circuit will be described.
FIG. 3 shows a timing chart of the operation of this circuit shown in FIG.
RS14 is basically turned on when CK1 is H and turned off when CK1 is L. The transition time from the off state to the fully on state is changed from the off state of TS10 and TS11 to the fully on state. In order to make the transition time longer than the changing transition time, the input control terminal voltage control means 14 receives CK1 and generates a signal CK1d to control the gate terminal voltage of RS14.

  That is, basically, as with the operation of the integrator of FIG. 17, CAP11 is charged between the input signal voltage and the AGND voltage when CK1 is H (ie, high level), and CAP11 is charged when CK2 is H. The charge is transferred (ie integrated) to the CAP 12.

  FIG. 3 shows the timing of CK1, CK2, and CK1d and the state of the amount of current supplied from the input signal.

When CK1 changes from L (that is, low level) to H and TS10 and TS11 change from the off state to the on state, the CAP11 starts to be charged. Since the gate voltage change of RS14 is gradual at the beginning of the change to, the signal does not turn on strongly and a large current does not flow through the input signal.
That is, sudden fluctuations in the power supply voltage and unnecessary radiation do not occur.

  Further, when the transistor switch is turned off at the most critical sampling end time in the switched capacitor circuit (that is, when CK1 changes from H to L), it is turned off only by changing one clock signal CK1 from L to H. Since the timing to perform is determined, an accurate sampling operation is possible.

FIG. 4 shows a timing chart of the input control terminal voltage control means shown in FIG.
In FIG. 4, CK1 changes from L to H at time t0, and in response thereto, CK1d that changes gradually is generated. The resistance value of the transistor to which CK1d is applied to the gate gradually changes from a high value to a low value, the current starts to flow gradually, and the amount of current gradually decreases, and the charge charging to the capacitor is finished.

  The voltage fluctuation at the terminal of the input signal (and the change in the AGND voltage) depends on the output impedance of the power source / signal source itself, the wiring impedance, and the amount of current flowing, and has the same shape as the amount of current.

  That is, the shape has a gently low peak value (compared to the conventional case). Further, since unnecessary radiation is generated in proportion to the amount of change in current (that is, the differential component), this is also smaller than in the conventional case.

  By gradually changing the gate potential of the charging speed control transistor switch in this way, the amount of current supplied from the input signal when the sampling capacitor starts to be charged is reduced, and the change in the amount of current is smoothed. It is possible to suppress changes in power supply voltage and generation of unnecessary radiation.

(Voltage fluctuation / unnecessary radiation)
Next, the effect of reducing voltage fluctuation and unnecessary radiation by this circuit will be described.
(1) A description will be given of what changes the current amount of the circuit.
The amount of current is most related to the gate voltage of the transistor that controls the gate voltage to adjust the amount of current. In the case of an N-type MOS, the resistance value is high when the gate voltage is low, and the resistance value is low when the gate voltage is high. However, since the resistance value itself is related to the source / drain voltage of the transistor, it is not uniquely determined only by the gate voltage. Further, the resistance value and the amount of current are in an inversely proportional relationship.

  That is, when the gate voltage is low, the resistance value is high and the amount of current is small. When the gate voltage is high, the resistance value is low and the amount of current is large.

  In the timing chart of FIG. 18 corresponding to the circuit of FIG. 17 described in the prior art, CK1 (= gate voltage) rises rapidly, the resistance value of the transistor decreases instantaneously, and a large current flows instantaneously.

  As a result, a large voltage fluctuation due to a large current (high peak value) and a large unnecessary radiation due to a steep current change are generated.

  On the other hand, in the timing chart 3 of FIG. 3 corresponding to the circuit of the present invention of FIG. 1, CK1 (= gate voltage) rises slowly, and the resistance value of the transistor gradually changes from a high value to a low value. Since a considerable amount of charge has been passed while the resistance value is high, a small current is passed over a long period of time.

  As a result, a small power supply voltage fluctuation due to a small current (low peak value) and a small unnecessary radiation can be generated due to a gradual current change.

(2) Power supply (and ground) voltage fluctuation / signal source voltage fluctuation will be described.
Depending on the current that flows when the sampling capacitor is charged / discharged, the output impedance of the power supply (and ground) (when the input terminal is connected to the power supply) or the output impedance of the signal source (when the input terminal is connected to the signal source) ) And power supply voltage fluctuations due to wiring impedance. In the present invention, the voltage fluctuation is proportional to the amount of current. Therefore, the voltage fluctuation can be reduced by reducing the current amount at each time (or the peak value of the current amount).

(3) The power source (and ground) voltage fluctuation / unwanted radiation of the signal source will be described.
Unwanted radiation (electromagnetic induction noise) generates a large amount of unnecessary radiation in proportion to the change in the amount of current. By reducing the current amount change, that is, by reducing the current change gradient, it is possible to reduce the occurrence of unnecessary radiation.

(Other configuration examples)
In this example as described above, the charging speed control transistor switch is connected in series only to the switch (TS11) on one side of the sampling capacitor among the charging timing control transistor switches for simplification of description. A similar charging speed control transistor switch can be connected to the opposite switch (TS10). Further, a similar discharge speed control transistor switch can be connected to the discharge timing control transistor switch (TS12 or TS13).

  Further, as in this example, the first period and the second period are instructed, and the charging speed is received by receiving clock signals (CK1, CK2 in this example) for controlling the charge timing control transistor switch or the discharge timing control transistor switch. From the viewpoint of signal generation order (especially the order at the timing of turning on and off) and the ease of generation, it is necessary to generate a signal (CK1d in this example) for controlling the control transistor switch or the discharge speed control transistor switch. desirable.

  The switch may be an element having a function of turning on and off a signal path such as a MOS transistor or a bipolar transistor.

  The sampling capacitor may be formed between two insulated surfaces using any material that can be formed on a semiconductor substrate such as a polysilicon layer, a metal layer, or a diffusion layer.

  Further, the term “off state” used in this example is a state in which the signal is cut off because the voltage of the control terminal of the switch (the gate terminal in the case of a MOS transistor) is lower than the threshold voltage (N-type MOS transistor). In this case, the gate voltage is lower than the threshold voltage, which means that the source and drain are in a non-conducting state). “Completely on” means the control terminal of the switch (in the case of a MOS transistor, the gate The voltage of the terminal is the highest steady voltage during normal operation, so that the signal is strongly conducting (in the case of an N-type MOS transistor, the gate voltage is the positive power supply voltage of the circuit, so the source and drain) It is intended to be a state of strong conduction between the two).

  However, in the case of an element such as a P-type MOS that has a negative threshold voltage and is strongly turned on when a negative voltage is applied by the gate, the “off state” means that the voltage at the control terminal of the switch is the threshold voltage. Therefore, it is intended that the signal is cut off, and “fully on” means that the voltage at the control terminal of the switch is the lowest steady-state voltage during normal operation, so the signal is strongly conducted. Intended to be in a state.

  In this example, the input terminal voltage control unit 14 is configured as a hardware circuit as the input terminal voltage control unit 14. However, the input terminal voltage control unit 14 is configured to change the input terminal voltage based on control of a program or the like. It is also possible to configure.

  For example, this circuit uses the CK1 signal as a trigger input to generate a slowly changing signal CK1d, so that the shape of CK1d can be generated while calculating the shape that changes with time in terms of software, or stored in memory. It is possible to control by taking out the obtained information and sequentially generating and outputting a “voltage signal” using a DA converter.

[Second example]
A second embodiment of the present invention will be described with reference to FIGS.
FIG. 5 shows a circuit configuration example of a second example of the input control terminal voltage control means.
The input control terminal voltage control means has a change speed determined by a circuit element including a current source element and a capacitor when a charge speed control transistor switch or a discharge speed control transistor switch changes from an off state to an on state. The input control signal terminal of the transistor switch for charge rate control or the transistor switch for discharge rate control is controlled by the signal it has.

  This circuit is a circuit that generates a slowly changing signal CK1d whose rate of change is constant with respect to CK1.

  Input CK1 is inverted twice by an inverter formed by inverters INV82, TR85, and TR82 and outputs CK1d having the same phase. When CKd1 changes from H to L, current 81 is current mirrored by TR81 and TR80. When CKd1 changes from L to H while being limited, the current 82 is limited by the current mirrored by TR84 and TR83, and the capacitance added to CK1d or the parasitic capacitance CAP81 is charged to change the voltage. go.

6 shows a timing chart of the input control terminal voltage control means shown in FIG.
In FIG. 6, CK1 changes from L to H at time t0, and in response thereto, CK1d that changes gradually is generated. The resistance value of the transistor to which CK1d is applied to the gate gradually changes from a high value to a low value, the current starts to flow gradually, and the amount of current gradually decreases, and the charge charging to the capacitor is finished.

  The voltage fluctuation at the terminal of the input signal (and the change in the AGND voltage) depends on the output impedance of the power source / signal source itself, the wiring impedance, and the amount of current flowing, and has the same shape as the amount of current.

  That is, the shape has a gently low peak value (compared to the conventional case). Further, since unnecessary radiation is generated in proportion to the amount of change in current (that is, the differential component), this is also smaller than in the conventional case.

  The amount of current supplied from the input signal is reduced by gently changing the gate potential of the charging speed control transistor switch by the signal CKd1 having the changing speed determined by the current source elements TR80 and TR83 and the capacitor CAP81. In addition, the change in the amount of current is smoothed, and the change in the power supply voltage and the generation of unnecessary radiation are suppressed.

  In this case, as compared with the first circuit example of FIG. 2, the change in the gate voltage of the transistor switch for charging speed control at the time when the current starts to flow from the input signal is maintained in the vicinity of the H level while maintaining the same degree of gentleness. Since the asymptotic speed to the H level is fast, the sampling capacitor can be charged for a longer time with low impedance, and settling errors can be reduced.

[Third example]
A third embodiment of the present invention will be described with reference to FIGS.
FIG. 7 shows a circuit configuration example of a third example of the input control terminal voltage control means.
The input control terminal voltage control means has a portion with the fastest change speed in the middle of the state change immediately after the start of the state change when the charge speed control transistor switch or the discharge speed control transistor switch changes from the OFF state to the ON state. The input control signal terminal of the charge rate control transistor switch or the discharge rate control transistor switch is controlled by the signal.

  This circuit is a circuit that generates a signal CK1d whose change rate changes gradually with respect to CK1.

  Input CK1 is inverted twice by an inverter formed by inverters INV92, TR95, and TR92 and outputs CK1d having the same phase. However, when CKd1 changes from H to L, current 91 is current mirrored by TR91 and TR90. While being limited, and when CKd1 changes from L to H, the current 92 is limited by the current mirrored by TR94 and TR93, and when CKd1 changes from L to H, TR96 The current generated there is mirrored by TR97 and TR98 and added as a current for pulling up CK1d in the H direction, and the capacitance added to CK1d or the parasitic capacitance CAP91 is charged to change the voltage.

FIG. 8 shows a timing chart of the input control terminal voltage control means shown in FIG.
In FIG. 8, the change of CK1d immediately after time t0 is adjusted so as to be particularly gradual, so that a smaller amount of current flows for a long time in the initial stage of current generation, and most of the charge flows, so that the current peak is kept lower. .
Also, the change in the amount of current is made smaller, resulting in smaller unnecessary radiation.

  The amount of current supplied from the input signal is reduced by gently changing the gate potential of the charging speed control transistor switch by the signal CKd1 having the changing speed determined by the current source element TR90 or TR93 and the capacitor CAP91. In addition, the change in the amount of current is smoothed, and the change in the power supply voltage and the generation of unnecessary radiation are suppressed.

  In the case of this circuit, as compared with the first circuit in FIG. 2 or the second circuit in FIG. 5, the change in gate voltage of the charging speed control transistor switch at the time when the current starts to flow from the input signal has the same degree of gentleness. Since the asymptotic speed to the H level in the vicinity of the H level is faster, the sampling capacitor can be charged with a low impedance for a longer time, and the settling error can be further reduced.

[Fourth example]
A fourth embodiment of the present invention will be described with reference to FIG.
<Configuration>
The switched capacitor circuit according to the present invention includes a plurality of sampling capacitors for charging and discharging electric charge, and a plurality of charge timing control transistors for controlling the timing at which both ends of the plurality of sampling capacitors are charged to a desired voltage in the first period. A switch,
A plurality of discharge timing control transistor switches for controlling the timing of discharging charges stored in the plurality of sampling capacitors in the second period, and at least a part or all of the ends of the plurality of charge timing control transistor switches A charge speed control transistor switch connected between the common terminal and the terminal for applying the desired voltage, or one end of the plurality of discharge timing control transistor switches. A part or all of them are common terminals, and either a discharge speed control transistor switch connected between the common terminal and a terminal for supplying a voltage connected to discharge electric charge, and an input control terminal voltage control Means.

Here, the input control terminal voltage control means will be described.
If this input control terminal voltage control means has a charging speed control transistor switch, the charging speed control transistor switch is turned on in the first period and turned off in the second period, and changes from the off state to the fully on state. The input control terminal voltage of the charging speed control transistor switch may be controlled such that the transition time is longer than the transition time during which the charging timing control transistor switch changes from the OFF state to the fully ON state.

  Further, when the input control terminal voltage control means has a plurality of discharge speed control transistor switches, the input control terminal voltage control means turns off the discharge speed control transistor switch in the first period and turns it on in the second period. The input control terminal voltage of the discharge speed control transistor switch may be controlled so that the transition time for changing to the state is longer than the transition time for changing from the OFF state of the discharge timing control transistor switch to the fully ON state.

(Concrete example)
FIG. 9 shows a configuration example of the switched capacitor circuit.
In this example, a switched capacitor circuit is shown as a configuration example integrated on a semiconductor substrate using MOS transistors.

CAP31 and CAP34 are sampling capacitors that charge and discharge charges.
The N-type MOS transistors TS30, TS31, TS35, and TS36 are charge timing control transistor switches.
N-type MOS transistors TS32, TS33, TS37, and TS38 are discharge timing control transistor switches.
RS34 which is an N-type MOS transistor is a transistor switch for charge speed control.

  The integration capacitor CAP32 is connected to the operational amplifier 33 in a feedback manner, and its input is connected to TS33 and TS38. The integration capacitor CAP32 is an integrator that integrates the input signal with the period of the two-phase non-overlap clock signals CK1 and CK2. .

<Circuit operation>
The operation of this circuit will be described.
The operation of this circuit is the same as the timing chart of the operation of FIG. 3 of the circuit of FIG.

  RS34 is basically turned on when CK1 is H and turned off when CK1 is L, but the transition time from the off state to the fully on state is from the off state of TS30, TS31, TS35, and TS36. The input control terminal voltage control means 34 receives CK1 and generates a signal CK1d to control the gate terminal voltage of RS34 so as to be longer than the transition time for changing to the fully on state.

  That is, basically as in the operation of the integrator of FIG. 17, when CK1 is H (ie, high level), CAP31 and CAP34 are charged between the input signal voltage and the AGND voltage, and when CK2 is H, CAP31 and CAP34 are charged. The charged electric charge is transferred (that is, integrated) to the CAP 32.

  The timing of CK1, CK2, and CK1d and the state of the amount of current supplied from the input signal are the same as in the timing chart of FIG. 3 corresponding to the circuit of FIG.

According to this, when CK1 changes from L (ie, low level) to H and TS30, TS31, TS35, and TS36 change from the off state to the on state, charging of CAP31 and CAP34 starts, so that current flows rapidly. However, since the gate voltage change of RS34 is gentle at the beginning of the change start from the OFF state to the ON state, it does not turn on strongly and a large current does not flow in the input signal.
That is, sudden fluctuations in the power supply voltage and unnecessary radiation do not occur.

  In addition, the reason why an accurate sampling operation is possible, the arrangement of the charge timing control transistor switch, the arrangement of the discharge timing control transistor switch, the material of the sampling capacitor, the input control terminal voltage control means, etc. are described in the first embodiment. It can be easily understood according to the explanations of the examples to the third example.

[Fifth Example]
A fifth embodiment of the present invention will be described with reference to FIG.
<Configuration>
The switched capacitor circuit according to the present invention includes a plurality of sampling capacitors for charging and discharging electric charge, and a plurality of charge timing control transistors for controlling the timing at which both ends of the plurality of sampling capacitors are charged to a desired voltage in the first period. A switch,
A plurality of discharge timing control transistor switches for controlling the timing of discharging charges stored in the plurality of sampling capacitors in the second period, and at least a part or all of the plurality of charge timing control transistor switches in series A charge rate control transistor switch connected to a plurality of discharge timing control transistor switches connected in series to a part or all of the plurality of discharge timing control transistor switches, and input control terminal voltage control means It consists of.

Here, the input control terminal voltage control means will be described.
If this input control terminal voltage control means has a transistor switch for charge rate control, it turns on the transistor switch for charge rate control in the first period and turns it off in the second period, and changes from the off state to the fully on state. The input control terminal voltage of the charging speed control transistor switch may be controlled such that the transition time for the charging timing control transistor switch is longer than the transition time for changing from the OFF state to the fully ON state.

  Further, when the input control terminal voltage control means has a plurality of discharge speed control transistor switches, the input control terminal voltage control means turns off the discharge speed control transistor switch in the first period and turns it on in the second period. The input control terminal voltage of the discharge speed control transistor switch may be controlled so that the transition time for changing to the state is longer than the transition time for changing from the OFF state of the discharge timing control transistor switch to the fully ON state.

(Concrete example)
FIG. 10 shows a configuration example of the switched capacitor circuit.
In this example, a switched capacitor circuit is shown as a configuration example integrated on a semiconductor substrate using MOS transistors.
CAP41 and CAP44 are sampling capacitors that charge and discharge charges.
N-type MOS transistors TS40, TS41, TS45, and TS46 are charge timing control transistor switches.
N-type MOS transistors TS42, TS43, TS47, and TS48 are discharge timing control transistor switches.
The N-type MOS transistors RS44 and RS49 are charging speed control transistor switches.

  Integration capacitor CAP42. It is connected to the operational amplifier 43 in a feedback manner, and its input is connected to TS43 and TS48. The input signal is an integrator that integrates with the period of the two-phase non-overlap clock signals CK1 and CK2.

<Circuit operation>
The operation of this circuit will be described.
The operation of this circuit is the same as the timing chart of the operation of FIG. 3 of the circuit of FIG.

  RS44 and RS49 are basically turned on when CK1 is H and turned off when CK1 is L, but the transition time from the off state to the fully on state is the off state of TS40, TS41, TS45 and TS46. Input control terminal voltage control means 44 and input control terminal voltage control means 45 receive CK1 to generate a signal CK1d so that the gate terminal voltages of RS44 and RS49 are respectively set to be longer than the transition time for changing from the fully on state to the I have control.

  That is, basically, as in the operation of the integrator of FIG. 17, when CK1 is H (ie, high level), CAP41 and CAP44 are charged between the input signal voltage and the AGND voltage, and when CK2 is H, CAP41 and CAP44 are charged. The charged charge is transferred (that is, integrated) to the CAP 42.

  The timing of CK1, CK2, and CK1d and the state of the amount of current supplied from the input signal are the same as in the timing chart of FIG. 3 corresponding to the circuit of FIG.

According to this, when CK1 changes from L (ie, low level) to H and TS40, TS41, TS45, and TS46 change from the off state to the on state, the charging of CAP41 and CAP44 starts, so the current suddenly increases. At the beginning of the change from the OFF state to the ON state, the gate voltage change of RS44 and TS49 is gentle, so that it does not turn on strongly and a large current does not flow in the input signal.
That is, sudden fluctuations in the power supply voltage and unnecessary radiation do not occur.

  In addition, the reason why an accurate sampling operation is possible, the arrangement of the charge timing control transistor switch, the arrangement of the discharge timing control transistor switch, the material of the sampling capacitor, the input control terminal voltage control means, etc. are described in the first embodiment. It can be easily understood according to the explanations of the examples to the third example.

[Sixth example]
A sixth embodiment of the present invention will be described with reference to FIG.
<Configuration>
In the switched capacitor circuit shown in FIG. 10 of the fifth example described above, this circuit has a part or all of the input control terminals of a plurality of charge rate control transistor switches or a plurality of discharge rate control transistor switches. It is an example in the case of being configured as a common terminal.

(Concrete example)
FIG. 11 shows a configuration example of a switched capacitor circuit.
In this example, a switched capacitor circuit is shown as a configuration example integrated on a semiconductor substrate using MOS transistors.
CAP51 and CAP54 are sampling capacitors that charge and discharge charges.
N-type MOS transistors TS50, TS51, TS55, and TS56 are charge timing control transistor switches.
N-type MOS transistors TS52, TS53, TS57, and TS58 are discharge timing control transistor switches.
The N-type MOS transistors RS54 and RS59 are charging speed control transistor switches.

  The integration capacitor CAP52 is connected to the operational amplifier 53 in a feedback manner, and its input is connected to TS53 and TS58. The integration capacitor CAP52 is an integrator that integrates the input signal with the period of the two-phase non-overlap clock signals CK1 and CK2.

<Circuit operation>
The operation of this circuit will be described.
The operation of this circuit is the same as the timing chart of the operation of FIG. 3 of the circuit of FIG.

  RS54 and RS59 are basically turned on when CK1 is H and turned off when CK1 is L. The transition time from the off state to the fully on state is from the off state of TS50, TS51, TS55, and TS56. The input control terminal voltage control means 54 receives CK1 and generates a signal CK1d to control the gate terminal voltages of both RS54 and RS59 so as to be longer than the transition time for changing to the fully on state.

  That is, basically, similarly to the operation of the integrator of FIG. 17, when CK1 is H (that is, high level), CAP51 and CAP54 are charged between the input signal voltage and the AGND voltage, and when CK2 is H, CAP51 and CAP54 are charged. The charge that has been charged is transferred (that is, integrated) to the CAP 52.

  The timing of CK1, CK2, and CK1d and the state of the amount of current supplied from the input signal are the same as in the timing chart of FIG. 3 corresponding to the circuit of FIG.

According to this, when CK1 changes from L (that is, low level) to H and TS50, TS51, TS55, and TS56 change from the OFF state to the ON state, the charging of CAP51 and CAP54 starts, so the current suddenly increases. At the beginning of the change from the OFF state to the ON state, the gate voltage change of RS54 and TS59 is gentle, so that it does not turn on strongly and no large current flows through the input signal.
That is, sudden fluctuations in the power supply voltage and unnecessary radiation do not occur.

  In this example, the circuit configuration can be realized by a smaller number of input control terminal voltage control means than in the fifth example described above.

  In addition, the reason why an accurate sampling operation is possible, the arrangement of the charge timing control transistor switch, the arrangement of the discharge timing control transistor switch, the material of the sampling capacitor, the input control terminal voltage control means, etc. are described in the first embodiment. It can be easily understood according to the explanations of the examples to the third example.

[Seventh example]
A seventh embodiment of the present invention will be described with reference to FIGS.
<Configuration>
This circuit shows a modification of the connection configuration including the input control terminal voltage control means in the switched capacitor circuit shown in FIG. 1 of the first example described above.

FIG. 12 shows a configuration example of a switched capacitor circuit.
In this example, a switched capacitor circuit is shown as a configuration example integrated on a semiconductor substrate using MOS transistors.

The CAP 61 is a sampling capacitor that charges and discharges charges.
TS60 and TS64 which are N-type MOS transistors and TS61 which is a P-type MOS transistor are charge timing control transistor switches.
The N-type MOS transistors TS62 and TS63 are discharge timing control transistor switches.
RS65 which is an N-type MOS transistor and RS66 which is a P-type MOS transistor are charge speed control transistor switches.

  The integration capacitor CAP62 is connected in feedback to the operational amplifier 63, and its input is connected to TS63, the input of RS66 is connected to VDD which is a positive power supply voltage, and the input of RS65 is connected to VSS which is a negative power supply voltage. .

<Circuit operation>
The operation of this circuit will be described.
FIG. 13 shows a timing chart of the operation of this circuit shown in FIG.
When the input signal BIT0 is H, the CAP 61 is charged with a voltage between VDD and AGND. When the input signal BIT0 is L, the CAP 61 is charged with a voltage between VSS and AGND.

  The input signal is an integrator that is integrated according to the value of the input signal BIT0 in a cycle of CK1B that is an inversion of the two-phase non-overlap clock signals CK1, CK2, and CK1.

  RS66 is basically turned on when CK1B is L and turned off when CK1B is H, but the transition time from the off state to the fully on state is changed from the off state of TS60 and TS61 to the fully on state. The input control terminal voltage control means 64 receives CK1B, generates a signal CK1Bd, and controls the gate terminal voltage of RS66 so as to be longer than the changing transition time.

  RS65 is basically turned on when CK1 is H and turned off when CK1 is L, but the transition time from the off state to the fully on state is changed from the off state of TS60 and TS64 to the fully on state. In order to make the transition time longer than the changing transition time, the input control terminal voltage control means 65 receives CK1 and generates a signal CK1d to control the gate terminal voltage of RS65.

  That is, basically, similar to the operation of the integrator of FIG. 17, when CK1 is H (ie, high level), CAP61 is charged between VDD or VSS and AGND voltage, and when CK2 is H, CAP61 is charged. The stored charge is transferred (that is, integrated) to the CAP 62.

  FIG. 13 shows the timing of CK1, CK2, CK1B, CK1d, and CK1Bd and the state of the amount of current supplied from VDD and VSS.

According to this, when CK1 changes from L (ie, low level) to H, or CK1B changes from H to L and TS60, TS61 (or TS64) changes from the off state to the on state, CAP61 starts charging. Therefore, the current tends to flow rapidly, but at the beginning of the change from the OFF state to the ON state, the gate voltage change of RS65 (or RS66) is gentle, so that the input signal does not turn on strongly and a large current flows. Absent.
That is, sudden fluctuations in the power supply voltage and unnecessary radiation do not occur.

  In this example, the sampled voltages are VDD and VSS, but this is only an example, and any voltage may be used.

  In addition, this example can be used as a DA converter that converts a digital signal such as a digital delta-sigma DA converter into an analog signal.

  In addition, the reason why an accurate sampling operation is possible, the arrangement of the charge timing control transistor switch, the arrangement of the discharge timing control transistor switch, the material of the sampling capacitor, the input control terminal voltage control means, and the like are as described above. It can be easily understood according to the explanations of the examples to the third example.

[Eighth Example]
An eighth embodiment of the present invention will be described with reference to FIG.
<Configuration>
This circuit shows a modification of the connection configuration including the input control terminal voltage control means in the switched capacitor circuit shown in FIG. 11 of the sixth example.
FIG. 14 shows a configuration example of a switched capacitor circuit.

  In this example, a switched capacitor circuit is shown as a configuration example integrated on a semiconductor substrate using MOS transistors.

CAP101 and CAP104 are sampling capacitors that charge and discharge charges.
N-type MOS transistors TS100, TS104, TS107, TS111 and P-type MOS transistors TS101, TS108 are charge timing control transistor switches.
N-type MOS transistors TS102, TS103, TS109, and TS110 are discharge timing control transistor switches.
RS105 and RS112 which are N-type MOS transistors and RS106 and RS113 which are P-type MOS transistors are charge speed control transistor switches.

  The integration capacitor CAP102 is feedback-connected to the operational amplifier 103, and its input is connected to TS103 and TS110.

  The inputs of RS106 and TS113 are connected to VDD which is a positive power supply voltage, and the inputs of RS105 and RS112 are connected to VSS which is a negative power supply voltage.

<Circuit operation>
The operation of this circuit will be described.
The operation of this circuit is the same as the timing chart of the operation of FIG. 13 of the circuit of FIG.

  When the input signals BIT1 and BIT0 are H, CAP101 and CAP104 are charged with a voltage between VDD and AGND, respectively.

  When the input signals BIT1 and BIT0 are L, CAP101 and CAP104 are charged with a voltage between VSS and AGND, respectively.

  The input signal is an integrator that is integrated according to the values of the input signals BIT1 and BIT0 in a cycle of CK1B that is an inversion of the two-phase non-overlap clock signals CK1, CK2, and CK1.

  RS106 and RS113 are basically turned on when CK1B is L and turned off when CK1B is H, but the transition time from the off state to the fully on state is off of TS100, TS101, TS107, and TS108. The input control terminal voltage control means 104 receives CK1B and generates a signal CK1Bd to control the gate terminal voltages of RS106 and RS113 in common so as to be longer than the transition time for changing from the state to the fully on state.

  In addition, RS105 and RS112 are basically turned on when CK1 is H and turned off when CK1 is L, but the transition times for changing from the off state to the fully on state are TS100, TS104, TS107, and TS111. The input control terminal voltage control means 105 receives CK1 and generates a signal CK1d to control the gate terminal voltages of RS105 and TS112 in common so that the transition time from the OFF state to the fully ON state is longer.

  That is, basically, similar to the operation of the integrator of FIG. 17, when CK1 is H (ie, high level), CAP101 and CAP104 are charged between VDD or VSS and AGND voltage, and when CK2 is H, CA101, The electric charge charged in the CAP 104 is transferred (that is, integrated) to the CAP 102.

  The timing chart of FIG. 14 shows the timing of CK1, CK2, CK1B, CK1d, and CK1Bd and the state of the amount of current supplied from VDD and VSS. Although the input signal BIT1 is not written in FIG. 14, it is the same as the operation of BIT0.

According to this, CK1 changes from L (ie, low level) to H, or CK1B changes from H to L, and TS100, TS101 (or TS104), TS107, TS108 (or TS111) changes from the off state to the on state. Sometimes, the CAP101 starts to be charged, so that the current tends to flow rapidly, but at the beginning of the change from the OFF state to the ON state, the change in the gate voltage of the RS105 (or RS106) or RS112 (or RS113) is gradual. Therefore, it does not turn on strongly and a large current does not flow in the input signal.
That is, sudden fluctuations in the power supply voltage and unnecessary radiation do not occur.

  In this example, the sampled voltages are VDD and VSS. However, this is an example and any voltage may be used.

  In addition, this example can be used as a DA converter that converts a multi-bit digital signal into an analog signal by a digital delta-sigma DA converter, for example.

  In addition, the reason why an accurate sampling operation is possible, the arrangement of the charge timing control transistor switch, the arrangement of the discharge timing control transistor switch, the material of the sampling capacitor, the input control terminal voltage control means, and the like are as described above. It can be easily understood according to the explanations of the examples to the third example.

1 is a circuit diagram illustrating a configuration example of a switched capacitor circuit according to a first embodiment of the present invention. FIG. It is a circuit diagram which shows the circuit structural example of the 1st example of an input control terminal voltage control means. 2 is a timing chart showing an operation of the switched capacitor circuit shown in FIG. 1. It is a timing chart of an input control terminal voltage control means. It is a circuit diagram which shows the circuit structural example of the 2nd example of the input control terminal voltage control means which is the 2nd Embodiment of this invention. It is a timing chart of the input control terminal voltage control means shown in FIG. It is a circuit diagram which shows the circuit structural example of the 3rd example of the input control terminal voltage control means which is the 3rd Embodiment of this invention. It is a timing chart of the input control terminal voltage control means shown in FIG. It is a circuit diagram which shows the structural example of the switched capacitor circuit which is the 4th Embodiment of this invention. It is a circuit diagram which shows the structural example of the switched capacitor circuit which is the 5th Embodiment of this invention. It is a circuit diagram which shows the structural example of the switched capacitor circuit which is the 6th Embodiment of this invention. It is a circuit diagram which shows the structural example of the switched capacitor circuit which is the 7th Embodiment of this invention. 13 is a timing chart showing an operation of the switched capacitor circuit shown in FIG. It is a circuit diagram which shows the structural example of the switched capacitor circuit which is the 8th Embodiment of this invention. It is a circuit diagram which shows the structural example of the conventional switched capacitor circuit. 16 is a timing chart showing an operation of the switched capacitor circuit shown in FIG. It is a circuit diagram which shows the structural example of the conventional switched capacitor circuit. 18 is a timing chart showing an operation of the switched capacitor circuit shown in FIG.

Explanation of symbols

14 Input control terminal voltage control means 34 Input control terminal voltage control means 44 Input control terminal voltage control means 54 Input control terminal voltage control means 64 Input control terminal voltage control means 104, 105 Input control terminal voltage control means

Claims (18)

A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Means for controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in the first period;
Means for controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in the second period;
A charge / discharge rate control transistor switch connected in series to one terminal of the charge timing control transistor switch or one terminal of the discharge timing control transistor switch;
Here, the charge / discharge speed control transistor switch is constituted by a charge speed control transistor switch or a discharge speed control transistor switch,
A switched capacitor circuit comprising charge / discharge rate control means connected to an input control terminal of the charge / discharge rate control transistor switch for controlling a signal input to the input control terminal. A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Here, a plurality of sets of circuits in which the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are configured as one set are connected in parallel,
Means for controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in the first period;
Means for controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in the second period;
Charge / discharge speed control transistor switch connected in series to one common connection terminal of the charge timing control transistor switch connected in parallel or one common connection terminal of the discharge timing control transistor switch connected in parallel When,
Here, the charge / discharge speed control transistor switch is constituted by a charge speed control transistor switch or a discharge speed control transistor switch,
A switched capacitor circuit comprising charge / discharge rate control means connected to an input control terminal of the charge / discharge rate control transistor switch for controlling a signal input to the input control terminal. A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Here, a plurality of sets of circuits in which the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are configured as one set are connected in parallel,
Means for controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in the first period;
Means for controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in the second period;
A plurality of charging terminals connected in series to one connecting terminal of each pair of charging timing control transistor switches connected in parallel, or to one terminal of each pair of discharging timing control transistor switches connected in parallel, respectively. A transistor switch for controlling the discharge rate;
Here, the charge / discharge speed control transistor switch is constituted by a charge speed control transistor switch or a discharge speed control transistor switch,
Switched capacity comprising a plurality of charge / discharge speed control means connected to the input control terminals of the charge / discharge speed control transistor switches of the respective groups and controlling signals input to the input control terminals. Circuit. A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Here, a plurality of sets of circuits in which the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are configured as one set are connected in parallel,
Means for controlling the drive timing of the charge timing control transistor switch to charge the sampling capacitor to a desired voltage in the first period;
Means for controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in the second period;
A plurality of charging terminals connected in series to one connecting terminal of each pair of charging timing control transistor switches connected in parallel, or to one terminal of each pair of discharging timing control transistor switches connected in parallel, respectively. A transistor switch for controlling the discharge rate;
Here, the charge / discharge speed control transistor switch is constituted by a charge speed control transistor switch or a discharge speed control transistor switch,
Switched capacity comprising charge / discharge speed control means connected in common to the input control terminals of the charge / discharge speed control transistor switches of each set and controlling signals input to the input control terminals. Circuit. The charge / discharge rate control means includes:
When the charge / discharge speed control transistor switch is configured as a charge speed control transistor switch connected to the charge timing control transistor switch,
The charging speed control transistor switch is turned on in the first period and turned off in the second period,
The transition time for changing from the off state to the fully on state is made longer than the transition time for changing from the off state to the fully on state of the charge timing control transistor switch. 5. The switched capacitor circuit according to claim 1, wherein the voltage is controlled. The charge / discharge rate control means includes:
When the charge / discharge speed control transistor switch is configured as a discharge speed control transistor switch connected to the discharge timing control transistor switch,
The discharge speed control transistor switch is turned off in the first period and turned on in the second period,
The transition time for changing from the off state to the fully on state is longer than the transition time for changing from the off state to the fully on state of the discharge timing control transistor switch. 5. The switched capacitor circuit according to claim 1, wherein the voltage is controlled. The charge / discharge rate control means includes:
When the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state,
The charge control transistor switch or the input control signal terminal of the discharge speed control transistor switch is controlled by a signal that changes with a time constant determined by a circuit element including a resistor and a capacitor. The switched capacitor circuit according to claim 1. The charge / discharge rate control means includes:
When the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state,
A charge speed control transistor switch or an input control signal terminal of the discharge speed control transistor switch is controlled by a signal having a change speed determined by a circuit element including a current source element and a capacitor. The switched capacitor circuit according to claim 1. The charge / discharge rate control means includes:
When the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state,
The input control signal terminal of the charge speed control transistor switch or the discharge speed control transistor switch is controlled by a signal having a part having the fastest change speed in the middle of the state change immediately after the start of the state change. The switched capacitor circuit according to claim 1. A switch switching method of a switched capacitor circuit,
A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
A charge / discharge speed control transistor switch connected in series to one terminal of the charge timing control transistor switch or one terminal of the discharge timing control transistor switch, the charge / discharge speed control transistor switch Is a circuit configured by a transistor switch for charge rate control or a transistor switch for discharge rate control,
Controlling the drive timing of the charge timing control transistor switch in order to charge the sampling capacitor to a desired voltage in the first period;
Controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in a second period;
A switch switching method for a switched capacitor circuit, comprising: a charge / discharge rate control step of controlling a signal input to an input control terminal of the charge / discharge rate control transistor switch. A switch switching method of a switched capacitor circuit,
A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Here, a plurality of sets of circuits in which the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are configured as one set are connected in parallel,
Charge / discharge speed control transistor switch connected in series to one common connection terminal of the charge timing control transistor switch connected in parallel or one common connection terminal of the discharge timing control transistor switch connected in parallel The charge / discharge speed control transistor switch is a charge speed control transistor switch or a discharge speed control transistor switch.
Controlling the drive timing of the charge timing control transistor switch in order to charge the sampling capacitor to a desired voltage in the first period;
Controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in a second period;
A switch switching method for a switched capacitor circuit, comprising: a charge / discharge rate control step of controlling a signal input to an input control terminal of the charge / discharge rate control transistor switch. A switch switching method of a switched capacitor circuit,
A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Here, a plurality of sets of circuits in which the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are configured as one set are connected in parallel,
A plurality of charging terminals connected in series to one connecting terminal of each pair of charging timing control transistor switches connected in parallel, or to one terminal of each pair of discharging timing control transistor switches connected in parallel, respectively. A discharge speed control transistor switch, and the charge / discharge speed control transistor switch is a charge speed control transistor switch or a circuit configured by a discharge speed control transistor switch.
Controlling the drive timing of the charge timing control transistor switch in order to charge the sampling capacitor to a desired voltage in the first period;
Controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in a second period;
A switch switching method for a switched capacitor circuit, comprising: a plurality of charge / discharge speed control steps for controlling a signal input to an input control terminal of each set of charge / discharge speed control transistor switches. A switch switching method of a switched capacitor circuit,
A sampling capacitor for charging and discharging electric charge;
Two charge timing control transistor switches connected between both terminals of the sampling capacitor;
Two discharge timing control transistor switches connected between both terminals of the sampling capacitor;
Here, a plurality of sets of circuits in which the sampling capacitor, the two charge timing control transistor switches, and the two charge timing control transistor switches are configured as one set are connected in parallel,
A plurality of charging terminals connected in series to one connecting terminal of each pair of charging timing control transistor switches connected in parallel, or to one terminal of each pair of discharging timing control transistor switches connected in parallel, respectively. A discharge speed control transistor switch, the charge / discharge speed control transistor switch is constituted by a charge speed control transistor switch or a discharge speed control transistor switch,
Controlling the drive timing of the charge timing control transistor switch in order to charge the sampling capacitor to a desired voltage in the first period;
Controlling the drive timing of the discharge timing control transistor switch to discharge the charge stored in the sampling capacitor in a second period;
A switch switching method for a switched capacitor circuit, comprising: a charge / discharge rate control step for controlling a signal input in common to an input control terminal of each set of charge / discharge rate control transistor switches. The charge / discharge rate control step includes:
When the charge / discharge speed control transistor switch is configured as a charge speed control transistor switch connected to the charge timing control transistor switch,
The charging speed control transistor switch is turned on in the first period and turned off in the second period,
The transition time for changing from the off state to the fully on state is made longer than the transition time for changing from the off state to the fully on state of the charge timing control transistor switch. 14. The method for switching a switched capacitor circuit according to claim 10, wherein the voltage is controlled. The charge / discharge rate control step includes:
When the charge / discharge speed control transistor switch is configured as a discharge speed control transistor switch connected to the discharge timing control transistor switch,
The discharge speed control transistor switch is turned off in the first period and turned on in the second period,
The transition time for changing from the off state to the fully on state is longer than the transition time for changing from the off state to the fully on state of the discharge timing control transistor switch. 14. The method for switching a switched capacitor circuit according to claim 10, wherein the voltage is controlled. The charge / discharge rate control step includes:
When the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state,
The charge control transistor switch or the input control signal terminal of the discharge speed control transistor switch is controlled by a signal that changes with a time constant determined by a circuit element including a resistor and a capacitor. The switch switching method of the switched capacitor circuit according to claim 10. The charge / discharge rate control step includes:
When the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state,
A charge speed control transistor switch or an input control signal terminal of the discharge speed control transistor switch is controlled by a signal having a change speed determined by a circuit element including a current source element and a capacitor. The switch switching method of the switched capacitor circuit according to claim 10. The charge / discharge rate control step includes:
When the charge speed control transistor switch or the discharge speed control transistor switch changes from an off state to an on state,
The input control signal terminal of the charge speed control transistor switch or the discharge speed control transistor switch is controlled by a signal having a part having the fastest change speed in the middle of the state change immediately after the start of the state change. The switch switching method of the switched capacitor circuit according to claim 10.

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