JP2006086351A - Solid-state imaging device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device which suppresses the degradation of characteristics accompanied by miniaturization, and facilitates an electronic shuttering operation in an AGP. <P>SOLUTION: The solid-state imaging device comprises an identical conductive type n well 24 to a semiconductor substrate 20 formed in the surface region of the semiconductor substrate 20, a plurality of isolation regions which are disposed in substantially parallel to one another across a given distance in the surface region of the semiconductor substrate 20 and of reverse conductive types with respect to the semiconductor substrate 20 defining the n well 24, and a plurality of transfer electrodes 32 which extend in a direction intersecting with the isolation region on the semiconductor substrate 20 and are disposed in substantially parallel to one another. In the surface region of the semiconductor substrate 20 in which at least one of pairs of the transfer electrodes 32 constituting one pixel is provided, an n<SP>+</SP>region 29 having impurity density higher than the n well 24 is selectively formed, thereby solving the problem. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a CCD solid-state imaging device and a manufacturing method thereof.

  FIG. 9 is a schematic diagram showing a configuration of a frame transfer type CCD solid-state imaging device. The frame transfer type CCD solid-state imaging device basically includes an imaging unit 10i, a storage unit 10s, a horizontal transfer unit 10h, and an output unit 10d. In the imaging unit 10i, pixels of photoelectric conversion elements are arranged in a matrix. A plurality of photoelectric conversion elements are arranged as columns extending in the direction toward the storage unit 10s. Each column also serves as a vertical shift register and is arranged in parallel to each other. The light incident on the imaging unit 10i is converted into information charges by a photoelectric conversion element for each pixel, vertically transferred as information charges for each pixel, and output to the accumulation unit 10s. The accumulating unit 10s includes a light-shielded vertical shift register that is continuous with the vertical shift register of the imaging unit 10i. Information charges are once held in the storage unit 10s and then transferred to the horizontal transfer unit 10h line by line. The horizontal transfer unit 10h is composed of one row of horizontal shift registers extending in the direction toward the output unit 10d. The horizontal transfer unit 10h receives the information charge transferred from the storage unit 10s, and transfers the information charge to the output unit 10d in units of one pixel. The output unit 10d converts a charge amount for each pixel into a voltage value, and a change in the voltage value is taken out as a CCD output.

  FIG. 10 is a plan view showing the structure of an imaging unit 10i of a conventional CCD solid-state imaging device. FIG. 11 is a cross-sectional view illustrating a structure in which the imaging unit 10i illustrated in FIG. 10 is cut in the WW direction. 12 is a cross-sectional view illustrating a structure in which the imaging unit 10i illustrated in FIG. 10 is cut in the XX direction.

  A P well 22 to which a P type impurity is added is formed on an N type semiconductor substrate 20. An N well 24 to which an N-type impurity is added at a high concentration is formed in the surface region of the P well 22. In the N well 24, isolation regions 26 to which P-type impurities are added are arranged in parallel with each other at a predetermined interval Wc. The isolation region 26 has a width Wd. The N-well 24 is electrically partitioned by adjacent separation regions 26, and a region sandwiched between the separation regions 26 becomes a channel region 28 that is an information charge transfer path.

  An insulating film 30 is provided on the N well 24. Further, a plurality of transfer electrodes 32 are arranged in parallel to each other so as to intersect the extending direction of the channel region 28 via the insulating film 30. For example, a combination of three adjacent transfer electrodes 32-1, 32-2, and 32-3 constitutes one pixel. Three-phase transfer clocks φ1 to φ3 are applied to the transfer electrodes 32-1, 32-2, and 32-3 constituting one pixel. By applying the transfer clocks φ1 to φ3 with different phases, the potential wells formed in the channel regions 28 under the transfer electrodes 32-1, 32-2, and 32-3 are sequentially moved in the transfer direction to transfer information charges. Vertical transfer can be performed (for example, JP-A-2001-156284).

  Among CCD solid-state imaging devices having such a configuration, when information charges are accumulated in the imaging unit 10i at the time of imaging, an AGP (All There is a technology that uses a technique called Gates Pinning.

For example, as shown in FIG. 12, the surface of the semiconductor substrate 20 under one of the transfer electrodes 32-1, 32-2, and 32-3 (transfer electrode 32-2 in FIG. 12) constituting one pixel. An N ⁺ region to which a high concentration N-type impurity is added is selectively provided in the region. With such a structure, when information charges are accumulated in the imaging unit 10i, even when a negative potential is applied to all the transfer electrodes and the gates are turned off, the transfer provided with the N ⁺ region is provided. A potential well deeper than that under the other transfer electrodes 32-1 and 32-3 is formed under the electrode 32-2, and information charges can be accumulated. At this time, holes gather near the surface of the channel region 28 and are pinned to an interface state existing at the interface between the semiconductor substrate 20 and the insulating film 30. By filling the interface state with the pinned holes, the dark current generated during the exposure period can be reduced, and noise can be prevented from being mixed into the information charges generated along with the dark current.

JP 2001-156284 A

  CCD solid-state imaging devices are used in digital cameras and camera-equipped mobile phones, and miniaturization of CCD solid-state imaging devices is required because of the advantages of increasing pixel density and reducing power consumption to improve camera resolution. It has been.

  However, if the width Wc of the channel region 28 is reduced in order to reduce the size of the CCD solid-state imaging device, the influence of the separation region 26 on the channel region 28 increases, and the potential in the N well 24 of the channel region 28 increases. This produces a narrow channel effect where the profile changes. At this time, in order to maintain the characteristics of the CCD solid-state imaging device, it is necessary to reduce the dose of ions when forming the P well 22 as the width Wc of the channel region 28 becomes narrower. However, when the cell size is about several μm, it becomes close to the lower limit at which ion implantation can be controlled, and it becomes difficult to perform ion implantation with good reproducibility of the dose.

  Further, when an electronic shutter operation is performed to discharge the charges accumulated in the potential well to the deep part of the substrate by changing the substrate potential, there is a problem that it is difficult for the CCD solid-state imaging device to which AGP is applied to discharge the charges.

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a solid-state imaging device applied to AGP and a manufacturing method thereof while corresponding to the narrowing of the channel region.

  The solid-state imaging device according to the present invention includes a first semiconductor region having the same conductivity type as that of the semiconductor substrate formed in a surface region of one main surface of the semiconductor substrate, and a predetermined interval between the surface region of the one main surface of the semiconductor substrate. A plurality of isolation regions opposite to the semiconductor substrate that divide the first semiconductor region and extending in a direction intersecting the isolation region on the semiconductor substrate. A plurality of transfer electrodes arranged substantially in parallel with each other, and a surface region of the semiconductor substrate on which at least one of the set of transfer electrodes constituting one pixel is provided is higher than the first semiconductor region A second semiconductor region having an impurity concentration is selectively formed.

  Here, it is preferable that the isolation region is formed deeper than a boundary surface between the semiconductor substrate and the first semiconductor region.

  According to another aspect of the present invention, there is provided a method of manufacturing a solid-state imaging device, the first step of forming a first semiconductor region by implanting an impurity having the same conductivity type as the semiconductor substrate into one main surface of the semiconductor substrate; A second step of forming a second semiconductor region by implanting an impurity of the same conductivity type as that of the semiconductor substrate at an impurity concentration higher than that of the first semiconductor region into a part of a surface region of one main surface; Impurities having a conductivity type opposite to that of the semiconductor substrate are implanted substantially parallel to each other at a predetermined interval on one main surface of the semiconductor substrate to form a plurality of isolation regions and a channel region between the adjacent isolation regions And a fourth step of forming, on the semiconductor substrate, a plurality of transfer electrodes that intersect the plurality of isolation regions and are arranged substantially parallel to each other, and the second step. In this step, the transfer constituting one pixel is performed. At least one of the pair of electrodes, wherein the selectively forming the second semiconductor region in a surface region of said semiconductor substrate provided.

  Here, in the third step, it is preferable that the isolation region is formed deeper than a boundary surface between the semiconductor substrate and the first semiconductor region.

  According to the present invention, the deterioration of the characteristics accompanying the downsizing of the CCD solid-state imaging device is suppressed, and in the structure to which AGP is applied, the variation in the concentration of impurities added to the semiconductor substrate is reduced, and the substrate is lower than the conventional substrate. The electronic shutter operation is enabled by the potential.

<Structure of solid-state image sensor>
A CCD solid-state imaging device according to an embodiment of the present invention will be described in detail with reference to the drawings. The overall configuration of the CCD solid-state imaging device in the present embodiment is basically composed of an imaging unit 10i, a storage unit 10s, a horizontal transfer unit 10h, and an output unit 10d, as in FIG.

  FIG. 1 is a plan view of an imaging unit 10i of the CCD solid-state imaging device in the present embodiment. 2 and 3 show cross-sectional structures obtained by cutting the imaging unit 10i in the YY direction and the ZZ direction, respectively.

An N well 24 to which an N type impurity is added at a high concentration is formed in the surface region of the N type semiconductor substrate 20. As the semiconductor substrate 20, for example, a general semiconductor material such as a silicon substrate or a gallium arsenide substrate can be used. The concentration of the N-type impurity contained in the semiconductor substrate 20 is preferably 10 ¹⁴ / cm ³ or more and 10 ¹⁶ / cm ³ or less. Arsenic (As), phosphorus (P), antimony (Sb), or the like can be used as the N-type impurity added to the N well 24. The impurity concentration in the N well 24 is 10 ¹⁴ / cm ³ or more and 10 ¹⁷ / cm ³ or less is preferable, and more preferably 5.0 × 10 ¹⁴ / cm ³ or more and 10 ¹⁶ / cm ³ or less.

  In the N well 24, isolation regions 26 to which P-type impurities are added are arranged in parallel with each other at a predetermined interval Wc. The isolation region 26 has a width Wd. The N well 24 is electrically partitioned by two adjacent isolation regions 26, and a region partitioned by the isolation region 26 becomes a channel region 28 which is an information charge transfer path. In order to reduce the size of the CCD solid-state imaging device, the width Wd of the separation region 26 is preferably as narrow as possible within a range having an element separation capability. On the other hand, the width Wc of the channel region 28 is preferably 1 μm or more and 3 μm or less. The isolation region 26 is preferably formed deeper than the boundary surface between the semiconductor substrate 20 and the N well 24.

Boron (B), aluminum (Al), gallium (Ga), indium (In), or the like can be used as the P-type impurity added to the isolation region 26, and the impurity concentration in the isolation region 26 is 10 ¹⁵ / cm ^3. It is preferably 10 ¹⁹ / cm ³ or less, more preferably 10 ¹⁵ / cm ³ or more and 10 ¹⁸ / cm ³ or less.

  An insulating film 30 is provided on the N well 24. As the insulating film 30, a silicon-based material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film, a titanium oxide-based material, or the like can be used.

  A plurality of transfer electrodes 32 are arranged in parallel to each other on the insulating film 30 so as to be orthogonal to the extending direction of the channel region 28. The transfer electrode 32 can be made of a conductive material such as metal or polycrystalline silicon.

In the present embodiment, three transfer electrodes 32-1, 32-2, and 32-3 continuous in the extending direction of the channel region 28 constitute one pixel. Here, in the channel region 28, a region provided with one of the transfer electrodes 32-1, 32-2 and 32-3 constituting one pixel (referred to as the transfer electrode 32-2 in the present embodiment). An N ⁺ region 29 in which an N-type impurity is added at a high concentration is selectively provided in the surface region of the lower semiconductor substrate 20. The impurity concentration of the N ⁺ region 29 is preferably 10 ¹⁶ / cm ³ or more and 10 ¹⁸ / cm ³ or less.

  Three-phase transfer clocks φ1 to φ3 are applied to the transfer electrodes 32-1, 32-2, and 32-3. As a result, the potential of the channel region 28 under the transfer electrodes 32-1, 32-2, and 32-3 is controlled to store and transfer information charges.

4 and 5 are diagrams schematically showing a potential state from the surface of the semiconductor substrate 20 toward the deep part during imaging by AGP. FIG. 4 shows a potential distribution along the line AA under the transfer electrode 32-2 in which the N ⁺ region 29 is formed. FIG. 5 shows a potential distribution along the BB line between the transfer electrode 32-1 and the transfer electrode 32-3 in which the N ⁺ region 29 is not formed. The horizontal axis indicates the depth from the surface of the semiconductor substrate 20, the vertical axis indicates the potential at each position, the lower side is the positive potential side, and the upper side is the negative potential side. 4 and 5 show potential distributions when the transfer electrodes 32-1 and 32-3 have a potential of −4V, the transfer electrode 32-2 has a potential of −10V, and the substrate 20 has a potential of 7V.

Under the transfer electrode 32-2, the potential distribution spreads toward the channel region 28 due to the concentration difference between the P-type impurity concentration of the isolation region 26 and the N-type impurity concentration of the channel region 28. At this time, since the width Wc of the channel region 28 is narrow enough to form a potential barrier in the depth direction of the semiconductor substrate 20, the influence from the adjacent isolation region 26 becomes large, and the A of the channel region 28 is increased. -Dominates near the A line. Therefore, a potential well is formed in the N well 24 due to the influence of the N ⁺ region 29. That is, as shown in FIG. 4, the potential drops from the surface of the semiconductor substrate 20 to take a local minimum value in the N well 24, and the potential rises again toward the interface between the N well 24 and the semiconductor substrate 20 and near the interface. In this case, the maximum value is obtained, and the potential gradually decreases toward the deep part of the semiconductor substrate 20.

On the other hand, no potential well is formed in the N well 24 between the transfer electrode 32-1 and the transfer electrode 32-3 because the N ⁺ region 29 is not affected. That is, as shown in FIG. 5, the potential gradually decreases from the surface of the semiconductor substrate 20 toward the deep part of the substrate.

  As described above, according to the CCD solid-state imaging device of the present embodiment, even when the width Wc of the channel region is reduced, the potential in the N well 24 is generated by AGP that applies a negative potential to all the transfer electrodes 32. Wells can be formed. At the time of imaging, it is possible to store information charges in this potential well. When information charges exceeding the potential well accumulation capacity are generated, excess charges are discharged to a deep portion of the semiconductor substrate 20 across the potential barrier between the N well 24 and the semiconductor substrate 20.

  Further, by applying three-phase transfer clocks φ1 to φ3 having different phases for each combination of three consecutive transfer electrodes 32-1, 32-2, and 32-3, the transfer electrodes 32-1 and 32-2 are applied. , 32-3, the information well can be sequentially transferred by controlling the depth of the potential well in the channel region 28.

Further, it is possible to perform an electronic shutter operation for discharging charges by further increasing the potential of the semiconductor substrate 20. 6 and 7 are diagrams schematically showing a potential state from the surface of the substrate 20 toward the deep part during imaging by AGP. FIG. 6 shows a potential distribution along the line AA under the transfer electrode 32-2 in which the N ⁺ region 29 is formed. FIG. 7 shows a potential distribution along the BB line between the transfer electrode 32-1 and the transfer electrode 32-3 in which the N ⁺ region 29 is not formed. 6 and 7 show potential distributions when the transfer electrode 32 is set to a negative potential of several volts and the substrate 20 is set to a positive potential of several tens of volts.

  When a high positive potential is applied to the semiconductor substrate 20, no potential well is formed in the channel region 28 in any of the cases of FIGS. 6 and 7, and the potential is increased from the surface of the semiconductor substrate 20 toward the substrate deep portion. Decrease gradually. Therefore, by applying a high positive potential to the semiconductor substrate 20, the information charges accumulated in the potential well of the channel region 28 are discharged to the deep portion of the substrate 20.

  Although the structure of the imaging unit 10i has been described in the present embodiment, the same structure can be applied to the vertical shift register of the storage unit 10s.

<Method for Manufacturing Solid-State Imaging Device>
FIG. 8 is a process flow diagram of the manufacturing method of the CCD solid-state imaging device in the present embodiment. Here, a method for manufacturing only the imaging unit 10i of the CCD solid-state imaging device will be described, but a general method for manufacturing a CCD solid-state imaging device can be applied to the other components.

An N-type impurity is diffused in a region where an element is formed on the surface of the semiconductor substrate 20. For example, a silicon substrate can be used as the semiconductor substrate 20, and phosphorus (P) can be used as the N-type impurity. By this N-type impurity introduction step, an N well 24 is formed in the surface region of the semiconductor substrate 20 (FIG. 8A). Here, it is preferable that the effective N-type impurity concentration in the N well 24 is 10 ¹⁴ / cm ³ or more and 10 ¹⁶ / cm ³ or less.

Further, the surface of the semiconductor substrate 20 is covered with a resist pattern 40 having an opening along a region of the channel region 28 where the transfer electrode 32-2 is provided later, and N-type impurities are introduced at a high concentration using the resist pattern 42 as a mask. (FIG. 8B). By this N-type impurity introduction step, a high impurity concentration N ⁺ region 29 is formed. Here, the impurity concentration of the N ⁺ region 29 is preferably 10 ¹⁶ / cm ³ or more and 10 ¹⁸ / cm ³ or less.

Next, the resist pattern 40 is removed, and then the surface of the semiconductor substrate 20 is covered with a resist pattern 42 having openings having a width Wd and spaced apart from each other by a distance Wc so as to be orthogonal to the N ⁺ region 29. P-type impurities are introduced using 42 as a mask (FIG. 8C). For example, boron (B) can be used for the P-type impurity. By this P-type impurity introduction step, an isolation region 26 having a width Wd in the N well 24 and a channel region 28 having a width Wc are formed between these isolation regions 26. Here, the width Wc of the channel region 28 is 1 μm or more and 3 μm or less. The P-type impurity concentration in the isolation region 26 is preferably 10 ¹⁵ / cm ³ or more and 10 ¹⁹ / cm ³ or less. Further, the isolation region 26 can be formed deeper than the boundary surface between the semiconductor substrate 20 and the N well 24 by adjusting the number of times of ion implantation and its energy.

Next, after removing the resist pattern 40, a silicon oxide film is formed as the insulating film 30 so as to cover the isolation region 26 and the channel region 28. A polycrystalline silicon film is laminated on the insulating film 30, and the polycrystalline silicon film is patterned to form the transfer electrode 32 (FIG. 8D). At this time, the transfer electrodes 32-1 to 32-3 are arranged so that the transfer electrode 32-2 overlaps the N ⁺ region 29.

It is a top view which shows the structure of the imaging part of the solid-state image sensor in embodiment of this invention. It is sectional drawing which shows the structure of the imaging part of the solid-state image sensor in embodiment of this invention. It is sectional drawing which shows the structure of the imaging part of the solid-state image sensor in embodiment of this invention. It is a figure which shows the change of the potential to the N well depth direction at the time of the imaging which applied AGP. It is a figure which shows the change of the potential to the N well depth direction at the time of the imaging which applied AGP. It is a figure which shows the change of the potential to the N well depth direction at the time of an electronic shutter. It is a figure which shows the change of the potential to the N well depth direction at the time of an electronic shutter. It is a figure which shows the process flow of the manufacturing method of the solid-state image sensor in embodiment of this invention. It is the schematic which shows the structure of a CCD solid-state image sensor. It is a top view which shows the structure of the imaging part of the conventional solid-state image sensor. It is sectional drawing which shows the structure of the imaging part of the conventional solid-state image sensor. It is sectional drawing which shows the structure of the imaging part of the conventional solid-state image sensor.

Explanation of symbols

10i imaging unit, 10s storage unit, 10h horizontal transfer unit, 10d output unit, 20 semiconductor substrate, 22P well, 24N well, 26 isolation region, 28 channel region, 29N ⁺ region, 30 insulating film, 32 transfer electrode, 40, 42 Resist pattern.

Claims (4)

A first semiconductor region of the same conductivity type as the semiconductor substrate formed in a surface region of one main surface of the semiconductor substrate;
A plurality of isolation regions opposite in conductivity type to the semiconductor substrate, which are arranged substantially parallel to each other at a predetermined interval on a surface region of one main surface of the semiconductor substrate, and partition the first semiconductor region;
A plurality of transfer electrodes extending in a direction crossing the separation region on the semiconductor substrate and arranged substantially parallel to each other,
A second semiconductor region having an impurity concentration higher than that of the first semiconductor region is selectively formed in a surface region of the semiconductor substrate provided with at least one of the pair of transfer electrodes constituting one pixel. A solid-state imaging device. The solid-state imaging device according to claim 1,
The isolation region is formed deeper than a boundary surface between the semiconductor substrate and the first semiconductor region. A first step of forming a first semiconductor region by implanting impurities of the same conductivity type as the semiconductor substrate into one main surface of the semiconductor substrate;
A second semiconductor region is formed by implanting an impurity having the same conductivity type as that of the semiconductor substrate into a part of a surface region of one main surface of the semiconductor substrate at an impurity concentration higher than that of the first semiconductor region. Process,
Impurities having a conductivity type opposite to that of the semiconductor substrate are implanted substantially parallel to each other at a predetermined interval on one main surface of the semiconductor substrate to form a plurality of isolation regions and a channel region between the adjacent isolation regions A third step defining
A fourth step of forming a plurality of transfer electrodes that intersect the plurality of separation regions and are arranged substantially parallel to each other on the semiconductor substrate;
In the second step, the second semiconductor region is selectively formed in a surface region of the semiconductor substrate provided with at least one of the pair of transfer electrodes constituting one pixel. Device manufacturing method. In the manufacturing method of the solid-state image sensing device according to claim 3,
In the third step, the isolation region is formed deeper than a boundary surface between the semiconductor substrate and the first semiconductor region.

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