JP2006080786A

JP2006080786A - Thin film piezoelectric filter and manufacturing method thereof

Info

Publication number: JP2006080786A
Application number: JP2004261524A
Authority: JP
Inventors: Yoshihiko Goto; 義彦後藤; Hidetoshi Fujii; 英俊藤井; Masaki Takeuchi; 雅樹竹内
Original assignee: Murata Manufacturing Co Ltd
Current assignee: Murata Manufacturing Co Ltd
Priority date: 2004-09-08
Filing date: 2004-09-08
Publication date: 2006-03-23
Anticipated expiration: 2024-09-08
Also published as: JP4461972B2

Abstract

<P>PROBLEM TO BE SOLVED: To provide a piezoelectric device which can be made thinner than a conventional chip size package, and a manufacturing method thereof. <P>SOLUTION: In the piezoelectric device 10, a piezoelectric element 11 and a cover plate 30 are disposed in opposition to each other and has peripheral edge parts 17 and 35 joined. The piezoelectric element 11 includes an insulating film 12 having a center portion 12a projected from a peripheral portion 12b, a thin film part which is disposed in the projecting side of the center portion 12a of the insulating film 12 and consists of a pair of electrodes 14 and 18 facing each other and a piezoelectric film 16 interposed between the pair of electrodes 14 and 18, and pads 15 and 19 which are disposed in the projecting side of the peripheral portion 12b of the insulating film 12 and are electrically connected to the electrodes 14 and 18 respectively. The cover plate 30 includes; lands 32 and 34 which are formed on a surface in the side facing the piezoelectric element 11 and are joined to the pads 15 and 19 of the piezoelectric element 30; and external electrodes 31 and 33 which are formed on a surface opposite to the piezoelectric element 11 and are electrically connected to the lands 32 and 34. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、薄膜圧電フィルタ等の圧電デバイスおよびその製造方法に関し、詳しくは、チップサイズパッケージ型圧電デバイスの薄型化に関する。 The present invention relates to a piezoelectric device such as a thin film piezoelectric filter and a manufacturing method thereof, and more particularly, to a reduction in thickness of a chip size package type piezoelectric device.

従来、圧電素子サイズまでパッケージを小型化したＣＳＰ（チップサイズパッケージ）型圧電デバイスが開発されている。例えば、図１に示すＢＡＷフィルタ（バルク弾性波フィルタ）２は、共振子素子が形成された基板３の両側に、基板３と同サイズの蓋６，８が結合層７，９を介して貼り付けられている。共振子素子の振動部分４は、基板３，６から音響的に浮かせる必要があるため、Ｓｉの異方性エッチングを用いて基板３，６に空洞３ｘ，６ｘを形成している（例えば、特許文献１参照）。
特表２００４−５０３１６４号公報 2. Description of the Related Art Conventionally, a CSP (chip size package) type piezoelectric device in which a package is downsized to a piezoelectric element size has been developed. For example, in the BAW filter (bulk acoustic wave filter) 2 shown in FIG. 1, lids 6 and 8 having the same size as the substrate 3 are attached to both sides of the substrate 3 on which the resonator elements are formed via the coupling layers 7 and 9. It is attached. Since the vibrating portion 4 of the resonator element needs to be acoustically floated from the substrates 3 and 6, cavities 3x and 6x are formed in the substrates 3 and 6 using Si anisotropic etching (for example, patents). Reference 1).
JP-T-2004-503164

このような構造の圧電デバイスは、共振子素子を支持するＳｉ基板や、その両側に接合されるＳｉ基板が必須であるため、製品高さ（厚さ）が大きい。 The piezoelectric device having such a structure has a large product height (thickness) because an Si substrate supporting the resonator element and Si substrates bonded to both sides thereof are essential.

本発明は、かかる実情に鑑み、従来のチップサイズパッケージよりもさらに薄型化することができる、圧電デバイスおよびその製造方法を提供しようとするものである。 In view of such circumstances, the present invention intends to provide a piezoelectric device and a method for manufacturing the same that can be made thinner than a conventional chip size package.

本発明は、上記課題を解決するため、以下のように構成した圧電デバイスを提供する。 In order to solve the above-described problems, the present invention provides a piezoelectric device configured as follows.

圧電デバイスは、圧電素子と蓋板とが対向して配置され、周縁部が接合される。前記圧電素子は、中心部分が周辺部分に対して突出している絶縁膜と、前記絶縁膜の前記中心部分の突出側に配置された、対向する一対の電極及び該電極間に挟まれた圧電膜からなる薄膜部と、前記絶縁膜の前記周辺部分の前記突出側に配置され、前記電極にそれぞれ電気的に接続されたパッドとを有する。前記蓋板は、前記圧電素子に対向する側の面に形成され、前記圧電素子の前記パッドに接合されたランドと、前記圧電素子とは反対側の面に形成され、前記ランドに電気的に接続された外部電極とを有する。 In the piezoelectric device, the piezoelectric element and the cover plate are arranged to face each other, and the peripheral edge portion is joined. The piezoelectric element includes an insulating film having a central portion protruding from a peripheral portion, a pair of opposed electrodes disposed on the protruding side of the central portion of the insulating film, and a piezoelectric film sandwiched between the electrodes And a pad disposed on the projecting side of the peripheral portion of the insulating film and electrically connected to the electrode. The lid plate is formed on a surface facing the piezoelectric element, formed on a surface bonded to the pad of the piezoelectric element, and on a surface opposite to the piezoelectric element, and electrically connected to the land. A connected external electrode.

上記構成において、絶縁膜の中心部分と周辺部分との段差により形成される空間を、圧電素子の振動空間として用いることができる。薄膜部は、絶縁膜の周辺部分から退避した中心部分に配置されるので、圧電素子の片側（絶縁膜の中心部分の突出側）にのみ蓋板を配置することができる。したがって、圧電素子の両側に蓋板を配置する場合よりも、圧電デバイスを薄型化することができる。 In the above configuration, a space formed by a step between the central portion and the peripheral portion of the insulating film can be used as a vibration space of the piezoelectric element. Since the thin film portion is disposed in the central portion retracted from the peripheral portion of the insulating film, the cover plate can be disposed only on one side of the piezoelectric element (the protruding side of the central portion of the insulating film). Therefore, the piezoelectric device can be made thinner than in the case where the cover plates are arranged on both sides of the piezoelectric element.

好ましくは、前記蓋板を貫通するスルーホールが形成され、該スルーホールの一端が前記パッドに接続され、該スルーホールの他端が前記外部電極に接続される。 Preferably, a through hole penetrating the lid plate is formed, one end of the through hole is connected to the pad, and the other end of the through hole is connected to the external electrode.

上記構成によれば、パッドと外部電極との間の配線を短くして、圧電デバイスの電気特性を向上することができる。 According to the said structure, the wiring between a pad and an external electrode can be shortened, and the electrical property of a piezoelectric device can be improved.

好ましくは、前記圧電素子の前記蓋板が接合された面の反対側に接着されたフィルムを有する。これにより、外部からの有機物汚染、パーティクルの侵入などを遮断し、圧電素子の振動が阻害されないようにすることができる。 Preferably, the piezoelectric element has a film bonded to the opposite side of the surface to which the cover plate is bonded. Accordingly, it is possible to block organic contamination from the outside, intrusion of particles, and the like, so that the vibration of the piezoelectric element is not inhibited.

また、本発明は、以下のように構成された圧電デバイスの製造方法を提供する。 The present invention also provides a method of manufacturing a piezoelectric device configured as follows.

圧電デバイスの製造方法は、一方の面に間隔を設けて複数の凸部が形成された基板の該一方の面上に犠牲層を形成する工程と、前記犠牲層の上に、前記各凸部に対応して、絶縁膜と、一対の電極及び該電極間に挟まれた圧電膜からなる薄膜部をそれぞれ形成し、前記各凸部の近傍部分に前記電極にそれぞれ電気的に接続されたパッドを形成し、前記各凸部の近傍部分より外側の周縁に接合層をそれぞれ形成する工程と、蓋板基板の一方の面に、前記パッド及び前記接合層に対応する複数のランド及び接合層を形成し、該蓋板基板の前記一方の面を前記基板の前記一方の面に対向させ、対応する前記パッドと前記ランドとをそれぞれ接合するとともに、対応する前記接合層同士を接合する工程と、前記犠牲層をエッチングし、前記基板を前記絶縁膜から分離する工程と、前記基板を分離した前記絶縁膜と前記蓋板基板との間の部分を個々の圧電デバイスに分割する工程とを備える。 A method of manufacturing a piezoelectric device includes a step of forming a sacrificial layer on one surface of a substrate on which a plurality of convex portions are formed with a space on one surface, and each convex portion on the sacrificial layer. Corresponding to each of the pads, the insulating film, a pair of electrodes, and a thin film portion made of a piezoelectric film sandwiched between the electrodes, respectively, are formed, and the pads are electrically connected to the electrodes in the vicinity of the convex portions, respectively. Forming a bonding layer on the outer periphery of the vicinity of each convex portion, and a plurality of lands and bonding layers corresponding to the pad and the bonding layer on one surface of the cover plate substrate. Forming the one surface of the cover plate substrate to face the one surface of the substrate, bonding the corresponding pad and the land, and bonding the corresponding bonding layers; The sacrificial layer is etched to remove the substrate. And a step of separating from the membrane, and a step of dividing the portion between the cover plate substrate and the insulating film separating the substrate into individual piezoelectric device.

上記方法によれば、共振子素子の片側にのみ蓋板を設け、凸部が形成された基板を犠牲層のエッチングにより除去するので、圧電デバイスの低背化及び低コスト化を図ることができる。また、凸部が形成された基板は再使用できるので、製造コストの低減を図ることができる。 According to the above method, the cover plate is provided only on one side of the resonator element, and the substrate on which the convex portion is formed is removed by etching the sacrificial layer, so that the piezoelectric device can be reduced in height and cost. . In addition, since the substrate on which the convex portion is formed can be reused, the manufacturing cost can be reduced.

好ましくは、前記絶縁膜の前記蓋基板に接合された面の反対側にフィルムを接着する工程を備える。これにより、外部からの有機物汚染、パーティクルの侵入などを遮断し、圧電素子の振動が阻害されないようにすることができる。 Preferably, the method includes a step of adhering a film to the opposite side of the surface of the insulating film bonded to the lid substrate. Accordingly, it is possible to block organic contamination from the outside, intrusion of particles, and the like, so that the vibration of the piezoelectric element is not inhibited.

本発明の圧電デバイスおよびその製造方法によれば、従来のチップサイズパッケージよりもさらに薄型化することができる。 According to the piezoelectric device and the manufacturing method thereof of the present invention, it can be made thinner than the conventional chip size package.

以下、本発明の実施の形態として実施例を図２〜図６を参照しながら説明する。 Hereinafter, examples of the present invention will be described with reference to FIGS.

図２は、圧電デバイス１０の断面図である。圧電デバイス１０は、ＢＡＷフィルタである。圧電デバイス１０は、圧電素子１１の両側に、蓋板３０とフィルム４０がそれぞれ接合されている。 FIG. 2 is a cross-sectional view of the piezoelectric device 10. The piezoelectric device 10 is a BAW filter. In the piezoelectric device 10, a cover plate 30 and a film 40 are respectively bonded to both sides of the piezoelectric element 11.

圧電素子１１は、絶縁膜１２に、下部電極１４、圧電膜１６、上部電極１８が形成されている。絶縁膜１２は、断面凸状に形成され、中心の凸部１２ａが、周囲の平坦部１２ｂから突出するようになっている。絶縁膜１２の凸部１２ａには、電極１４，１８間に圧電膜１６が挟まれた薄膜部が配置される。電極１４，１８は、絶縁膜１２の平坦部１２ｂまでそれぞれ延在する。平坦部１２ｂにおいて、電極１４，１８上にそれぞれパッド１５，１９が形成され、パッド１５，１９より外側の周縁に沿って接合層１７が形成されている。 In the piezoelectric element 11, a lower electrode 14, a piezoelectric film 16, and an upper electrode 18 are formed on an insulating film 12. The insulating film 12 is formed in a convex shape in cross section, and the central convex portion 12a projects from the surrounding flat portion 12b. A thin film portion in which the piezoelectric film 16 is sandwiched between the electrodes 14 and 18 is disposed on the convex portion 12 a of the insulating film 12. The electrodes 14 and 18 extend to the flat portion 12b of the insulating film 12, respectively. In the flat portion 12 b, pads 15 and 19 are formed on the electrodes 14 and 18, respectively, and a bonding layer 17 is formed along the peripheral edge outside the pads 15 and 19.

蓋板３０は、圧電素子１１に対向する側の面に、ランド３２，３４が形成され、圧電素子１１のパッド１５，１９にそれぞれ接合されている。また、周縁に沿って接合層３５が形成され、圧電素子１１の接合層１７と接合されている。蓋板３０には、貫通穴に導電材を配置したスルーホール３１ｘ，３３ｘが形成され、スルーホール３１ｘ，３３ｘの両端が、外部電極３１，３３とランド３２，３４とにそれぞれ接続されている。 The lid plate 30 has lands 32 and 34 formed on the surface facing the piezoelectric element 11, and is joined to the pads 15 and 19 of the piezoelectric element 11, respectively. Further, a bonding layer 35 is formed along the periphery, and is bonded to the bonding layer 17 of the piezoelectric element 11. The cover plate 30 is formed with through holes 31x and 33x in which a conductive material is disposed in the through hole, and both ends of the through holes 31x and 33x are connected to the external electrodes 31 and 33 and the lands 32 and 34, respectively.

フィルム４０は、絶縁膜１２の平坦部１２ｂに接合され、圧電素子１１の凸部１２ａとの間に空間１１ｘを形成する。 The film 40 is bonded to the flat portion 12 b of the insulating film 12 and forms a space 11 x between the convex portion 12 a of the piezoelectric element 11.

次に、図３〜図６を参照しながら、圧電デバイス１０の製造工程および構成を説明する。図３〜図６は、最終形状の２個の圧電デバイス１０に相当する部分を図示しているが、実際には、複数個の圧電デバイス１０に相当する部分を、例えば升目状に二次元配置した基板の状態で製造する。 Next, the manufacturing process and configuration of the piezoelectric device 10 will be described with reference to FIGS. Although FIGS. 3 to 6 illustrate portions corresponding to the two piezoelectric devices 10 having the final shape, actually, the portions corresponding to the plurality of piezoelectric devices 10 are two-dimensionally arranged in a grid shape, for example. It is manufactured in the state of the substrate.

まず、絶縁膜１２に凸部１２ａを形成するための基板２０を作製する。 First, the substrate 20 for forming the convex portion 12a on the insulating film 12 is produced.

図３（ａ）に示すように、基板２０としてＳｉを用いる。基板２０の上にポリマーなどのレジストパターン２１を形成する。レジストパターン２１の断面形状は、緩やかな順テーパで、厚みは０．２μｍ以上、数十μｍ以下が好ましい。このレジストパターン２１は、グレートーンフォトマスクを用いて形成できる。 As shown in FIG. 3A, Si is used as the substrate 20. A resist pattern 21 such as a polymer is formed on the substrate 20. The cross-sectional shape of the resist pattern 21 is a gentle forward taper, and the thickness is preferably 0.2 μm or more and several tens of μm or less. The resist pattern 21 can be formed using a gray tone photomask.

この後、レジストパターン２１の形成された基板２０を、例えば、ＣＦ_４などのフッ素系のガスを用いて反応性イオンエッチング（ＲＩＥ）を行う。ＣＦ_４により、基板２０とレジストパターンの両方がエッチングされ、レジストパターンのテーパ形状が基板２０に転写され、図３（ｂ）に示すように、基板２０に凸部２２が形成される。レジストを残してエッチングを終了し、レジストを有機溶剤で剥離してもよい。レジストが完全にエッチングできるまでエッチングを続けてもよい。 Thereafter, the substrate 20 on which the resist pattern 21 is formed is subjected to reactive ion etching (RIE) using a fluorine-based gas such as CF ₄ , for example. Both the substrate 20 and the resist pattern are etched by CF ₄ , and the taper shape of the resist pattern is transferred to the substrate 20, so that a convex portion 22 is formed on the substrate 20 as shown in FIG. Etching may be completed while leaving the resist, and the resist may be peeled off with an organic solvent. Etching may continue until the resist is completely etched.

次に、図３（ｃ）に示すように、凸部２２を形成した基板２０上に、犠牲層２４を形成する。犠牲層２４として、例えばＺｎＯを０．２μｍ以上、数十μｍ以下の厚さで形成する。犠牲層２４として、Ａｌなどの金属又はポリマーを用いてもよい。 Next, as shown in FIG. 3C, a sacrificial layer 24 is formed on the substrate 20 on which the convex portions 22 are formed. As the sacrificial layer 24, for example, ZnO is formed with a thickness of 0.2 μm or more and several tens of μm or less. As the sacrificial layer 24, a metal such as Al or a polymer may be used.

この後、図４に示すように、犠牲層２４の上に、絶縁膜１２としてＳｉＯ_２膜を０．２μｍ以上、数十μｍ以下の厚さで形成する。この絶縁膜１２の上に、スパッタ、ＣＶＤ、電子ビーム蒸着などによる成膜と、フォトリソグラフィーによるパターニングを用いることにより、Ｍｏ、Ｐｔ、Ａｌ、Ａｕ、Ｃｕ、Ｔｉなどを主材にした下部電極１４を形成する。下部電極１４は、図４（ａ）に示すように、略Ｌ字状に第１片１４ａと第２片１４ｂが結合してなり、第１片１４ａは絶縁膜１２の凸部１２ａ上に帯状に形成され、第２片１４ｂは、図４（ｂ）に示すように、絶縁膜１２の凸部１２ａ上からテーパ部を経て平坦部１２ｂまで帯状に形成される。 Thereafter, as shown in FIG. 4, a SiO ₂ film is formed on the sacrifice layer 24 as the insulating film 12 with a thickness of 0.2 μm or more and several tens of μm or less. A lower electrode 14 mainly composed of Mo, Pt, Al, Au, Cu, Ti or the like is formed on the insulating film 12 by using sputtering, CVD, electron beam evaporation, or the like and patterning by photolithography. Form. As shown in FIG. 4A, the lower electrode 14 is formed by a first piece 14 a and a second piece 14 b being joined in a substantially L shape, and the first piece 14 a has a strip shape on the convex portion 12 a of the insulating film 12. As shown in FIG. 4B, the second piece 14b is formed in a band shape from the top of the convex portion 12a of the insulating film 12 to the flat portion 12b through the taper portion.

この下部電極１４上に、スパッタなどによる成膜と、フォトリソグラフィーによるパターニングを用いることにより、ＺｎＯやＡｌＮなどの圧電膜１６を形成する。圧電膜１６は、下部電極１４の第１片１４ａを完全に覆う。圧電膜１６は、ＡｌＮを形成する場合、耐熱性に優れたＺｎＯをレジストに用いて、リフトオフによりＡｌＮをパターニングしてもよい。また、ＡｌＮを全面に成膜して後、フォトリソグラフィーにより樹脂レジストマスクを形成し、エッチングでＡｌＮパターンを形成してもよい。 A piezoelectric film 16 such as ZnO or AlN is formed on the lower electrode 14 by using film formation by sputtering or the like and patterning by photolithography. The piezoelectric film 16 completely covers the first piece 14 a of the lower electrode 14. In the case of forming AlN, the piezoelectric film 16 may be patterned by lift-off using ZnO having excellent heat resistance as a resist. Alternatively, after AlN is formed on the entire surface, a resin resist mask may be formed by photolithography, and an AlN pattern may be formed by etching.

この圧電膜１６の上に、下部電極１４と同様に、上部電極１８，１８'を形成する。一方の上部電極１８は、下部電極１４の第２片１４ｂと一列に並び、下部電極１４の第２片１４ｂを反対側に向けて、絶縁膜１２の凸部１２ａ上からテーパ部を経て平坦部１２ｂまで、帯状に形成される。他方の上部電極１８'は、下部電極１４の第１片１４ａの先端側において、下部電極１４の第２片１４ｂ及び一方の上部電極１８と平行に、絶縁膜１２の凸部１２ａ上から両側にテーパ部を経て平坦部１２ｂまで、帯状に形成される。１つの圧電デバイス１０において、下部電極１４と上部電極１８とが２箇所で重なり合い、２つの共振子素子が形成される。 Similar to the lower electrode 14, upper electrodes 18 and 18 ′ are formed on the piezoelectric film 16. One upper electrode 18 is arranged in a line with the second piece 14b of the lower electrode 14, and the second piece 14b of the lower electrode 14 is directed to the opposite side so as to be flat from the convex part 12a of the insulating film 12 through a tapered part. Up to 12b, it is formed in a strip shape. The other upper electrode 18 ′ is parallel to the second piece 14 b of the lower electrode 14 and the one upper electrode 18 on the tip side of the first piece 14 a of the lower electrode 14 and on both sides from the convex portion 12 a of the insulating film 12. A band is formed from the tapered portion to the flat portion 12b. In one piezoelectric device 10, the lower electrode 14 and the upper electrode 18 are overlapped at two places to form two resonator elements.

この後、圧電素子１１のダイシングラインに沿って適宜部分（図示例では、各辺の中間部分）の絶縁膜１２を除去し、犠牲層２４の上面を露出させる適宜の数の犠牲層エッチホール１２ｘを形成する。形成方法は、フォトリソグラフィーを用いて開口を有するレジストマスクを形成後、ＣＦ_４を用いてＲＩＥを行い、絶縁膜１２に開口を形成して後、レジスト剥離する。絶縁膜１２としてＳｉＯ_２以外にＳｉ_３Ｎ_４等を用いても、同様に形成できる。 Thereafter, an appropriate portion (in the illustrated example, an intermediate portion of each side) of the insulating film 12 is removed along the dicing line of the piezoelectric element 11, and an appropriate number of sacrificial layer etch holes 12x exposing the upper surface of the sacrificial layer 24. Form. As a forming method, a resist mask having an opening is formed using photolithography, RIE is performed using CF ₄ to form an opening in the insulating film 12, and then the resist is peeled off. Even if Si ₃ N ₄ or the like is used as the insulating film 12 in addition to SiO ₂ , it can be formed similarly.

この後、圧電素子１１のパッド１５，１５'，１９，１９'と周縁の接合層１７に、Ｃｕ，Ｓｎの積層金属膜を、膜の形成しやすい０．１μｍ〜５０μｍの範囲で蒸着する。 Thereafter, a laminated metal film of Cu and Sn is deposited on the pads 15, 15 ′, 19, 19 ′ of the piezoelectric element 11 and the bonding layer 17 on the periphery in a range of 0.1 μm to 50 μm where the film is easily formed.

一方、図５に示すように、蓋板３０について、外部電極３１，３１'，３３，３３'やスルーホール３１ｘ，３１ｘ'，３３ｘ，３３ｘ'を形成し、ダイシングラインに沿って適宜部分に貫通穴３０ｘを形成する。また、ランド３２，３４と周縁の接合層３５として、Ｃｕ，Ｓｎの積層金属膜を、圧電素子１１と同様に蒸着により形成する。 On the other hand, as shown in FIG. 5, external electrodes 31, 31 ′, 33, 33 ′ and through holes 31 x, 31 x ′, 33 x, 33 x ′ are formed on the cover plate 30 and penetrate through appropriate portions along the dicing line. Hole 30x is formed. Also, as the bonding layer 35 between the lands 32 and 34 and the periphery, a Cu and Sn laminated metal film is formed by vapor deposition in the same manner as the piezoelectric element 11.

そして、圧電素子１１の凸部１２ａ側と蓋板３０のランド３２，３４を形成した面とを向き合せて、はんだのリフローを行い、圧電素子１１と蓋板３０の周縁の接合層１７，３５同士の接合と、パッド１５，１９とランド３２，３４の接合とを行う。 Then, the convex portion 12a side of the piezoelectric element 11 and the surface of the lid plate 30 on which the lands 32 and 34 are formed face each other, and solder reflow is performed, so that the bonding layers 17 and 35 on the periphery of the piezoelectric element 11 and the lid plate 30 are formed. The bonding between the pads 15 and 19 and the lands 32 and 34 is performed.

この後、犠牲層２４のエッチングを行う。蓋板３０の貫通穴３０ｘは、犠牲層エッチホール１２ｘに対応した位置に形成されており、この貫通穴３０ｘから侵入したエッチング液により、エッチホール１２ｘを介して犠牲層２４をエッチングする。エッチング液は、犠牲層２４がＺｎＯの場合、燐酸と酢酸の混合液を用いる。犠牲層２４がＡｌの場合、燐酸と酢酸と硝酸の混合液を用いる。犠牲層２４がポリマーの場合、アセトンなどの有機溶剤を用いる。 Thereafter, the sacrificial layer 24 is etched. The through hole 30x of the cover plate 30 is formed at a position corresponding to the sacrificial layer etch hole 12x, and the sacrificial layer 24 is etched through the etch hole 12x by the etchant entering from the through hole 30x. As the etching solution, when the sacrificial layer 24 is ZnO, a mixed solution of phosphoric acid and acetic acid is used. When the sacrificial layer 24 is Al, a mixed solution of phosphoric acid, acetic acid and nitric acid is used. When the sacrificial layer 24 is a polymer, an organic solvent such as acetone is used.

犠牲層２４のエッチングを終了すると、図６（ａ）に示した蓋板３０に接合された絶縁膜１２との間の部分から、Ｓｉ基板２０を分離し除去する。 When the etching of the sacrificial layer 24 is finished, the Si substrate 20 is separated and removed from the portion between the sacrificial layer 24 and the insulating film 12 bonded to the lid plate 30 shown in FIG.

この後、図６（ｂ）に示したように、蓋板３０に接合された絶縁膜１２について、絶縁膜１２の凸部１２ａに対応する凹部１１ｘをフィルム４０で覆い、外部からの有機物汚染、パーティクルの侵入を遮断する。フィルム４０の材質は、例えば、ポリイミドである。フィルムの厚さは０．２μｍ以上、数十μｍ以下のものが入手しやすい。この凹部１１ｘを共振子素子の振動空間として用いる。 Thereafter, as shown in FIG. 6B, the insulating film 12 bonded to the lid plate 30 is covered with the film 40 on the concave portion 11x corresponding to the convex portion 12a of the insulating film 12, and organic contamination from the outside, Block particle intrusion. The material of the film 40 is, for example, polyimide. A film having a thickness of 0.2 μm or more and several tens of μm or less is easily available. The recess 11x is used as a vibration space for the resonator element.

この後、ダイシングラインに沿って切断し、個別の圧電デバイス１０に分離する。 Thereafter, the wafer is cut along dicing lines and separated into individual piezoelectric devices 10.

以上に説明したように、圧電デバイス１０は、共振子素子を形成した基板の両側に蓋板を接合していた従来品に対し、一方の蓋板を無くすことができるため、低背化と低コスト化を実現できる。また、絶縁膜１２を形成する基板２０の材料に単結晶Ｓｉを用いて作製しているため、Ｓｉの結晶構造を継承して、膜質の良い圧電膜１６が成膜され、特性の良い圧電デバイスを実現できる。接合層１７，３５により気密封止構造とすることができ、湿度や腐食性雰囲気に弱い材質を使っている場合でも信頼性を確保できる。絶縁膜１２を形成する基板２０は再利用できるため、製造コストを低減することができる。 As described above, the piezoelectric device 10 can eliminate one cover plate from the conventional product in which the cover plate is bonded to both sides of the substrate on which the resonator element is formed. Cost reduction can be realized. In addition, since the single crystal Si is used as the material of the substrate 20 for forming the insulating film 12, the piezoelectric film 16 having good film quality is formed by inheriting the crystal structure of Si, and the piezoelectric device having good characteristics. Can be realized. The bonding layers 17 and 35 can provide a hermetically sealed structure, and reliability can be ensured even when a material that is weak in humidity or a corrosive atmosphere is used. Since the substrate 20 on which the insulating film 12 is formed can be reused, the manufacturing cost can be reduced.

なお、本発明の圧電デバイスおよびその製造方法は、上記した実施の形態に限定されるものではなく、種々変更を加え得て実施可能である。 The piezoelectric device and the manufacturing method thereof according to the present invention are not limited to the above-described embodiment, and can be implemented with various modifications.

圧電デバイスの断面図である。（従来例）It is sectional drawing of a piezoelectric device. (Conventional example) 圧電デバイスの断面図である。（実施例）It is sectional drawing of a piezoelectric device. (Example) 製造工程の説明図である。（実施例）It is explanatory drawing of a manufacturing process. (Example) 製造工程の説明図である。（ａ）は平面図、（ｂ）は（ａ）の線Ｂ−Ｂに沿って切断した断面図である。（実施例）It is explanatory drawing of a manufacturing process. (A) is a top view, (b) is sectional drawing cut | disconnected along line BB of (a). (Example) 製造工程の説明図である。（ａ）は平面図、（ｂ）は（ａ）の線Ｂ−Ｂに沿って切断した断面図である。（実施例）It is explanatory drawing of a manufacturing process. (A) is a top view, (b) is sectional drawing cut | disconnected along line BB of (a). (Example) 製造工程の説明図である。（実施例）It is explanatory drawing of a manufacturing process. (Example)

Explanation of symbols

１０圧電デバイス
１１圧電素子
１２絶縁膜
１２ａ凸部（中心部分）
１２ｂ平坦部（周辺部分）
１４，１４' 下部電極
１５パッド
１６圧電膜
１７接合層（周縁部）
１８，１８' 上部電極
１９パッド
３１，３１' 外部電極
３１ｘ，３１ｘ' スルーホール
３３，３３' 外部電極
３３ｘ，３３ｘ' スルーホール
３５接合層（周縁部）
３０蓋板
４０フィルム DESCRIPTION OF SYMBOLS 10 Piezoelectric device 11 Piezoelectric element 12 Insulating film 12a Convex part (central part)
12b Flat part (peripheral part)
14, 14 'Lower electrode 15 Pad 16 Piezoelectric film 17 Bonding layer (peripheral part)
18, 18 'Upper electrode 19 Pad 31, 31' External electrode 31x, 31x 'Through hole 33, 33' External electrode 33x, 33x 'Through hole 35 Bonding layer (peripheral part)
30 lid plate 40 film

Claims

A piezoelectric device in which a piezoelectric element and a cover plate are arranged to face each other, and a peripheral portion is joined.
The piezoelectric element is
An insulating film having a central portion protruding from a peripheral portion;
A thin film portion comprising a pair of opposed electrodes and a piezoelectric film sandwiched between the electrodes, disposed on the protruding side of the central portion of the insulating film;
A pad disposed on the protruding side of the peripheral portion of the insulating film and electrically connected to the electrodes,
The lid plate is
A land formed on a surface facing the piezoelectric element and bonded to the pad of the piezoelectric element;
A piezoelectric device comprising an external electrode formed on a surface opposite to the piezoelectric element and electrically connected to the land.

The through hole penetrating the cover plate is formed, one end of the through hole is connected to the pad, and the other end of the through hole is connected to the external electrode. Piezoelectric device.

3. The piezoelectric device according to claim 1, further comprising a film bonded to a side opposite to a surface to which the cover plate of the piezoelectric element is bonded. 4.

Forming a sacrificial layer on the one surface of the substrate on which a plurality of convex portions are formed with an interval on one surface;
On the sacrificial layer, an insulating film, a pair of electrodes, and a thin film portion composed of a piezoelectric film sandwiched between the electrodes are formed corresponding to the convex portions, respectively, and in the vicinity of the convex portions. Forming a pad electrically connected to each of the electrodes, and forming a bonding layer on a peripheral edge outside the vicinity of each convex portion; and
A plurality of lands and bonding layers corresponding to the pads and the bonding layer are formed on one surface of the cover plate substrate, and the one surface of the cover plate substrate is opposed to the one surface of the substrate. Bonding the pad and the land, respectively, and bonding the corresponding bonding layers;
Etching the sacrificial layer and separating the substrate from the insulating film;
A method for manufacturing a piezoelectric device, comprising: a step of dividing a portion between the insulating film and the cover plate substrate from which the substrate is separated into individual piezoelectric devices.

5. The method of manufacturing a piezoelectric device according to claim 4, further comprising a step of adhering a film to an opposite side of a surface of the insulating film bonded to the lid substrate.