JP2006080497A - Compound semiconductor device and manufacturing method therefor - Google Patents

Compound semiconductor device and manufacturing method therefor Download PDF

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JP2006080497A
JP2006080497A JP2005229934A JP2005229934A JP2006080497A JP 2006080497 A JP2006080497 A JP 2006080497A JP 2005229934 A JP2005229934 A JP 2005229934A JP 2005229934 A JP2005229934 A JP 2005229934A JP 2006080497 A JP2006080497 A JP 2006080497A
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Harumasa Yoshida
治正 吉田
Yasufumi Takagi
康文 高木
Masakazu Kuwabara
正和 桑原
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Hamamatsu Photonics KK
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<P>PROBLEM TO BE SOLVED: To provide a compound semiconductor device in which the occurrence of cracking is reduced, even when a plurality of semiconductor layers containing an AlGaN compound layer is made thicker, and to provide a method for manufacturing it. <P>SOLUTION: The compound semiconductor device 10 comprises a sapphire substrate 11, a GaN buffer layer 12 grown on the sapphire substrate 11, a GaN layer 13 grown on the GaN buffer layer 12 and has an irregular surface 13S, an AlN intermediate layer 14 grown on the irregular surface 13S of the GaN layer 13, a Al<SB>X1</SB>Ga<SB>Y1</SB>N compound layer 15 grown on the irregular surface 14S of the AlN intermediate layer 14, and an Al<SB>X2</SB>Ga<SB>Y2</SB>N compound layer 16, which is grown on the Al<SB>X1</SB>Ga<SB>Y1</SB>N compound layer 15 and satisfies the relational expression X1>X2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、サファイア基板上に成長させた複数の層を備える化合物半導体デバイス、及び化合物半導体デバイスの製造方法に関する。   The present invention relates to a compound semiconductor device including a plurality of layers grown on a sapphire substrate, and a method for manufacturing the compound semiconductor device.

紫外半導体レーザ素子用の結晶材料として、AlGaN系化合物の材料が知られている。この材料の基板としては通常、単結晶サファイア基板を用いる。例えば、この基板とnコンタクト層との間に、AlGaIn1−X−YNからなり、組成を段階的に変化させた複数の半導体層を積層して半導体層を構成する方法が報告されている(特許文献1)。 As a crystal material for an ultraviolet semiconductor laser element, an AlGaN-based compound material is known. A single crystal sapphire substrate is usually used as the substrate of this material. For example, there is a method in which a semiconductor layer is formed by stacking a plurality of semiconductor layers made of Al X Ga Y In 1- XYN and having the composition changed stepwise between the substrate and the n contact layer. It has been reported (Patent Document 1).

また、図1に示すように、この基板11上にバッファー層12を介してGaN層13を成長させ、その上にAlX2GaY2N系化合物層16を成長させる方法がある。これにより、AlX2GaY2N系化合物層16は、X線ロッキングカーブ半値幅(XRC FWHM)が改善されるが、GaN層13との格子不整合に起因する引張歪によりクラックが発生する問題がある。 As shown in FIG. 1, there is a method in which a GaN layer 13 is grown on the substrate 11 via a buffer layer 12 and an Al X2 Ga Y2 N-based compound layer 16 is grown thereon. As a result, the Al X2 Ga Y2 N-based compound layer 16 has an improved X-ray rocking curve half width (XRC FWHM), but there is a problem that cracks are generated due to tensile strain caused by lattice mismatch with the GaN layer 13. is there.

これらの問題を解決する方法として、クラックフリーで良好な結晶品質を有するAlX2GaY2N系化合物層16を成長させる方法が報告されている(非特許文献1〜6)。これは、図2に示すように、サファイア基板11上にバッファー層12を介してGaN層13を成長させ、その上にAlN中間層14を成長させ、さらにその上にAlX2GaY2N系化合物層16を成長させる方法である。これによりAlX2GaY2N系化合物層16はクラックフリーとなり、さらにその上に複数の半導体層を成長させることが可能である。 As a method for solving these problems, a method of growing an Al X2 Ga Y2 N-based compound layer 16 having a crack-free and good crystal quality has been reported (Non-Patent Documents 1 to 6). As shown in FIG. 2, a GaN layer 13 is grown on a sapphire substrate 11 via a buffer layer 12, an AlN intermediate layer 14 is grown thereon, and an Al X2 Ga Y2 N-based compound is further formed thereon. This is a method of growing the layer 16. As a result, the Al X2 Ga Y2 N-based compound layer 16 becomes crack-free, and a plurality of semiconductor layers can be further grown thereon.

なお、図2に示す構造では、転位密度の低減のために、サファイア基板11上のGaN層13を周期的なストライプ状にエッチングした後、AlN中間層14を成長させ、さらにその上にAlX2GaY2N系化合物層16を埋め込み成長させており、これにより転位密度の低減が実現できることが報告されている(特許文献2参照)。
特開2001−230447号公報 特開2002−16009号公報 M. Iwaya et al, 5th International Conference onNitride Semiconductor (ICNS-5), Technical Digest, Tu-P2.080 H. Amano et al., "IMPROVEMENT OF CRYSTALLINEQUALITY OF GROUP III NITRIDES ON SAPPHIRE USING LOW TEMPERATUREINTERLAYERS", MRS Internet J. Nitride Semicond. Res. 4S1, G10.1(1999). M. Iwaya et al., "HIGH-QUALITYAlxGa1-xN USING LOW TEMPERATURE-INTERLAYER AND ITS APPLICATION TO UVDETECTOR", MRS Internet J. Nitride Semicond. Res. 5S1, W1.10(2000). M. Iwaya et al., "High-EfficiencyGaN/AlxGaN1-xN Multi-Quantum Well Light Emitter Grown on Low-DislocationDensity AlxGa1-xN", IPAP Conf. Series, 1(2000)833. J. Han et al., "Control andelimination of cracking of AlGaNusinglow-temperature AlGaN interlayers", Appl. Phys. Lett. 78(2001)67. M. Iwaya et al., "Suppression ofphase separation of AlGaN during lateral growth and fabrication ofhigh-efficiency UV-LED on optimized AlGaN", J. Cryst. Growth237-239(2002)951.
In the structure shown in FIG. 2, in order to reduce the dislocation density, after etching the GaN layer 13 on the sapphire substrate 11 in the periodic stripes, the AlN intermediate layer 14 is grown and the Al thereon X2 It has been reported that a Ga Y2 N-based compound layer 16 is embedded and grown, whereby a reduction in dislocation density can be realized (see Patent Document 2).
JP 2001-230447 A JP 2002-16209 A M. Iwaya et al, 5th International Conference onNitride Semiconductor (ICNS-5), Technical Digest, Tu-P2.080 H. Amano et al., "IMPROVEMENT OF CRYSTALLINEQUALITY OF GROUP III NITRIDES ON SAPPHIRE USING LOW TEMPERATUREINTERLAYERS", MRS Internet J. Nitride Semicond. Res. 4S1, G10.1 (1999). M. Iwaya et al., "HIGH-QUALITYAlxGa1-xN USING LOW TEMPERATURE-INTERLAYER AND ITS APPLICATION TO UVDETECTOR", MRS Internet J. Nitride Semicond. Res. 5S1, W1.10 (2000). M. Iwaya et al., "High-EfficiencyGaN / AlxGaN1-xN Multi-Quantum Well Light Emitter Grown on Low-DislocationDensity AlxGa1-xN", IPAP Conf. Series, 1 (2000) 833. J. Han et al., "Control andelimination of cracking of AlGaNusinglow-temperature AlGaN containings", Appl. Phys. Lett. 78 (2001) 67. M. Iwaya et al., "Suppression of phase separation of AlGaN during lateral growth and fabrication of high-efficiency UV-LED on optimized AlGaN", J. Cryst. Growth 237-239 (2002) 951.

しかしながら、上記のAlN中間層の技術を用いて紫外半導体レーザ素子用の結晶成長を行ったところ、AlGaN系化合物層を含む複数の半導体層において高密度のクラックが発生した。このようにAlN中間層の技術は必ずしも有効ではなく、AlGaN系化合物層を含む複数の半導体層の膜厚の増加により引張歪が蓄積された結果、ある膜厚すなわち臨界膜厚より厚くなるとクラックが発生するという問題がある。   However, when crystal growth for an ultraviolet semiconductor laser device was performed using the AlN intermediate layer technique described above, high-density cracks were generated in a plurality of semiconductor layers including an AlGaN-based compound layer. As described above, the AlN intermediate layer technology is not always effective, and as a result of the accumulation of tensile strain due to the increase in film thickness of a plurality of semiconductor layers including the AlGaN-based compound layer, cracks occur when the film thickness exceeds a certain film thickness, that is, the critical film thickness. There is a problem that occurs.

本発明は、このような問題点に鑑みてなされたものであり、AlGaN系化合物層を含む複数の半導体層を厚くさせてもクラックの発生が低減される、化合物半導体デバイス、及び化合物半導体デバイスの製造方法を提供することを目的とする。   The present invention has been made in view of such a problem, and a compound semiconductor device and a compound semiconductor device in which generation of cracks is reduced even if a plurality of semiconductor layers including an AlGaN-based compound layer are increased in thickness are provided. An object is to provide a manufacturing method.

上述の課題を解決するため、本発明の化合物半導体デバイスは、GaN層と、GaN層上に成長させたAlN中間層と、AlN中間層上に成長させたAlX1GaY1N系化合物層と、AlX1GaY1N系化合物層上に成長させ、X1>X2なる関係式を満たすAlX2GaY2N系化合物層とを備えることを特徴とする。 In order to solve the above problems, a compound semiconductor device of the present invention includes a GaN layer, an AlN intermediate layer grown on the GaN layer, an Al X1 Ga Y1 N-based compound layer grown on the AlN intermediate layer, And an Al X2 Ga Y2 N-based compound layer that is grown on the Al X1 Ga Y1 N-based compound layer and satisfies a relational expression of X1> X2.

なお、本発明の化合物半導体デバイスは、サファイア基板と、サファイア基板上に成長され、GaN層がその上に成長したGaNバッファー層とを更に備えることもできる。GaNバッファ層はサファイア基板とGaN層との間の格子不整合を緩和し、サファイア基板上に形成されるGaN層の結晶性を向上させることができる。   The compound semiconductor device of the present invention can further include a sapphire substrate and a GaN buffer layer grown on the sapphire substrate and having a GaN layer grown thereon. The GaN buffer layer can relax the lattice mismatch between the sapphire substrate and the GaN layer, and can improve the crystallinity of the GaN layer formed on the sapphire substrate.

なお、本発明の化合物半導体デバイスは、GaN層はGaN基板とすることもできる。GaN層をGaN基板とする場合、サファイア基板が不要となるため、格子不整合が生じず、各層の結晶性の劣化を抑制することができる。   In the compound semiconductor device of the present invention, the GaN layer can be a GaN substrate. In the case where the GaN layer is a GaN substrate, a sapphire substrate is not required, so that lattice mismatch does not occur and deterioration of crystallinity of each layer can be suppressed.

ここで、AlN中間層とAlX2GaY2N系化合物層との間に、AlX1GaY1N系化合物層を成長させている。AlX2GaY2N系化合物層には、層の膜厚が増加するとともに引張歪が蓄積される。ここでは、X1>X2であるため、AlX1GaY1N系化合物層よりも格子定数が大きいAlX2GaY2N系化合物層は、圧縮歪を受ける。これにより、クラックの発生原因となる引張歪が、圧縮歪により相殺される。この構成によれば、化合物半導体デバイスのAlX2GaY2N系化合物層の表面上のクラックの発生が低減される。さらに、この層の上に成長させる複数の半導体層を厚くさせてもクラックの発生が低減される。 Here, an Al X1 Ga Y1 N-based compound layer is grown between the AlN intermediate layer and the Al X2 Ga Y2 N-based compound layer. In the Al X2 Ga Y2 N-based compound layer, the tensile strain is accumulated as the layer thickness increases. Here, since X1> X2, the Al X2 Ga Y2 N-based compound layer having a larger lattice constant than the Al X1 Ga Y1 N-based compound layer is subjected to compressive strain. Thereby, the tensile strain causing the generation of cracks is offset by the compressive strain. According to this arrangement, generation of cracks on the surface of Al X2 Ga Y2 N-based compound layer of the compound semiconductor device is reduced. Furthermore, even if a plurality of semiconductor layers grown on this layer are made thick, the generation of cracks is reduced.

なお、Y1及びY2は0以上1以下であり、AlX1GaY1N系化合物層及びAlX2GaY2N系化合物層が3元混晶の場合は、Y1及びY2はそれぞれ1−X1及び1−X2である。また、AlX1GaY1N系化合物層及びAlX2GaY2N系化合物層が4元混晶の場合は、Y1及びY2は、それぞれX1との和及びX2との和が1より小さくなる。 Y1 and Y2 are 0 or more and 1 or less, and when the Al X1 Ga Y1 N-based compound layer and the Al X2 Ga Y2 N-based compound layer are ternary mixed crystals, Y1 and Y2 are 1-X1 and 1- X2. When the Al X1 Ga Y1 N-based compound layer and the Al X2 Ga Y2 N-based compound layer are quaternary mixed crystals, Y1 and Y2 have a sum of X1 and a sum of X2 smaller than 1, respectively.

また、GaN層は凹凸表面を有し、AlN中間層はGaN層の凹凸表面上に成長し、AlX1GaY1N系化合物層はAlN中間層の凹凸表面上に成長した構造も好ましい。これは、凹部では、横方向への埋め込み成長が起こり、横方向成長の過程で転位等の欠陥が横方向に曲げられる。この結果、AlX2GaY2N系化合物層の領域の欠陥密度を低減できる。 Further, a structure in which the GaN layer has an uneven surface, the AlN intermediate layer grows on the uneven surface of the GaN layer, and the Al X1 Ga Y1 N-based compound layer grows on the uneven surface of the AlN intermediate layer is also preferable. This is because, in the concave portion, lateral growth occurs, and defects such as dislocations are bent in the lateral direction during the lateral growth process. As a result, the defect density in the region of the Al X2 Ga Y2 N-based compound layer can be reduced.

また、GaN層の凹凸表面の凹凸は、ストライプ状に交互に配置されていることも好ましい。これにより、欠陥が残存する領域と欠陥が低減された領域とが交互に配置され、欠陥密度がさらに低減される。   It is also preferable that the irregularities on the irregular surface of the GaN layer are alternately arranged in stripes. Thereby, the area | region where a defect remains and the area | region where the defect was reduced are arrange | positioned alternately, and a defect density is further reduced.

また、AlX1GaY1N系化合物層はAlX1GaY1Nからなり、AlX2GaY2N系化合物層はX1>X2なる関係式を満たすAlX2GaY2Nからなることも好ましい。これにより、AlX1GaY1N系化合物層とAlX2GaY2N系化合物層とは、それぞれAlX1GaY1NとAlX2GaY2Nとからなる場合でも、AlGaN系化合物層を含む複数の半導体層を厚くさせてもクラックの発生が低減されることが可能となる。 The Al X1 Ga Y1 N-based compound layer is preferably made of Al X1 Ga Y1 N, and the Al X2 Ga Y2 N-based compound layer is preferably made of Al X2 Ga Y2 N satisfying the relational expression X1> X2. Thereby, even if the Al X1 Ga Y1 N-based compound layer and the Al X2 Ga Y2 N-based compound layer are composed of Al X1 Ga Y1 N and Al X2 Ga Y2 N, respectively, a plurality of semiconductors including the AlGaN-based compound layer Even if the layer is made thick, the generation of cracks can be reduced.

また、本発明の化合物半導体デバイスの製造方法は、(1)GaN層を、凹凸表面を有するように加工する凹凸加工工程と、(2)当該加工したGaN層の凹凸表面上にAlN中間層を成長させる中間層成長工程と、(3)AlN中間層の凹凸表面上にAlX1GaY1N系化合物層を成長させて、AlX1GaY1N系化合物層上にX1>X2なる関係式を満たすAlX2GaY2N系化合物層を成長させる化合物層成長工程とを含むことを特徴とする。 In addition, the method for manufacturing a compound semiconductor device of the present invention includes (1) a concavo-convex processing step for processing a GaN layer so as to have a concavo-convex surface, and (2) an AlN intermediate layer on the concavo-convex surface of the processed GaN layer. And (3) growing an Al X1 Ga Y1 N-based compound layer on the concavo-convex surface of the AlN intermediate layer and satisfying a relational expression X1> X2 on the Al X1 Ga Y1 N-based compound layer And a compound layer growth step of growing an Al X2 Ga Y2 N-based compound layer.

これにより、デバイス表面上のクラックの発生が低減され、AlGaN系化合物層を含む複数の半導体層を厚くさせてもクラックの発生が低減される化合物半導体デバイスが提供される。これは、AlX2GaY2N系化合物層には、層の膜厚が増加するとともに引張歪が蓄積され、一方、X1>X2であるため、AlX1GaY1N系化合物層よりも格子定数が大きいAlX2GaY2N系化合物層は圧縮歪を受ける結果、クラックの発生原因となる引張歪が圧縮歪により相殺されるからである。 Thereby, the occurrence of cracks on the device surface is reduced, and a compound semiconductor device is provided in which the occurrence of cracks is reduced even when the plurality of semiconductor layers including the AlGaN-based compound layer is thickened. This is because, in the Al X2 Ga Y2 N-based compound layer, the tensile strain is accumulated as the layer thickness increases. On the other hand, since X1> X2, the lattice constant is higher than that of the Al X1 Ga Y1 N-based compound layer. This is because the large Al X2 Ga Y2 N-based compound layer is subjected to compressive strain, and as a result, the tensile strain that causes cracks is offset by the compressive strain.

なお、本発明の化合物半導体デバイスの製造方法は、サファイア基板上にGaNバッファー層を成長させ、GaNバッファー層上にGaNバッファー層より厚いGaN層を成長させるGaN層成長工程を更に備えることができる。サファイア基板を用いる場合、GaNバッファ層をサファイア基板とGaN層との間に介在させることにより、格子不整合を緩和し、GaN層の結晶性を向上させることができる。   In addition, the manufacturing method of the compound semiconductor device of this invention can be further equipped with the GaN layer growth process which grows a GaN buffer layer on a sapphire substrate, and grows a GaN layer thicker than a GaN buffer layer on a GaN buffer layer. When a sapphire substrate is used, the GaN buffer layer is interposed between the sapphire substrate and the GaN layer, so that lattice mismatch can be alleviated and the crystallinity of the GaN layer can be improved.

また、本発明の化合物半導体デバイスの製造方法は、GaN基板をGaN層とするGaN基板準備工程を更に備えることができる。市販のGaN基板を準備して用いる場合、サファイア基板を用いる必要がないため、上記のような格子不整合が生じず、各層の結晶性の劣化を抑制することができる。   Moreover, the manufacturing method of the compound semiconductor device of this invention can further comprise the GaN substrate preparation process which uses a GaN substrate as a GaN layer. When a commercially available GaN substrate is prepared and used, since it is not necessary to use a sapphire substrate, the lattice mismatch as described above does not occur, and deterioration of crystallinity of each layer can be suppressed.

本発明によれば、AlGaN系化合物層を含む複数の半導体層を厚くさせてもクラックの発生が低減される、化合物半導体デバイス、及び化合物半導体デバイスの製造方法を提供することができる。   ADVANTAGE OF THE INVENTION According to this invention, even if it makes the several semiconductor layer containing an AlGaN-type compound layer thick, generation | occurrence | production of a crack can be provided, and the manufacturing method of a compound semiconductor device can be provided.

以下、本発明の実施の形態に係る化合物半導体デバイス、及び化合物半導体デバイスの製造方法について説明する。なお、同一要素には同一符号を用い、重複する説明は省略する。また、図面の寸法比率は、説明のものと必ずしも一致していない。さらに、本発明はこれに限定されるものではない。   Hereinafter, a compound semiconductor device and a method for manufacturing the compound semiconductor device according to an embodiment of the present invention will be described. In addition, the same code | symbol is used for the same element and the overlapping description is abbreviate | omitted. Further, the dimensional ratios in the drawings do not necessarily match those described. Furthermore, the present invention is not limited to this.

化合物半導体デバイス10の構成について説明する。   The configuration of the compound semiconductor device 10 will be described.

図3は、本実施形態に係る化合物半導体デバイス10の断面図である。   FIG. 3 is a cross-sectional view of the compound semiconductor device 10 according to the present embodiment.

この化合物半導体デバイス10は、サファイア基板11と、サファイア基板11上に成長させたGaNバッファー層(以下、「バッファー層」と称す。)12と、バッファー層12上に成長させ、凹凸表面13Sを有するGaN層13と、GaN層13の凹凸表面13S上に成長させたAlN中間層(以下、「中間層」と称す。)14と、中間層14の凹凸表面14S上に成長させたAlX1GaY1N系化合物層15と、AlX1GaY1N系化合物層15上に成長させたAlX2GaY2N系化合物層16と、を備えている。 This compound semiconductor device 10 has a sapphire substrate 11, a GaN buffer layer (hereinafter referred to as “buffer layer”) 12 grown on the sapphire substrate 11, and a concavo-convex surface 13 </ b> S grown on the buffer layer 12. GaN layer 13, AlN intermediate layer (hereinafter referred to as “intermediate layer”) 14 grown on uneven surface 13S of GaN layer 13, and Al X1 Ga Y1 grown on uneven surface 14S of intermediate layer 14 An N-based compound layer 15 and an Al X2 Ga Y2 N-based compound layer 16 grown on the Al X1 Ga Y1 N-based compound layer 15 are provided.

化合物半導体デバイス10の上にAlGaN系化合物からなる複数の半導体層を成長させた半導体構造物は、紫外半導体レーザ素子用の結晶材料として用いられ、発光デバイス、受光デバイス、電子デバイス等のデバイスに応用することが可能である。   A semiconductor structure in which a plurality of semiconductor layers made of an AlGaN compound are grown on the compound semiconductor device 10 is used as a crystal material for an ultraviolet semiconductor laser element, and is applied to devices such as a light emitting device, a light receiving device, and an electronic device. Is possible.

サファイア基板11はサファイアからなり、結晶成長面として(0001)面を有する。   The sapphire substrate 11 is made of sapphire and has a (0001) plane as a crystal growth surface.

バッファー層12はGaNからなり、中間層14はAlNからなる。   The buffer layer 12 is made of GaN, and the intermediate layer 14 is made of AlN.

また、GaN層13は、バッファー層12上に成長させてあり、凹凸表面13Sを有し、これにより複数の凸部13A及び凹部13Bを有する。ここで、GaN層13は、周期性を持ったストライプ状のラインアンドスペースを有するように、ストライプ状に交互に配置された凸部13A及び凹部13Bを有するのが好ましい。   The GaN layer 13 is grown on the buffer layer 12 and has a concavo-convex surface 13S, thereby having a plurality of convex portions 13A and concave portions 13B. Here, the GaN layer 13 preferably has convex portions 13A and concave portions 13B arranged alternately in a stripe shape so as to have a stripe-like line and space with periodicity.

さらに、中間層14及びAlX1GaY1N系化合物層15は、それぞれGaN層13の凹凸表面13S及び中間層14の凹凸表面14S上に成長させてある。さらに、AlX2GaY2N系化合物層16は、周期性を持ったストライプ状構造を埋め込んで平坦化するようにAlX1GaY1N系化合物層15上に成長させてある。 Furthermore, the intermediate layer 14 and the Al X1 Ga Y1 N-based compound layer 15 are grown on the uneven surface 13S of the GaN layer 13 and the uneven surface 14S of the intermediate layer 14, respectively. Further, the Al X2 Ga Y2 N-based compound layer 16 is grown on the Al X1 Ga Y1 N-based compound layer 15 so as to be buried and planarized with a periodic stripe structure.

AlX1GaY1N系化合物層15の材料は、AlX1GaY1N(0≦X1≦1、0≦Y1≦1、0<X1+Y1≦1)で表される2〜3元系の化合物を含む化合物半導体の中から選ばれる。このため、AlX1GaY1N系化合物層15の材料は、その他の元素を含んでいてもよく、例えばAlX1GaY1InZ1N(Z1=1−X1−Y1)化合物半導体でもよく、AlX1GaY1Nからなる半導体でもよい。 The material of the Al X1 Ga Y1 N-based compound layer 15 includes a two-ternary compound represented by Al X1 Ga Y1 N (0 ≦ X1 ≦ 1, 0 ≦ Y1 ≦ 1, 0 <X1 + Y1 ≦ 1). Selected from compound semiconductors. For this reason, the material of the Al X1 Ga Y1 N-based compound layer 15 may contain other elements, for example, an Al X1 Ga Y1 In Z1 N (Z1 = 1-X1-Y1) compound semiconductor, or an Al X1 A semiconductor made of Ga Y1 N may be used.

また、AlX2GaY2N系化合物層16の材料は、AlX2GaY2N(0≦X2≦1、0≦Y2≦1、0<X2+Y2≦1)で表される2〜3元系の化合物を含む化合物半導体の中から選ばれ、例えばAlX2GaY2InZ2N(Z2=1−X2−Y2)化合物半導体でもよく、AlX2GaY2Nからなる半導体でもよい。なおX2は、X1>X2なる関係式を満たし、これによりAlX2GaY2N系化合物層16におけるクラックの発生が低減される(クラックの発生が低減される理由は後述する)。 The material of the Al X2 Ga Y2 N-based compound layer 16 is a two-ternary compound represented by Al X2 Ga Y2 N (0 ≦ X2 ≦ 1, 0 ≦ Y2 ≦ 1, 0 <X2 + Y2 ≦ 1). For example, it may be an Al X2 Ga Y2 In Z2 N (Z2 = 1-X2-Y2) compound semiconductor or a semiconductor composed of Al X2 Ga Y2 N. X2 satisfies the relational expression of X1> X2, thereby reducing the occurrence of cracks in the Al X2 Ga Y2 N-based compound layer 16 (the reason why the occurrence of cracks is reduced will be described later).

これにより、AlX1GaY1N系化合物層15及びAlX2GaY2N系化合物層16が3元混晶の場合は、Y1及びY2は、それぞれ1−X1及び1−X2である。また、AlX1GaY1N系化合物層及びAlX2GaY2N系化合物層が4元混晶の場合は、Y1及びY2は、それぞれX1との和及びX2との和が1より小さくなる。 Thus, when the Al X1 Ga Y1 N-based compound layer 15 and the Al X2 Ga Y2 N-based compound layer 16 are ternary mixed crystals, Y1 and Y2 are 1-X1 and 1-X2, respectively. When the Al X1 Ga Y1 N-based compound layer and the Al X2 Ga Y2 N-based compound layer are quaternary mixed crystals, Y1 and Y2 have a sum of X1 and a sum of X2 smaller than 1, respectively.

次に、AlX2GaY2N系化合物層16のデバイス表面10Sにおけるクラックの発生が低減される理由について、図4を参照して説明する。 Next, the reason why the generation of cracks in the device surface 10S of the Al X2 Ga Y2 N-based compound layer 16 is reduced will be described with reference to FIG.

図4は、クラックの発生が低減される理由を説明する説明図である。   FIG. 4 is an explanatory diagram for explaining the reason why the occurrence of cracks is reduced.

AlX1GaY1N系化合物層15と、AlX2GaY2N系化合物層16との間には、X1>X2なる関係式が成立している。すなわち、AlX2GaY2N系化合物層16の材料は、AlX1GaY1N系化合物層15の材料よりもAlの組成比が小さい。これにより、AlX2GaY2N系化合物層16の材料は、AlX1GaY1N系化合物層15の材料よりも格子定数が大きく、直下の半導体層であるAlX1GaY1N系化合物層15の格子定数に合わせようとするために、圧縮歪を受けることになる。 A relational expression X1> X2 is established between the Al X1 Ga Y1 N-based compound layer 15 and the Al X2 Ga Y2 N-based compound layer 16. That is, the material of the Al X2 Ga Y2 N-based compound layer 16 has a smaller Al composition ratio than the material of the Al X1 Ga Y1 N-based compound layer 15. Thereby, the material of the Al X2 Ga Y2 N-based compound layer 16 has a larger lattice constant than the material of the Al X1 Ga Y1 N-based compound layer 15, and the Al X1 Ga Y1 N-based compound layer 15, which is a semiconductor layer immediately below. In order to match with the lattice constant, compression strain is applied.

一方、AlX2GaY2N系化合物層16は、層の膜厚が厚くなることにより蓄積される引張歪を受けることになる。 On the other hand, the Al X2 Ga Y2 N-based compound layer 16 is subjected to tensile strain accumulated as the layer thickness increases.

この結果、上記の引張歪が圧縮歪により相殺され、AlX2GaY2N系化合物層16のデバイス表面10Sにおけるクラックの発生が低減される。また、AlX2GaY2N系化合物層16の上に成長させる、AlGaN系化合物層を含む複数の半導体層を厚くさせてもクラックの発生が低減される。 As a result, the tensile strain is offset by the compressive strain, and the generation of cracks on the device surface 10S of the Al X2 Ga Y2 N-based compound layer 16 is reduced. Further, even if the plurality of semiconductor layers including the AlGaN-based compound layer grown on the Al X2 Ga Y2 N-based compound layer 16 is made thick, the generation of cracks is reduced.

なお、X1とX2との差は、少なくとも0.45あると好ましい。すなわち、X1−X2≧0.45なる関係式を満たすと好ましい。これは、AlX1GaY1N系化合物層15とAlX2GaY2N系化合物層16との格子不整合率(格子定数の不整合率)が少なくとも1%あれば、AlX1GaY1N系化合物層15が上記の圧縮歪を受け、この1%の格子不整合率は、Al組成の差に換算すれば、X1−X2=0.45に相当するからである。 Note that the difference between X1 and X2 is preferably at least 0.45. That is, it is preferable that the relational expression X1-X2 ≧ 0.45 is satisfied. If the lattice mismatch rate (lattice mismatch rate) between the Al X1 Ga Y1 N-based compound layer 15 and the Al X2 Ga Y2 N-based compound layer 16 is at least 1%, the Al X1 Ga Y1 N-based compound This is because the layer 15 is subjected to the above-described compressive strain, and the lattice mismatch rate of 1% corresponds to X1−X2 = 0.45 in terms of the difference in Al composition.

また、GaN層13は、凹凸表面13Sに複数の凸部13A及び凹部13Bを有することにより、凸部13Aより上に成長したAlX2GaY2N系化合物層16の欠陥領域92に、転位等の多数の欠陥が残存する。これは、欠陥領域92における、AlX1GaY1N系化合物層15とAlX2GaY2N系化合物層16との界面90における格子不整合などが原因である。 In addition, the GaN layer 13 has a plurality of convex portions 13A and concave portions 13B on the concave and convex surface 13S, so that the defect region 92 of the Al X2 Ga Y2 N-based compound layer 16 grown above the convex portions 13A has dislocations and the like. Many defects remain. This is caused by a lattice mismatch at the interface 90 between the Al X1 Ga Y1 N-based compound layer 15 and the Al X2 Ga Y2 N-based compound layer 16 in the defect region 92.

一方、凹部13Bより上に成長したAlX2GaY2N系化合物層16の低欠陥領域94では、横方向への埋め込み成長が起こり、この横方向の埋め込み成長の過程において転位等の欠陥が横方向に曲げられるため、欠陥密度を低減させることができる。 On the other hand, in the low defect region 94 of the Al X2 Ga Y2 N-based compound layer 16 grown above the recess 13B, lateral growth occurs, and defects such as dislocations occur in the lateral direction in the lateral growth process. Therefore, the defect density can be reduced.

ここで、複数の凸部13A及び凹部13Bは、ストライプ状に交互に配置されていることも好ましく、周期的なストライプ状のラインアンドスペースを有するように交互に配置されているのがより好ましい。これにより欠陥が、AlX2GaY2N系化合物層16内の複数の欠陥領域92に略均一に偏り無く分散して存在し、欠陥領域92と低欠陥領域94とが交互に配置されることになるので、欠陥の密度がさらに低減される。 Here, the plurality of convex portions 13A and concave portions 13B are also preferably arranged alternately in a stripe shape, and more preferably arranged alternately so as to have a periodic stripe-like line and space. As a result, defects are present in the plurality of defect regions 92 in the Al X2 Ga Y2 N-based compound layer 16 in a substantially uniform and non-uniform manner, and the defect regions 92 and the low defect regions 94 are alternately arranged. As a result, the density of defects is further reduced.

なお、上述のそれぞれの実施形態において、上述の歪の相殺によるクラックの抑制の観点から、各層の好適な厚みの範囲は、以下のように設定することが好ましい。
GaN層13の厚みの範囲:0.5〜500μm
AlN層14の厚みの範囲:5〜100nm
AlGaN層15の厚みの範囲:5〜1000nm
AlGaN層16の厚みの範囲:0.1〜20μm
In each of the above-described embodiments, it is preferable to set the preferred thickness range of each layer as follows from the viewpoint of suppressing cracks by canceling out the above-described strain.
GaN layer 13 thickness range: 0.5 to 500 μm
The thickness range of the AlN layer 14: 5 to 100 nm
The thickness range of the AlGaN layer 15: 5 to 1000 nm
The thickness range of the AlGaN layer 16: 0.1 to 20 μm

次に、化合物半導体デバイス10、及びこの上にAlGaN系化合物からなる複数の半導体層を成長させた半導体構造物30の製造方法について、図5を参照して説明する。下記工程(1)〜(5)を順次実施することで、化合物半導体デバイス10及び半導体構造物30を製造することができる。   Next, a method of manufacturing the compound semiconductor device 10 and the semiconductor structure 30 in which a plurality of semiconductor layers made of an AlGaN compound are grown thereon will be described with reference to FIG. The compound semiconductor device 10 and the semiconductor structure 30 can be manufactured by sequentially performing the following steps (1) to (5).

図5は、本実施形態に係る半導体構造物30の断面図である。   FIG. 5 is a cross-sectional view of the semiconductor structure 30 according to the present embodiment.

なお、本実施形態では、結晶を成長させる方法として有機金属気相成長(MOCVD)法が用いられるが、本発明はこれに限定されず、分子線成長(MBE)法、ハイドライド気相成長(HVPE)法等、他の成長方法を用いてもよい。   In this embodiment, a metal organic chemical vapor deposition (MOCVD) method is used as a method for growing a crystal. However, the present invention is not limited to this, and a molecular beam growth (MBE) method, a hydride vapor phase epitaxy (HVPE). ) Method or other growth methods may be used.

また、本実施形態では、窒素原料ガスとしてアンモニア(NH)を含むガスが、III族原料ガスとしてトリメチルガリウム(TMG)やトリメチルアルミニウム(TMA)を含むガスが、n型ドーピング原料ガスとしてシラン(SiH)を含むガスが、p型ドーピング原料ガスとしてビスシクロペンタジエニルマグネシウム(CpMg)を含むガスが用いられるが、本発明はこれに限定されない。 In this embodiment, the gas containing ammonia (NH 3 ) as the nitrogen source gas, the gas containing trimethylgallium (TMG) or trimethylaluminum (TMA) as the group III source gas, and silane ( The gas containing SiH 4 ) includes a gas containing biscyclopentadienyl magnesium (Cp 2 Mg) as a p-type doping source gas, but the present invention is not limited to this.

また、本実施形態では、AlX1GaY1N系化合物層15はAlX1GaY1Nからなり、AlX2GaY2N系化合物層16はAlX2GaY2Nからなるとしたが、それぞれAlX1GaY1InZ1NとAlX2GaY2InZ2Nとからなるとしてもよい。
工程(1)GaN層成長工程
In the present embodiment, the Al X1 Ga Y1 N-based compound layer 15 is made of Al X1 Ga Y1 N, and the Al X2 Ga Y2 N-based compound layer 16 is made of Al X2 Ga Y2 N, but each of them is Al X1 Ga Y1. It may be composed of In Z1 N and Al X2 Ga Y2 In Z2 N.
Process (1) GaN layer growth process

サファイア基板11を、MOCVDによる結晶成長を行うことが可能な空間(MOCVD室)に導入して固定し、MOCVD室内を水素雰囲気にする。次に、サファイア基板11に対して1050℃で5分間の熱処理を行い、サファイア基板11の表面を清浄化する。このように適切な条件で熱処理を行うことで、サファイア基板11の表面の汚染物質が取り除かれると共に、表面の平面度が向上する。   The sapphire substrate 11 is introduced and fixed in a space (MOCVD chamber) where crystal growth by MOCVD can be performed, and the MOCVD chamber is made a hydrogen atmosphere. Next, heat treatment is performed on the sapphire substrate 11 at 1050 ° C. for 5 minutes to clean the surface of the sapphire substrate 11. By performing the heat treatment under appropriate conditions in this manner, contaminants on the surface of the sapphire substrate 11 are removed and the flatness of the surface is improved.

次に、サファイア基板11の温度を475℃まで降温し、トリメチルガリウムを含むIII族原料ガス、及び窒素原料ガス等を供給して、サファイア基板11上に膜厚が25nmのバッファー層12を成長させる。そして、1075℃まで昇温し、トリメチルガリウムを含むIII族原料ガス、及び窒素原料ガス等を供給して、バッファー層12上に膜厚がバッファー層12より厚い2.5μmのGaN層13を成長させる。
工程(2)凹凸加工工程
Next, the temperature of the sapphire substrate 11 is lowered to 475 ° C., and a group III source gas containing trimethylgallium and a nitrogen source gas are supplied to grow a buffer layer 12 having a film thickness of 25 nm on the sapphire substrate 11. . Then, the temperature is raised to 1075 ° C., a group III source gas containing trimethylgallium, a nitrogen source gas, and the like are supplied to grow a 2.5 μm thick GaN layer 13 on the buffer layer 12. Let
Process (2) Concavity and convexity processing process

工程(1)で得られた基板をMOCVD室から取り出し、プラズマCVDによる成膜が可能な空間(プラズマCVD室)に導入して固定する。次に、上記の基板上に、膜厚が300nmのSiO膜を堆積させる。 The substrate obtained in the step (1) is taken out from the MOCVD chamber, and introduced into a space (plasma CVD chamber) in which film formation by plasma CVD is possible and fixed. Next, a 300 nm thick SiO 2 film is deposited on the substrate.

次に、通常のフォトリソグラフィー技術によりSiO膜を加工して、凹部13Bを構成する溝の長さ及び深さの双方に垂直な方向を幅とすると、凹部13Bの幅T2及び凸部13Aの幅T1が14μmである、周期ストライプ状でありラインアンドスペースを有するフォトレジストパターンを形成する。なお、幅T1=5〜25μm、幅T2=5〜25μmである場合には、上述のように欠陥を偏在させることができる。また、ストライプの方向は、GaN[1−100]方向である。 Next, when the SiO 2 film is processed by a normal photolithography technique and the width is in the direction perpendicular to both the length and depth of the groove constituting the recess 13B, the width T2 of the recess 13B and the protrusion 13A A photoresist pattern having a line-and-space pattern with a width T1 of 14 μm and a periodic stripe shape is formed. When the width T1 = 5 to 25 μm and the width T2 = 5 to 25 μm, defects can be unevenly distributed as described above. The stripe direction is the GaN [1-100] direction.

次に、周期ストライプ状に形成したSiO膜をマスクとして、平行平板型の反応性イオンエッチング(RIE)を用いて、GaN層13を2μmエッチングする。上記のエッチングには、20SCCM(立方センチメートル毎分)の塩素(Cl)ガスと、5SCCMの四塩化ケイ素(SiCl)ガスとを用い、リアクタ圧力を30mTorr、RFパワーを280Wとすることにより、0.2μm/min程度のエッチング速度が得られる。 Next, the GaN layer 13 is etched by 2 μm using parallel plate type reactive ion etching (RIE) using the SiO 2 film formed in a periodic stripe shape as a mask. In the etching described above, 20 SCCM (cubic centimeter per minute) chlorine (Cl 2 ) gas and 5 SCCM silicon tetrachloride (SiCl 4 ) gas are used, the reactor pressure is set to 30 mTorr, and the RF power is set to 280 W. An etching rate of about 2 μm / min can be obtained.

次に、上記のエッチング後、バッファードフッ酸(BHF)、フッ酸(HF)、あるいはCFガスを用いてSiOをエッチングすることにより、SiOを除去する。これにより、GaN層13は、凹凸表面13Sを有することとなる。次に、凹凸加工した基板を、再度、MOCVD成長室に導入して固定し、MOCVD室をアンモニア雰囲気にして、1075℃で5分間の熱処理を行う。 Next, after the above etching, the SiO 2 is removed by etching the SiO 2 using buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), or CF 4 gas. Thereby, the GaN layer 13 has the uneven surface 13S. Next, the processed substrate is again introduced into the MOCVD growth chamber and fixed, and the MOCVD chamber is placed in an ammonia atmosphere and heat treatment is performed at 1075 ° C. for 5 minutes.

本実施形態では、GaN層13のエッチングについては、RIEを用いたが、これに限定されず、例えば、反応性イオンビームエッチング(RIBE)、ECR−RIE、ICP−RIE等のエッチング方法を用いてもよい。また、エッチングに用いるガスには塩素ガス、四塩化ケイ素ガスを用いたが、これに限定されず、三塩化ボロン等の塩素系ガス、メタンガス等を用いてもよい。
工程(3)中間層成長工程
In the present embodiment, RIE is used for etching the GaN layer 13, but the GaN layer 13 is not limited to this. For example, an etching method such as reactive ion beam etching (RIBE), ECR-RIE, or ICP-RIE is used. Also good. Moreover, although chlorine gas and silicon tetrachloride gas were used for the gas used for etching, it is not limited to this, Chlorine gas, such as boron trichloride, methane gas, etc. may be used.
Process (3) Intermediate layer growth process

前工程で得られた基板の温度を550℃まで降温し、GaN層13の表面上に膜厚が10nmの中間層14を成長させる。
工程(4)化合物層成長工程
The temperature of the substrate obtained in the previous step is lowered to 550 ° C., and an intermediate layer 14 having a thickness of 10 nm is grown on the surface of the GaN layer 13.
Step (4) Compound layer growth step

工程(3)で得られた基板を1125℃まで昇温し、中間層14の凹凸表面14S上に膜厚が約500nmのAl0.6Ga0.4N層(AlX1GaY1N系化合物層15)を成長させる。次に、膜厚が6μmのAl0.15Ga0.85N層(AlX2GaY2N系化合物層16)を成長させる。これにより、周期ストライプ状構造が埋め込まれ、基板の表面が平坦化されて、化合物半導体デバイス10が得られる。なお、これらの膜厚は、平坦な基板上に成長させた場合の膜厚に換算した値である。
工程(5)半導体構造物30製造工程
The substrate obtained in step (3) is heated to 1125 ° C., and an Al 0.6 Ga 0.4 N layer (Al X1 Ga Y1 N-based compound having a film thickness of about 500 nm is formed on the uneven surface 14S of the intermediate layer 14. Layer 15) is grown. Next, an Al 0.15 Ga 0.85 N layer (Al X2 Ga Y2 N-based compound layer 16) having a thickness of 6 μm is grown. Thereby, the periodic stripe structure is embedded, the surface of the substrate is flattened, and the compound semiconductor device 10 is obtained. These film thicknesses are values converted into film thicknesses when grown on a flat substrate.
Process (5) Semiconductor structure 30 manufacturing process

前工程で得られた基板の上に、SiをドープしたAl0.15Ga0.85N層(Siドープクラッド層17)を3μm、Al0.07Ga0.93N層(第1ガイド層18)を100nm、AlGaN量子井戸構造19、Al0.07Ga0.93N層(第2ガイド層20)を100nm、Al0.35Ga0.65N層(ブロック層21)を20nm、MgをドープしたAl0.15Ga0.85N層(Mgドープクラッド層22)を0.6μm、MgをドープしたGaN層(コンタクト層23)を50nm、順に成長させて、半導体構造物30を得た。 On the substrate obtained in the previous step, a Si-doped Al 0.15 Ga 0.85 N layer (Si-doped cladding layer 17) is 3 μm and an Al 0.07 Ga 0.93 N layer (first guide layer). 18) 100 nm, AlGaN quantum well structure 19, Al 0.07 Ga 0.93 N layer (second guide layer 20) 100 nm, Al 0.35 Ga 0.65 N layer (block layer 21) 20 nm, Mg A 0.15 Ga 0.85 N layer (Mg-doped cladding layer 22) doped with Mg and a GaN layer (contact layer 23) doped with Mg are grown in order of 50 nm to obtain a semiconductor structure 30. It was.

また、化合物半導体デバイス10及び半導体構造物30の製造方法は、上述の工程(1)及び(3)を経た後に、以下の工程(4−2)及び上述の工程(5)を経ることも好ましい。これにより、図6に示すように、凹凸表面を有しないGaN層13を備えた、化合物半導体デバイス10及び半導体構造物30が得られる。   Moreover, it is also preferable that the manufacturing method of the compound semiconductor device 10 and the semiconductor structure 30 passes the following process (4-2) and the above-mentioned process (5) after passing through the above-mentioned processes (1) and (3). . Thereby, as shown in FIG. 6, the compound semiconductor device 10 and the semiconductor structure 30 provided with the GaN layer 13 having no uneven surface are obtained.

図6は、半導体構造物の別の実施形態の断面図である。
工程(4−2)化合物層成長工程の別の実施形態
FIG. 6 is a cross-sectional view of another embodiment of a semiconductor structure.
Step (4-2) Another Embodiment of Compound Layer Growth Step

工程(3)で得られた基板を1125℃まで昇温し、膜厚が約250nmのAl0.6Ga0.4N層(AlX1GaY1N系化合物層15)を成長させた後、Siをドープ(添加)した膜厚が3μmのAl0.15Ga0.85N層(AlX2GaY2N系化合物層16)を成長させることにより、凹凸表面13Sを有しない化合物半導体デバイス10が得られる。ここで、Siの添加量は1×1018cm−3である。 The substrate obtained in step (3) was heated to 1125 ° C., and an Al 0.6 Ga 0.4 N layer (Al X1 Ga Y1 N-based compound layer 15) having a film thickness of about 250 nm was grown. By growing an Al 0.15 Ga 0.85 N layer (Al X2 Ga Y2 N-based compound layer 16) having a film thickness of 3 μm doped with Si, the compound semiconductor device 10 having no uneven surface 13S is obtained. can get. Here, the addition amount of Si is 1 × 10 18 cm −3 .

なお、III族原料ガスであるトリメチルアルミニウムを含むガスと、窒素原料ガスであるアンモニアを含むガスとは気相中で反応することが知られており、この反応を抑制するために、上記のAlGaN系化合物からなる半導体層15〜22の成長は、減圧下で行うことが好ましく、本実施形態では76Torrで行った。   It is known that a gas containing trimethylaluminum, which is a group III source gas, and a gas containing ammonia, which is a nitrogen source gas, react in the gas phase. In order to suppress this reaction, the above AlGaN is used. The growth of the semiconductor layers 15 to 22 made of a system compound is preferably performed under reduced pressure, and is performed at 76 Torr in the present embodiment.

次に、AlX1GaY1N系化合物層15及びAlX2GaY2N系化合物層16として、それぞれAl0.6Ga0.4N及びAl0.15Ga0.85Nを用いて得られた化合物半導体デバイス10の表面の写真について説明する。 Next, the Al X1 Ga Y1 N-based compound layer 15 and the Al X2 Ga Y2 N-based compound layer 16 were obtained using Al 0.6 Ga 0.4 N and Al 0.15 Ga 0.85 N, respectively. A photograph of the surface of the compound semiconductor device 10 will be described.

図7は、工程(1)〜(5)を経て得られた半導体構造物30の構造物表面30Sの写真である。   FIG. 7 is a photograph of the structure surface 30S of the semiconductor structure 30 obtained through the steps (1) to (5).

また、図8は、工程(4)におけるAlX1GaY1N系化合物層15の成長に関して膜厚を約250nmとして工程(1)〜(5)を経て得られた半導体構造物30の構造物表面30Sの写真である。 8 shows the structure surface of the semiconductor structure 30 obtained through steps (1) to (5) with the film thickness being about 250 nm with respect to the growth of the Al X1 Ga Y1 N-based compound layer 15 in step (4). It is a photograph of 30S.

さらに、図9は、背景技術である非特許文献1〜6に示されているように、AlX1GaY1N系化合物層15を成長させずに製造した半導体構造物30の構造物表面30Sの写真である。 Further, FIG. 9, as shown in Non-Patent Documents 1 to 6 which is in the background, Al X1 Ga Y1 N-based compound layer 15 semiconductor structure 30 produced without growing the structure surface 30S It is a photograph.

図10は、工程(1)、(3)、及び(4−2)を経て得られた、GaN層13が凹凸表面を有しない化合物半導体デバイス10のデバイス表面10Sの写真である。   FIG. 10 is a photograph of the device surface 10S of the compound semiconductor device 10 in which the GaN layer 13 does not have an uneven surface, obtained through the steps (1), (3), and (4-2).

また、図11は、AlX1GaY1N系化合物層15を有さず、GaN層13が凹凸表面を有しない化合物半導体デバイス10のデバイス表面10Sの写真である。 FIG. 11 is a photograph of the device surface 10S of the compound semiconductor device 10 that does not have the Al X1 Ga Y1 N-based compound layer 15 and the GaN layer 13 does not have an uneven surface.

工程(1)〜(5)を経て半導体構造物30を得た場合、図7に示すように、構造物表面30Sにクラックは観察されなかった。なお、写真中の横縞は、工程(2)において加工した周期ストライプ状のGaN層13に起因したもので、クラックではない。   When the semiconductor structure 30 was obtained through the steps (1) to (5), no crack was observed on the structure surface 30S as shown in FIG. In addition, the horizontal stripe in a photograph originates in the periodic stripe-shaped GaN layer 13 processed in process (2), and is not a crack.

また、工程(4)において成長させたAlX1GaY1N系化合物層15を約250nm成長させて半導体構造物30を得た場合も、図8に示すように、構造物表面30Sにクラックは観察されなかった。 Also, when the semiconductor structure 30 is obtained by growing the Al X1 Ga Y1 N-based compound layer 15 grown in the step (4) by about 250 nm, cracks are observed on the structure surface 30S as shown in FIG. Was not.

一方、AlX1GaY1N系化合物層15を成長させずに製造した半導体構造物30は、図9に示すように、構造物表面30Sにクラック(白矢印で示される写真中の2本の縦縞)が高密度に観察された。 On the other hand, the semiconductor structure 30 manufactured without growing the Al X1 Ga Y1 N-based compound layer 15 has cracks (two vertical stripes in the photograph indicated by white arrows) on the structure surface 30S, as shown in FIG. ) Was observed at high density.

工程(1)、(3)、及び(4−2)を経て得られた、GaN層13が凹凸表面を有しない化合物半導体デバイス10のデバイス表面10Sには、図10に示すように、クラックは観察されなかった。   As shown in FIG. 10, cracks are present on the device surface 10 </ b> S of the compound semiconductor device 10 in which the GaN layer 13 does not have an uneven surface obtained through the steps (1), (3), and (4-2). Not observed.

また、AlX1GaY1N系化合物層15を有さず、GaN層13が凹凸表面を有しない化合物半導体デバイス10のデバイス表面10Sには、図11に示すように、クラックが観察された。 Further, as shown in FIG. 11, cracks were observed on the device surface 10S of the compound semiconductor device 10 that does not have the Al X1 Ga Y1 N-based compound layer 15 and the GaN layer 13 does not have an uneven surface.

次に、本実施形態に係る化合物半導体デバイス10の作用及び効果について説明する。   Next, functions and effects of the compound semiconductor device 10 according to the present embodiment will be described.

化合物半導体デバイス10がAlX1GaY1N系化合物層15を備えず、中間層14の上にAlX2GaY2N系化合物層16を膜厚が厚くなるように成長させる場合、ある膜厚(臨界膜厚)より厚くなるとクラックが発生する。 When the compound semiconductor device 10 does not include the Al X1 Ga Y1 N-based compound layer 15 and the Al X2 Ga Y2 N-based compound layer 16 is grown on the intermediate layer 14 so as to increase the thickness, a certain thickness (critical) Cracks occur when the film thickness is greater.

一方、化合物半導体デバイス10がAlX1GaY1N系化合物層15を備える場合、AlX2GaY2N系化合物層16は、AlX1GaY1N系化合物層15より格子定数が大きいために圧縮歪を受ける。ここで、AlX2GaY2N系化合物層16の膜厚増加とともに蓄積される引張歪が、この圧縮歪により相殺されて、デバイス表面10Sのクラックの発生が抑制される。また、化合物半導体デバイス10の上にAlGaN系化合物層を含む複数の半導体層を厚く成長させてもクラックの発生が低減される。 On the other hand, when the compound semiconductor device 10 includes the Al X1 Ga Y1 N-based compound layer 15, the Al X2 Ga Y2 N-based compound layer 16 has a lattice constant larger than that of the Al X1 Ga Y1 N-based compound layer 15, and thus compressive strain is generated. receive. Here, the tensile strain accumulated with the increase in the film thickness of the Al X2 Ga Y2 N-based compound layer 16 is offset by this compressive strain, and the occurrence of cracks on the device surface 10S is suppressed. Further, even if a plurality of semiconductor layers including an AlGaN-based compound layer are grown thick on the compound semiconductor device 10, the generation of cracks is reduced.

さらに、GaN層13が凹凸表面を有する場合、凹部13Bより上に成長したAlX2GaY2N系化合物層16では横方向成長が起こり、これにより欠陥が横方向に曲げられるため、低欠陥領域94が形成される。 Further, when the GaN layer 13 has a concavo-convex surface, the Al X2 Ga Y2 N-based compound layer 16 grown above the recess 13B grows in the lateral direction, which causes the defects to be bent in the lateral direction. Is formed.

図12は、別の実施形態に係る半導体デバイス10の断面図である。   FIG. 12 is a cross-sectional view of a semiconductor device 10 according to another embodiment.

この化合物半導体デバイス10は、図3に示したものと比較してサファイア基板11及びバッファ層12を備えていない点でのみ異なる。なお、GaN層13は自重を単独で保持できる強度の厚みを有するGaN基板である。すなわち、化合物半導体デバイス10のGaN層13はGaN基板13とすることもできる。市販のGaN基板13を準備して用いる場合、上述のサファイア基板が不要となるため、格子不整合が生じず、各層の結晶性の劣化を抑制することができる。また、GaN基板13を用いる場合、上述のGaN層の形成工程(1)は不要となる。なお、GaN基板13上にエピタキシャル成長するGaN層13を新たに形成し、全体をGaN基板としてもよい。   This compound semiconductor device 10 differs from that shown in FIG. 3 only in that it does not include the sapphire substrate 11 and the buffer layer 12. The GaN layer 13 is a GaN substrate having a thickness capable of holding its own weight alone. That is, the GaN layer 13 of the compound semiconductor device 10 can be the GaN substrate 13. When the commercially available GaN substrate 13 is prepared and used, the above-described sapphire substrate is not necessary, so that lattice mismatch does not occur and deterioration of crystallinity of each layer can be suppressed. Further, when the GaN substrate 13 is used, the above-described GaN layer forming step (1) becomes unnecessary. A GaN layer 13 that is epitaxially grown on the GaN substrate 13 may be newly formed, and the whole may be a GaN substrate.

なお、GaN基板13の厚みは、50μm〜500μmである。   The GaN substrate 13 has a thickness of 50 μm to 500 μm.

図13は、更に別の実施形態に係る半導体デバイス10の断面図である。   FIG. 13 is a cross-sectional view of a semiconductor device 10 according to yet another embodiment.

この化合物半導体デバイス10は、図3に示したものと比較して、AlN層14がサファイア基板11に接触する深さまでGaN層13の凹部13Bがエッチングされている点のみで異なる。サファイア基板11上のAlN層14は、GaNバッファ層12の側方に位置する。GaN層13の凹凸面における凹部13Bは、GaN層13の側壁とサファイア基板11の表面で構成される。   This compound semiconductor device 10 differs from that shown in FIG. 3 only in that the recess 13B of the GaN layer 13 is etched to a depth at which the AlN layer 14 contacts the sapphire substrate 11. The AlN layer 14 on the sapphire substrate 11 is located on the side of the GaN buffer layer 12. The concave portion 13 </ b> B on the concave and convex surface of the GaN layer 13 is constituted by the side wall of the GaN layer 13 and the surface of the sapphire substrate 11.

本例の場合、凹部13BにおけるAlN層14は、GaN層上ではなく、サファイア基板11上に成長することとなる。この場合、サファイアとAlGaN層との格子不整合を緩和する効果を奏する。   In the case of this example, the AlN layer 14 in the recess 13B grows on the sapphire substrate 11, not on the GaN layer. In this case, the effect of relaxing the lattice mismatch between the sapphire and the AlGaN layer is achieved.

以上のように、本発明によれば、AlN中間層14とAlGaN系化合物層16との間に、AlGaN系化合物層15を成長させており、引張歪と圧縮歪の相殺により、クラックの発生を抑制することができる。   As described above, according to the present invention, the AlGaN compound layer 15 is grown between the AlN intermediate layer 14 and the AlGaN compound layer 16, and cracks are generated by canceling out the tensile strain and the compressive strain. Can be suppressed.

GaN層上にAlGaN層を成長させたデバイスの断面図である。It is sectional drawing of the device which grew the AlGaN layer on the GaN layer. GaN層上にAlN中間層を成長させ、その上にAlGaN層を成長させたデバイスの断面図である。It is sectional drawing of the device which made the AlN intermediate layer grow on the GaN layer, and made the AlGaN layer grow on it. 本実施形態に係る化合物半導体デバイスの断面図である。It is sectional drawing of the compound semiconductor device which concerns on this embodiment. クラックの発生が低減される理由を説明する説明図である。It is explanatory drawing explaining the reason that generation | occurrence | production of a crack is reduced. 半導体構造物の断面図である。It is sectional drawing of a semiconductor structure. 半導体構造物の別の実施形態の断面図である。FIG. 6 is a cross-sectional view of another embodiment of a semiconductor structure. 工程(1)〜(5)を経て得られた半導体構造物の構造物表面の写真である。It is a photograph of the structure surface of the semiconductor structure obtained through steps (1) to (5). 工程(4)においてAlX1GaY1N系化合物層の膜厚を約250nmとして工程(1)〜(5)を経て得られた半導体構造物の構造物表面の写真である。It is a photograph of the structure surface of the semiconductor structure obtained through steps (1) to (5) with the film thickness of the Al X1 Ga Y1 N-based compound layer being about 250 nm in step (4). AlX1GaY1N系化合物層を成長させずに製造した半導体構造物の構造物表面の写真である。Al X1 Ga Y1 N-based compound layer semiconductor structure manufactured without growth is a photograph of the structure surface. GaN層が凹凸表面を有しない化合物半導体デバイスのデバイス表面の写真である。It is a photograph of the device surface of the compound semiconductor device in which a GaN layer does not have an uneven surface. AlX1GaY1N系化合物層を有さず、GaN層が凹凸表面を有しない化合物半導体デバイスのデバイス表面の写真である。Has no Al X1 Ga Y1 N-based compound layer, GaN layer is a photograph of the device surface of the compound semiconductor device having no uneven surface. 別の実施形態に係る半導体デバイス10の断面図である。It is sectional drawing of the semiconductor device 10 which concerns on another embodiment. 更に別の実施形態に係る半導体デバイス10の断面図である。It is sectional drawing of the semiconductor device 10 which concerns on another embodiment.

符号の説明Explanation of symbols

10…化合物半導体デバイス、10S…デバイス表面、11…サファイア基板、12…バッファー層、13…GaN層、13A…凸部、13B…凹部、13S…GaN層の凹凸表面、14…中間層、14S…中間層の凹凸表面、15…AlX1GaY1N系化合物層、16…AlX2GaY2N系化合物層、17…Siドープクラッド層、18…第1ガイド層、19…AlGaN量子井戸構造、20…第2ガイド層、21…ブロック層、22…Mgドープクラッド層、23…コンタクト層、30…半導体構造物、30S…構造物表面、90…界面、92…欠陥領域、94…低欠陥領域。 DESCRIPTION OF SYMBOLS 10 ... Compound semiconductor device, 10S ... Device surface, 11 ... Sapphire substrate, 12 ... Buffer layer, 13 ... GaN layer, 13A ... Convex part, 13B ... Concave part, 13S ... Concave surface of GaN layer, 14 ... Intermediate layer, 14S ... irregular surface of the intermediate layer, 15 ... Al X1 Ga Y1 N-based compound layer, 16 ... Al X2 Ga Y2 N-based compound layer, 17 ... Si-doped cladding layer, 18 ... first guide layer, 19 ... AlGaN quantum well structure, 20 2nd guide layer, 21 Block layer, 22 Mg doped cladding layer, 23 Contact layer, 30 Semiconductor structure, 30S Structure surface, 90 Interface, 92 Defect region, 94 Low defect region

Claims (9)

GaN層と、
前記GaN層上に成長させたAlN中間層と、
前記AlN中間層上に成長させたAlX1GaY1N系化合物層と、
前記AlX1GaY1N系化合物層上に成長させ、X1>X2なる関係式を満たすAlX2GaY2N系化合物層と、
を備える、化合物半導体デバイス。
A GaN layer;
An AlN intermediate layer grown on the GaN layer;
An Al X1 Ga Y1 N-based compound layer grown on the AlN intermediate layer;
An Al X2 Ga Y2 N-based compound layer grown on the Al X1 Ga Y1 N-based compound layer and satisfying a relational expression of X1>X2;
A compound semiconductor device comprising:
サファイア基板と、
前記サファイア基板上に成長され、前記GaN層がその上に成長したGaNバッファー層と、
を更に備える、請求項1に記載の化合物半導体デバイス。
A sapphire substrate,
A GaN buffer layer grown on the sapphire substrate and having the GaN layer grown thereon;
The compound semiconductor device according to claim 1, further comprising:
前記GaN層はGaN基板である、請求項1に記載の化合物半導体デバイス。   The compound semiconductor device according to claim 1, wherein the GaN layer is a GaN substrate. 前記GaN層は、凹凸表面を有し、
前記AlN中間層は、前記GaN層の前記凹凸表面上に成長し、
前記AlX1GaY1N系化合物層は、前記AlN中間層の凹凸表面上に成長した、
ことを特徴とする、請求項1に記載の化合物半導体デバイス。
The GaN layer has an uneven surface,
The AlN intermediate layer grows on the uneven surface of the GaN layer,
The Al X1 Ga Y1 N-based compound layer has grown on the uneven surface of the AlN intermediate layer,
The compound semiconductor device according to claim 1, wherein:
前記GaN層の前記凹凸表面の凹凸は、ストライプ状に交互に配置されていることを特徴とする、請求項4に記載の化合物半導体デバイス。   5. The compound semiconductor device according to claim 4, wherein the irregularities on the irregular surface of the GaN layer are alternately arranged in a stripe shape. 前記AlX1GaY1N系化合物層は、AlX1GaY1Nからなり、
前記AlX2GaY2N系化合物層は、X1>X2なる関係式を満たすAlX2GaY2Nからなる、
ことを特徴とする、請求項1〜5の何れかに記載の化合物半導体デバイス。
The Al X1 Ga Y1 N-based compound layer is made of Al X1 Ga Y1 N,
The Al X2 Ga Y2 N-based compound layer is made of Al X2 Ga Y2 N satisfying a relational expression of X1> X2.
The compound semiconductor device according to claim 1, wherein the compound semiconductor device is a device.
GaN層を、凹凸表面を有するように加工する凹凸加工工程と、
当該加工したGaN層の前記凹凸表面上にAlN中間層を成長させる中間層成長工程と、
前記AlN中間層の凹凸表面上にAlX1GaY1N系化合物層を成長させて、前記AlX1GaY1N系化合物層上にX1>X2なる関係式を満たすAlX2GaY2N系化合物層を成長させる化合物層成長工程と、
を含むことを特徴とする化合物半導体デバイスの製造方法。
A concavo-convex processing step for processing the GaN layer to have a concavo-convex surface;
An intermediate layer growth step of growing an AlN intermediate layer on the irregular surface of the processed GaN layer;
An Al X1 Ga Y1 N-based compound layer is grown on the uneven surface of the AlN intermediate layer, and an Al X2 Ga Y2 N-based compound layer satisfying the relational expression X1> X2 is formed on the Al X1 Ga Y1 N-based compound layer. A compound layer growth step to grow,
The manufacturing method of the compound semiconductor device characterized by the above-mentioned.
サファイア基板上にGaNバッファー層を成長させ、前記GaNバッファー層上に前記GaNバッファー層より厚い前記GaN層を成長させるGaN層成長工程を更に備えることを特徴とする請求項7に記載の化合物半導体デバイスの製造方法。   8. The compound semiconductor device according to claim 7, further comprising a GaN layer growth step of growing a GaN buffer layer on the sapphire substrate and growing the GaN layer thicker than the GaN buffer layer on the GaN buffer layer. Manufacturing method. GaN基板を前記GaN層とするGaN基板準備工程を更に備えることを特徴とする請求項7に記載の化合物半導体デバイスの製造方法。   The method of manufacturing a compound semiconductor device according to claim 7, further comprising a GaN substrate preparation step using a GaN substrate as the GaN layer.
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