JP2006080402A - Method for manufacturing printed-wiring board having embedded capacitor circuit and printed-wiring board obtained by the method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for manufacturing a printed-wiring board excellent in an uniformity in film thickness of a dielectric layer and a positional accuracy of a capacitor circuit, which removes as much of an extra dielectric layer as possible, and to provide the printed-wiring board having the embedded capacitor circuit. <P>SOLUTION: The manufacturing method comprises the steps of using the capacitor-layer-forming material having the dielectric layer between a first conductive layer for forming an upper electrode and a second conductive layer for forming a lower electrode, forming a first insulating layer on the outer surface of the second conductive layer of the capacitor-layer-forming material, etching between the upper electrode part of the first conductive layer positioning at the outer layer and the unnecessary part in a thin slit shape, after that, simultaneously exfoliating the dielectric layer of the unnecessary part by exfoliating and removing the unnecesary part of the first conductive layer, and machining the printed-wiring board by leaving only the upper electrode part. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The invention according to the present application relates to a method for manufacturing a printed wiring board having a built-in capacitor circuit, and a printed wiring board obtained by the manufacturing method. In particular, a preferred method for manufacturing a printed wiring board incorporating a capacitor circuit is provided.

  Conventionally, a multilayer printed wiring board with a built-in capacitor circuit (element) uses one or more of the insulating layers located in the inner layer as a dielectric layer, and the inner layer circuit located on both sides of the dielectric layer serves as a capacitor. The upper and lower electrodes have been used in opposition to each other.

  A printed wiring board having such a built-in capacitor is preferably applied to a general printed wiring board manufacturing process, and leads to the manufacturing process shown in FIG. 12 through the processes shown in FIGS. The method has been adopted. That is, as shown in FIG. 12C, in order to form the upper electrode 20 by etching the first conductive layer 3, UV exposure is performed using the exposure pattern film 7 ″, development, etching, and resist. By peeling, a state as shown in FIG. At this time, the dielectric layer is exposed at a portion other than the upper electrode.

  Therefore, using the intermediate product as shown in FIG. 12F, the dielectric layer spreads over the entire surface of the multilayer printed wiring board as well as the capacitor circuit portion even after the subsequent printed wiring board manufacturing process. In addition, a dielectric layer is also present below and around the power supply line and the signal transmission line other than the capacitor circuit. Since this dielectric layer has a high dielectric constant, there has been a problem that dielectric loss increases when a signal signal or the like is transmitted. In addition, there are many cases where it is impossible to embed other circuit elements such as inductors in this dielectric layer, and circuit design is usually subject to certain restrictions.

  Therefore, among those skilled in the art, in order to form a dielectric layer only at a necessary portion, an insulating layer provided on the inner layer substrate surface is subjected to an opening treatment as disclosed in Patent Document 1, and a high dielectric material is formed at that portion. Embedded image or as disclosed in Patent Document 2, a method of transferring a layer with a capacitor circuit previously formed on a resin film onto the surface of the inner core material, as disclosed in Patent Document 3, and a screen printing method For example, a method of printing a paste containing a dielectric filler has been adopted.

JP 09-116247 A JP 2000-323845 A Japanese Patent Laid-Open No. 08-125302

  However, as long as a normal printed wiring board manufacturing process is employed, it is inevitable that the dielectric layer spreads over the entire surface, and it is difficult to leave the dielectric layer only at necessary portions. Further, in the inventions disclosed in Patent Documents 2 to 3, although the state where the dielectric layer remains in the unnecessary portion can be eliminated, the film thickness uniformity of the dielectric layer is lacking, and the positional accuracy during transfer or screen printing is improved. There was a problem.

A capacitor is required as a basic quality to have as much electric capacity as possible. The capacitance (C) of the capacitor is calculated from the equation C = εε ₀ (A / d) (ε ₀ is the dielectric constant of vacuum). In particular, due to the recent trend of light and thin electronic and electrical equipment, the same demands will be made on printed wiring boards, and it is not possible to take a large capacitor electrode area within a certain printed wiring board area. It is almost impossible and it is clear that there is a limit to the improvement in terms of surface area (A). Accordingly, in order to increase the capacitance of the capacitor, it is necessary to reduce the thickness (d) of the dielectric layer if the surface area (A) of the capacitor electrode and the relative dielectric constant (ε) of the dielectric layer are constant. In addition, lack of film thickness uniformity is not preferable because of the large variation in quality as a capacitor.

  In addition, when there is a problem with positional accuracy during transfer or screen printing, the position between the upper electrode and the lower electrode formed at the corner is displaced, and the effective area of the surface area (A) that affects the capacitance of the capacitor is As a result, the capacitor performance as designed cannot be obtained, and the product quality is out of specification.

  Therefore, a multilayer printed wiring board manufacturing technique that has excellent dielectric layer thickness uniformity and capacitor circuit positional accuracy without requiring a complicated manufacturing method, and removes the dielectric layer as much as possible except for the capacitor circuit section. In addition, a multilayer printed wiring board having a built-in capacitor circuit has been demanded.

  Thus, as a result of diligent research, the inventors of the present invention have come up with a method for manufacturing a printed wiring board incorporating the capacitor circuit according to the present invention. This manufacturing method rather positively utilizes the disadvantage that the adhesion between the dielectric layer and the lower electrode is weak. And since the most common printed wiring board manufacturing process can be adopted, no special equipment investment is required, no unnecessary process increases, and industrial merit is great.

  The basic method for manufacturing a printed wiring board having a built-in capacitor circuit according to the present invention is “capacitor layer formation having a dielectric layer between a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode” It is a method for manufacturing a printed wiring board having a built-in capacitor circuit using a “material”, and includes the following steps A to G.

Step A: The second conductive layer of the capacitor layer forming material is provided with a nickel-phosphorus alloy layer at least on the surface in contact with the dielectric layer, and the second conductive layer of the capacitor layer forming material is formed on the outer surface of the second conductive layer of the capacitor layer forming material. A first insulating layer forming step of forming one insulating layer;
Process B: A slit etching process in which an etching resist layer is formed on the surface of the first conductive layer located in the outer layer, the etching pattern is exposed and developed, and the space between the upper electrode part and the unnecessary part is etched into a thin slit shape. .
Step C: After the slit etching, the unnecessary portion of the first conductive layer is peeled and removed, so that the dielectric layer of the unnecessary portion is also peeled off at the same time, and the first conductive layer unnecessary portion is peeled off to leave a necessary circuit including the upper electrode. Process.
Step D: Cover the surface on which the upper electrode is formed with an etching resist, perform etching pattern exposure to make the second conductive layer into the lower electrode shape, and develop, etch, and remove the resist to form the lower electrode into the lower electrode shape Process.
Step E: A second insulating layer forming step of forming a second insulating layer and a third conductive layer on the upper electrode surface.
Step F: An interlayer conduction means forming step for performing interlayer machining such as perforating processing for ensuring conduction between the capacitor circuit composed of the upper electrode / dielectric layer / lower electrode and the third conductive layer, and the like.
Step G: an outer layer circuit forming step of forming an outer layer circuit by etching the third conductive layer.

  The second conductive layer of the capacitor layer forming material is preferably provided with a nickel-phosphorus alloy layer on at least the surface in contact with the dielectric layer.

  Furthermore, the slit width when performing the slit etching is preferably in the range of 25 μm to 110 μm.

  And the printed wiring board obtained by the manufacturing method of a printed wiring board provided with the built-in capacitor circuit which concerns on this invention turns into a product excellent in manufacturing cost with high quality.

  In the method for manufacturing a multilayer printed wiring board having a built-in capacitor circuit according to the present invention, since a dielectric layer does not exist in an unnecessary portion, even if a signal circuit is formed in the vicinity of the capacitor circuit, transmission of a signal signal or the like In some cases, dielectric loss does not increase, and other circuit elements such as inductors can be embedded, so that the constraint conditions of circuit design can be greatly relaxed. Therefore, the printed wiring board provided with the built-in capacitor circuit obtained by this manufacturing method is of extremely high quality.

  Hereinafter, the present invention will be described in more detail through embodiments and examples.

  Hereinafter, the description will be divided into “a method for manufacturing a printed wiring board having a built-in capacitor circuit” and “a printed wiring board having a built-in capacitor circuit”.

(Embodiment of manufacturing method of printed wiring board having built-in capacitor circuit)
A manufacturing method of a multilayer printed wiring board (hereinafter simply referred to as “multilayer printed wiring board”) incorporating the capacitor circuit according to the present invention is mainly shown in FIGS. 2 to 4 and FIGS. It explains using. In the present invention, a lot of drawings are used for explanation. In the drawing, via holes for securing electrical continuity between the capacitor portion and the circuit between layers are formed at an arbitrary time point and shape based on a regular method. It can be done. Therefore, detailed description of these interlayer conduction means is omitted, and the present invention will be described so that the present invention can be clearly understood as a technical idea.

Capacitor layer forming material: First, a capacitor layer forming material used in a method for manufacturing a printed wiring board having a built-in capacitor circuit according to the present invention will be described. By using the capacitor layer forming material fabricated in advance as described above, the film thickness uniformity of the dielectric layer can be maintained at a high level. The capacitor layer forming material 2 includes a dielectric layer 5 between a first conductive layer 3 forming an upper electrode and a second conductive layer 4 forming a lower electrode, as shown in several variations in FIG. It has a layer structure. And as this capacitor layer constituent material becomes clear from the manufacturing method described later, it is not preferable that the interface between the second conductive layer 4 serving as the lower electrode and the dielectric layer 5 adheres extremely firmly.

  Therefore, the second conductive layer 4 can be formed by various methods such as bonding of metal foil, plating method, vapor deposition method, etc., but easily peels off by the following manufacturing method depending on the type of dielectric layer. Those having characteristics are preferably used selectively. For example, when a single second conductor layer is used as shown in FIG. 1A, it is preferable to use a nickel-phosphorus alloy that is a nickel alloy. Further, as shown in FIG. 1B, a nickel-phosphorus alloy layer 4a or the like is adopted as a two-layer structure on the surface of the second conductive layer in contact with the dielectric layer, and the others are a copper layer 4b. Further, as shown in FIG. 1C, a three-layer structure in which a nickel-phosphorus alloy layer 4a or the like is employed on the surface of the second conductive layer in contact with the dielectric layer and the other surface side may be used. When the second conductive layer is formed using a metal foil such as a copper foil provided with a surface treatment layer such as a nickel-phosphorus alloy, the capacitor layer forming material having the form shown in FIG. Conceivable. However, assuming the case where the lower electrode shape is formed by etching the second conductive layer, it is most preferable to use the capacitor layer forming material having the form shown in FIG. This is because it is difficult to dissolve the nickel alloy by the copper etching solution used in the printed wiring board manufacturing process, and the amount of nickel alloy can be reduced as much as possible.

  The first conductive layer 3 can also be formed by various methods such as bonding of metal foil, plating method, vapor deposition method, etc., considering that a general printed wiring board production line is used. Alternatively, it is preferable to use a copper alloy. However, as will be apparent from the following manufacturing method, since the first conductive layer 3 is peeled off with the dielectric layer 5 attached thereto, the first conductive layer 3 and the dielectric layer 5 can be easily separated. It must not happen. The adhesion strength between the first conductive layer 3 and the dielectric layer 5 is required to be at least higher than the adhesion strength between the second conductive layer 4 and the dielectric layer 5. Therefore, the material of the first conductive layer 3 may be determined in consideration of the adhesion strength between the second conductive layer 4 and the dielectric layer 5.

  For the dielectric layer, various known methods such as a so-called sol-gel method, a coating method in which a dielectric layer is formed by coating using a dielectric filler-containing resin solution containing a dielectric filler and a binder resin can be employed. .

Method for manufacturing printed wiring board having built-in capacitor circuit: Hereinafter, a method for manufacturing a printed wiring board having a built-in capacitor circuit according to the present invention will be described. When the capacitor layer forming material shown in FIG. Is illustratively shown. Hereinafter, Step A to Step G will be described for each step.

  Step A is a first insulating layer forming step of forming a first insulating layer on the outer surface of the second conductive layer of the capacitor layer forming material. That is, in this process, an insulating layer constituent material used for printed wiring board applications such as glass-epoxy prepreg and polyimide resin base material is pressed into the second conductive layer 4 of the capacitor layer forming material 2 shown in FIG. The insulating layer 6 is formed as shown in FIG. There are no particular limitations on the bonding method and conditions at this time. Further, as shown in FIG. 8, it is naturally possible to bond the second conductive layer 4 of the capacitor layer forming material on both surfaces of the insulating layer 6 with the insulating layer 6 as the center, thereby forming a capacitor layer on both surfaces. . However, the drawings will be described with a capacitor layer attached to one side.

  In step B, an etching resist layer 9 is formed on the surface of the first conductive layer located on the outer layer, the etching pattern is exposed and developed, and a slit is formed between the upper electrode portion and the unnecessary portion in a thin slit shape. Etching process. That is, as shown in FIG. 3C, in order to expose an etching pattern capable of slit etching with a width of 25 μm to 200 μm, after forming an etching resist layer, the exposure pattern film 7 is used for UV exposure and development. Then, slit etching is performed and the resist is peeled off. However, it is not necessary to remove the resist at this stage if necessary. This is because if it is left until it is completely unnecessary, damage to the upper electrode in a later process can be prevented. Therefore, in the drawings used for explanation, the state in a state where the resist is not removed is schematically shown. As a result, as shown in FIG. 3D, a slit 8 is formed between the upper electrode portion and the unnecessary portion. Here, the slit etching width is set to 25 μm to 200 μm. When the slit etching width is less than 25 μm, it is difficult to make the etching solution around the formed slit, the etching rate becomes extremely slow, and the side surface shape of the dielectric layer deteriorates. If the slit etching width exceeds 200 μm, the intrusion of the etching solution in the slit becomes too easy, and the solution intrusion into the interface between the lower electrode and the dielectric layer that lacks adhesion becomes easy, and the lower electrode and the dielectric layer It will interfere with the adhesion.

  In step C, after the slit etching is performed, the unnecessary portion of the first conductive layer is peeled and removed, so that the dielectric layer of the unnecessary portion is also peeled off at the same time, and the first conductive layer unnecessary portion that leaves the necessary circuit including the upper electrode remains. It is a peeling process. When an unnecessary portion is to be removed in this step, the adhesion strength between the first conductive layer 3 and the dielectric layer 5 is higher than the adhesion strength between the second conductive layer 4 and the dielectric layer 5. The conductive layer and the dielectric layer are peeled off at the same time, and the surface of the second conductive layer 4 is exposed at the peeled portion as shown in FIG.

  In step D, the surface on which the upper electrode 20 is formed is covered with an etching resist, etching pattern exposure is performed to form the second conductive layer into the lower electrode shape, and development, etching, and resist removal are performed to form the lower electrode shape. This is an electrode forming step. That is, as shown in FIG. 4F, an etching resist layer 9 ′ is formed on the surface on which the upper electrode 20 is formed, and UV exposure is performed using an exposure pattern film 7 ′ for etching the second conductive layer 4. Then, it is developed, etched, and the resist is peeled off. As a result, as shown in FIG. 5G, the lower electrode 21 is formed.

  Step E: A second insulating layer forming step of forming the second insulating layer and the third conductive layer on the upper electrode surface. Here, although referred to as a second insulating layer forming step, the second insulating layer 10 and the third conductive layer 11 are simultaneously formed on the upper electrode surface. At this time, a method as described below can be adopted as a method of bonding the second insulating layer 10 and the third conductive layer 11 together.

  In forming the second insulating layer and the third conductive layer on the upper electrode surface, a prepreg 12 such as a glass-epoxy material and a metal foil 13 are used, and are stacked and pressed as shown in FIG. The state is the same as (h). In addition, description of frame | skeleton materials 13, such as a glass cloth, is abbreviate | omitted in the 2nd insulating layer 10 of FIG.5 (h).

  Further, in forming the second insulating layer and the third conductive layer on the upper electrode surface, as shown in FIG. 10, the metal foil 14 with a resin layer is stacked on the upper electrode surface and bonded together by pressing, as shown in FIG. It is also preferable to use the same state as in (h). The metal foil with a resin layer mentioned here is provided with a semi-cured resin layer 15 for constituting an insulating layer on one side of the metal foil.

  Further, when forming the second insulating layer 10 and the third conductive layer 11 on the upper electrode surface, as shown in FIG. 11, the metal foil 16 with a skeleton material-containing resin layer is stacked on the upper electrode surface and pressed. It is also preferable that the same state as in FIG. The metal foil with a skeleton material-containing resin layer referred to herein is a skeleton including a skeleton material 17 such as a woven fabric or a non-woven fabric such as a glass fiber or an aramid fiber in a resin layer for constituting an insulating layer on one side of the metal foil. The material-containing resin layer 18 is provided.

  Step F is an interlayer conduction means forming step in which drilling is performed to ensure conduction between the capacitor circuit composed of the upper electrode / dielectric layer / lower electrode and the third conductive layer, and interlayer conduction plating is performed. In this step, as shown in FIG. 6 (i), drilling (drilling processing) is performed to form via holes and through holes, and FIG. 6 (j) shows a state where interlayer conductive plating 17 is performed. Yes. The interlayer conduction means can use not only the plating method but also a conductive paste filling method.

  Step G is an outer layer circuit forming step for forming an outer layer circuit by etching the third conductive layer 11. Based on a conventional method, an etching resist layer is formed on the third conductive layer 11, UV exposure is performed using an exposure pattern film for etching the third conductive layer 11, development is performed, etching is performed, and the resist is peeled off. To do. As a result, as shown in FIG. 7 (k), the outer layer circuit 17 is formed and takes the form of the printed wiring board 1.

Printed wiring board with built-in capacitor circuit: A printed wiring board with a built-in capacitor circuit is obtained through the above-described steps. In this printed wiring board, there is no dielectric layer other than the built-in capacitor part, and the capacitor circuit part is wrapped in the constituent resin of the insulating layer, so that the problem of adhesion between the dielectric layer and the insulating layer does not occur. Less delamination occurs in the inner layer. In addition, as long as this manufacturing method is employed, the film thickness uniformity of the dielectric layer is good, and the positional accuracy of the capacitor circuit is also good. Examples will be shown below.

Step A: First, the capacitor layer forming material will be described. The capacitor layer forming material used in this example is as shown in FIG. That is, the first conductive layer 3 for forming the upper electrode is a copper layer formed by sputtering deposition having a thickness of 5 μm, and the second conductive layer 4 for forming the lower electrode is an electrolytic copper foil having a thickness of 35 μm. A surface-treated electrolytic copper foil provided with a nickel-phosphorus alloy plating layer having a thickness of 3 μm on both sides was used. The dielectric layer 5 positioned between the first conductive layer and the second conductive layer was formed as a dielectric film on the surface of the second conductive layer using a sol-gel method. In the sol-gel method used at this time, ethanolamine was added to a methanol solution heated near the boiling point as a stabilizer so as to have a concentration of 50 mol% to 60 mol% with respect to the total amount of metal, titanium isopropoxide, A sol-gel solution in which a propanol solution of zirconium propoxide, lead acetate, lanthanum acetate, and nitric acid as a catalyst were sequentially added and finally diluted to 0.2 mol / l with methanol was used. Then, using a spin coater, this sol-gel solution was applied to the surface of the nickel-phosphorus alloy layer of the surface-treated copper foil, dried in an air atmosphere at 250 ° C. for 5 minutes, and in an air atmosphere at 500 ° C. for 15 minutes. Perform pyrolysis. Further, the coating process was repeated 6 times to adjust the film thickness. Finally, a baking process was performed in a nitrogen substitution atmosphere at 600 ° C. for 30 minutes to form a dielectric layer. The composition ratio of the dielectric layer at this time was Pb: La: Zr: Ti = 1.1: 0.05: 0.52: 0.48. The adhesion strength between the first conductive layer 3 (copper component) and the dielectric layer 5 as described above is higher than the adhesion strength between the second conductive layer 4 (surface nickel-phosphorus alloy component) and the dielectric layer 5, It is possible to peel off the unnecessary portion and the dielectric layer at the same time.

The nickel-phosphorus alloy layer is formed by using a phosphoric acid solution on both sides of an electrolytic copper foil having a thickness of 35 μm, a nickel sulfate concentration of 250 g / l, a nickel chloride concentration of 40.39 g / l, and H ₃ BO _3. Electrolysis was performed under conditions of a concentration of 19.78 g / l, a H ₃ PO ₃ concentration of 3 g / l, a liquid temperature of 50 ° C., and a current density of 20.4 A / dm ^2. -The phosphorus alloy layer was electrodeposited uniformly and smoothly.

  Using this capacitor layer forming material 2, the FR-4 prepreg having a thickness of 50 μm is bonded to the second conductive layer 4 by pressing at about 180 ° C. for about 60 minutes based on a conventional method, and FIG. An insulating layer 6 was formed as shown in FIG.

Step B: Here, an etching resist layer 9 is formed by laminating a dry film having a thickness of 25 μm on the surface of the first conductive layer 3 located in the outer layer, and an etching pattern is exposed as shown in FIG. Development was performed, and the resist was peeled off by slit etching for etching the upper electrode portion and the unnecessary portion into a thin slit shape. The slit etching width at this time was 100 μm. As a result, as shown in FIG. 3D, a slit 8 was formed between the upper electrode portion and the unnecessary portion.

Step C: When slit etching is completed, the unnecessary portion of the first conductive layer is physically peeled off and removed, and the unnecessary portion and the dielectric layer can be removed at the same time during the peeling operation. There was no residual dielectric layer on the surface. As a result, as shown in FIG. 4E, the surface of the second conductive layer 4 is exposed at the peeling portion.

Step D: Here, as shown in FIG. 4 (f), an exposure for etching the second conductive layer 4 by forming an etching resist layer 9 ′ using a liquid resist on the surface on which the upper electrode 20 is formed. The pattern film 7 ′ was used for UV exposure, development, etching, and resist stripping. As a result, the shape of the lower electrode 21 was formed as shown in FIG.

Step E: Here, the second insulating layer 10 and the third conductive layer 11 are simultaneously formed on the upper electrode surface. At this time, the second insulating layer 10 and the third conductive layer 11 are laminated by using the resin layer-attached metal foil 14 and overlapping the resin layer-attached metal foil 14 on the upper electrode surface as shown in FIG. Bonding was performed by pressing at about 180 ° C. for about 60 minutes to obtain the same state as in FIG. The metal foil with a resin layer mentioned here is provided with a semi-cured resin layer for constituting an insulating layer on one side of the metal foil.

  The metal foil with resin layer used in this example is an electro-deposited copper foil having a nominal thickness of 18 μm and a roughened surface with a surface roughness (Rzjis) of 3.0 μm, and the surface thereof is semi-cured by coating. A resin layer was formed. A resin composition used for forming the semi-cured resin layer was prepared. Here, as resin, bisphenol A type epoxy resin (trade name: YD-128, manufactured by Tohto Kasei Co., Ltd.) 30 parts by weight, o-cresol type epoxy resin (trade name: ESCN-195XL80, manufactured by Sumitomo Chemical Co., Ltd.) 50 parts by weight 16 parts by weight of dicyandiamide (4 parts by weight as dicyandiamide) in the form of a dimethylformaldehyde solution having a solid content of 25% as an epoxy resin curing agent, and 2-ethyl 4-methylimidazole (trade name: Cazole 2E4MZ, Shikoku Chemicals) as a curing accelerator 0.1 part by weight is dissolved in a mixed solvent of methyl ethyl ketone and dimethyl formaldehyde (mixing ratio: methyl ethyl ketone / dimethyl formaldehyde = 4/6) to obtain a resin composition having a solid content of 60%, and this is an electrolytic copper foil It was used by coating on the rough surface. Then, the mixture was left at room temperature for 30 minutes, and a hot air at 150 ° C. was blown for 2 minutes using a hot air dryer to remove a certain amount of solvent, and a 50 μm thick semi-cured resin film was obtained. .

Step F: Drilling is performed for forming a via hole by a laser method for ensuring conduction between the capacitor circuit comprising the upper electrode / dielectric layer / lower electrode and the third conductive layer, as shown in FIG. It was in the state. Then, as the interlayer conductive plating 17 for plating the inner wall of the via hole to ensure the interlayer conductive, copper plating was performed based on a conventional method to obtain the state shown in FIG.

Step G: Here, an etching resist layer is formed on the third conductive layer 11 using a dry film having a thickness of 25 μm, and UV exposure is performed using an exposure pattern film for etching the third conductive layer 11. Then, development, etching, and resist peeling were performed to form the outer layer circuit 17 as shown in FIG.

  Since the dielectric layer does not exist in the unnecessary part in the same plane where the built-in capacitor circuit is manufactured, the dielectric loss at the time of signal signal transmission of the signal circuit is Other circuit elements such as an inductor can be embedded in a small size. Therefore, circuit design is facilitated and design variations are dramatically improved. A printed wiring board provided with a built-in capacitor circuit obtained by the manufacturing method according to the present invention is of extremely high quality, but can be efficiently produced with the above manufacturing method and can be easily supplied to the market. .

The schematic cross section which shows the variation of the capacitor layer forming material used by this invention. The schematic diagram showing the manufacture flow of the printed wiring board which incorporates a capacitor circuit. The schematic diagram showing the manufacture flow of the printed wiring board which incorporates a capacitor circuit. The schematic diagram showing the manufacture flow of the printed wiring board which incorporates a capacitor circuit. The schematic diagram showing the manufacture flow of the printed wiring board which incorporates a capacitor circuit. The schematic diagram showing the manufacture flow of the printed wiring board which incorporates a capacitor circuit. The schematic diagram showing the manufacture flow of the printed wiring board which incorporates a capacitor circuit. The schematic diagram which shows one form in the case of forming a capacitor circuit on both surfaces of an insulating layer. The schematic diagram showing the aspect which forms a 2nd insulating layer and a 3rd conductive layer on an upper electrode surface using a prepreg and metal foil. The schematic diagram showing the aspect which forms a 2nd insulating layer and a 3rd conductive layer on an upper electrode surface using the metal foil with a resin layer. The schematic diagram showing the aspect which forms a 2nd insulating layer and a 3rd conductive layer on an upper electrode surface using metal foil with a frame material containing resin layer. The schematic cross section showing the manufacturing flow of the prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Printed wiring board 2a, 2b, 2c provided with built-in capacitor circuit Capacitor layer forming material 3 1st conductive layer 4 2nd conductive layer 4a Layer 4b of nickel-phosphorus alloy etc. Copper layer 5 Dielectric layer 6 1st insulating layer 7 Etching pattern Exposed film 8 Slit 9, 9 'Etching resist layer 10 Second insulating layer 11 Third conductive layer 12 Prepreg 13 Metal foil 14 Metal foil with resin layer 15 Semi-cured resin layer 16 Metal foil 17 with skeleton material-containing resin layer Skeleton material 18 Skeletal material-containing resin layer 20 Upper electrode 21 Lower electrode

Claims (4)

A method of manufacturing a printed wiring board having a built-in capacitor circuit using a capacitor layer forming material having a dielectric layer between a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode,
The manufacturing method of a printed wiring board provided with the built-in capacitor circuit characterized by including the following processes A-G.
Step A: A first insulating layer forming step of forming a first insulating layer on the outer surface of the second conductive layer of the capacitor layer forming material.
Process B: A slit etching process in which an etching resist layer is formed on the surface of the first conductive layer located in the outer layer, the etching pattern is exposed and developed, and the space between the upper electrode part and the unnecessary part is etched into a thin slit shape. .
Step C: After the slit etching, the unnecessary portion of the first conductive layer is peeled and removed, so that the dielectric layer of the unnecessary portion is also peeled off at the same time, and the first conductive layer unnecessary portion is peeled off to leave a necessary circuit including the upper electrode. Process.
Step D: Cover the surface on which the upper electrode is formed with an etching resist, perform etching pattern exposure to make the second conductive layer into the lower electrode shape, and develop, etch, and remove the resist to form the lower electrode into the lower electrode shape Process.
Step E: A second insulating layer forming step of forming a second insulating layer and a third conductive layer on the upper electrode surface.
Step F: An interlayer conduction means forming step for performing interlayer machining such as perforating processing for ensuring conduction between the capacitor circuit composed of the upper electrode / dielectric layer / lower electrode and the third conductive layer, and the like.
Step G: an outer layer circuit forming step of forming an outer layer circuit by etching the third conductive layer. 2. The method of manufacturing a printed wiring board having a built-in capacitor circuit according to claim 1, wherein the second conductive layer of the capacitor layer forming material includes a nickel-phosphorus alloy layer on at least a surface in contact with the dielectric layer. The manufacturing method of a printed wiring board provided with a built-in capacitor circuit according to claim 1 or 2, wherein a slit width in the case of performing the slit etching is 25 to 200 µm.
The printed wiring board obtained by the manufacturing method of a printed wiring board provided with the built-in capacitor circuit in any one of Claims 1-3.

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