JP2006079695A - Nonvolatile semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device capable of preventing prolonged writing or erasing due to a later failure.
A nonvolatile semiconductor memory device includes a memory cell array having electrically rewritable nonvolatile memory cells, a sense amplifier circuit for reading data from the memory cell array, and the sense amplifier circuit holding at the time of writing or erasing. A pass / fail detection circuit for detecting completion of writing or erasing based on verify read data, and the pass / fail detection circuit has a data latch configured to be able to write defective column separation data in accordance with a command input. .
[Selection] Figure 1

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).

  In the write sequence of the EEPROM flash memory, normally, the write voltage application and the subsequent write verify are repeated in order to keep the threshold distribution of the write data within a certain range. After the verify read, a verify determination (pass / fail determination) is performed to check whether all the write data has been written. When it is determined that writing of all bits is completed, the writing sequence is completed. When there is an insufficiently written bit, the writing voltage is applied again.

  The maximum value (the number of write cycles or the number of loops) Nmax of the write voltage application frequency is set in advance. If writing of all bits is not completed even when the number of times of writing reaches Nmax, the writing sequence ends.

  When the flash memory system has an ECC function outside or inside the chip, the presence of a certain number of fail (number of fail bits or number of fail columns) is allowed in relation to the ECC function. Therefore, it is desirable to detect the number of failures when writing ends with “fail” and to make a “pseudo pass” when this is within the allowable number of failures.

  From this point of view, a flash memory has already been proposed that enables high-speed verification determination and enables pass / fail detection in relation to the number of allowable failures (see Patent Document 1).

  In addition, in a large capacity flash memory, a redundancy system for defect repair is employed. That is, a redundant cell array is prepared so as to replace a defective portion (for example, a defective column) when an allowable range of defects is detected in a test before shipment. Further, the memory chip is provided with a defective address storage circuit, and an address coincidence detection circuit for detecting coincidence between an externally supplied address and the defective address held by the defective address storage circuit. Control is performed.

  As the defective address storage circuit, a fuse circuit or a ROM circuit is usually used. There has also been proposed a method of storing defective address data together with various other initial setting data in the memory cell array without providing these fuse circuits and ROM circuits (see, for example, Patent Document 2). In this case, the defective address data is automatically read when the power is turned on and transferred to the initial setting register (defective address register). Based on the defective address data held in the defective address register, defective address replacement control is performed thereafter.

When the redundancy system is employed in this way, it is necessary to exclude the defective portion from the determination target in the verification determination. Otherwise, the writing sequence will always fail until the maximum number of writings Nmax is repeated. The same applies to erasure. For this reason, the verify determination circuit is provided with a data latch that holds data for separating a defective column (see Patent Document 1).
JP 2003-140899 A JP 2001-176290 A

    Conventional flash memories cannot deal with defects that occur after shipment. As described above, a certain fail is allowed in relation to the ECC function, and therefore a defect that occurs after shipment is allowed within the range.

    However, if a late failure is left as it is, writing time and erasing time become long. This is because, as described above, the write sequence including the defective address is always written to the maximum number of times of writing Nmax and fails. The same applies to erasure.

    An object of the present invention is to provide a nonvolatile semiconductor memory device that can prevent a prolonged writing or erasing due to a later failure.

A nonvolatile semiconductor memory device according to one aspect of the present invention is provided.
A memory cell array having electrically rewritable nonvolatile memory cells;
A sense amplifier circuit for reading data from the memory cell array;
A pass / fail detection circuit for detecting write or erase completion based on verify read data held by the sense amplifier circuit at the time of writing or erasing;
The pass / fail detection circuit includes a data latch configured to write defective column separation data in accordance with a command input.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device that can prevent a prolonged writing or erasing due to a later failure.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a functional block configuration of a flash memory according to an embodiment of the present invention, and FIG. 2 shows a configuration of the memory cell array 1.

  The memory cell array 1 is configured by arranging NAND cell units NU in a matrix. Each NAND cell unit NU connects a plurality (16 in the example of FIG. 2) of electrically rewritable nonvolatile memory cells M0 to M15 and both ends thereof connected to the source line CELSRC and the bit line BL, respectively. Select gate transistors S1 and S2.

  The control gates of the memory cells in the NAND cell unit are connected to different word lines WL0 to WL15. The gates of the selection gate transistors S1 and S2 are connected to selection gate lines SGS and SGD, respectively.

  A set of NAND cell units sharing one word line constitutes a block serving as a data erasing unit. As shown in FIG. 2, a plurality of blocks BLK0, BLK1,... Are arranged in the bit line direction.

  The row decoder 3 selectively drives a word line and a selection gate line according to a row address, and includes a word line driver and a selection gate line driver. The sense amplifier circuit 2 is connected to a bit line to read data in units of pages, and also serves as a data latch that holds write data for one page. Using such a sense amplifier circuit 2, reading and writing are performed in units of pages. Sense amplifier circuit 2 includes a data cache for relaying data exchange with data lines.

  The memory cell array 1 has a redundant column cell array (not shown) used for defective column replacement, in addition to a normal cell array used for normal data reading / writing. Corresponding to these, the sense amplifier circuit 2 is also provided with a normal sense amplifier circuit and a redundant sense amplifier circuit.

  FIG. 2 shows an example in which one sense amplifier P / B of the sense amplifier circuit 2 is arranged on each bit line BL. However, when the memory cell array 1 is miniaturized, it becomes difficult to arrange the sense amplifiers at the bit line pitch. Therefore, in the large-capacity flash memory, as shown in FIG. 3, a method in which two adjacent bit lines BLe and BLo share one sense amplifier P / B is used. Two adjacent bit lines BLe and BLo are selectively connected to a sense amplifier P / B by bit line selection gates Qe and Qo.

  In the example of FIG. 2, a set of memory cells arranged along one word line constitutes one page. In a system in which adjacent two bit lines share a sense amplifier, a set of memory cells along one word line constitutes two pages.

  Data exchange between the sense amplifier circuit 2 and the external input / output terminal I / O is performed via the I / O buffer 6 and the data bus 14. A column gate circuit controlled by a column selection signal CSLi is attached to the sense amplifier circuit 2, and the column decoder 4 performs this column gate control. For example, as shown in FIG. 2, the number of input / output terminals I / O is eight (I / O0-I / O7), and between the sense amplifier circuit 2 and the external input / output terminal I / O is 1 by the above-described column control. Serial data transfer is performed in byte units (column units).

  The address “Add” supplied via the input / output terminal I / O is transferred to the row decoder 2 and the column decoder 4 via the address register 5. A command “Com” supplied via the input / output terminal I / O is decoded by a state control circuit (hereinafter referred to as a controller) 10. The controller 10 performs data write and erase sequence control and read operations based on various external control signals (write enable signal WEn, read enable signal REn, command latch enable signal CLE, address latch enable signal ALE, etc.) and a command Com. Take control.

  The internal voltage generation circuit 9 is controlled by the controller 10 to generate various internal voltages necessary for write, erase and read operations. A booster circuit is used to generate an internal voltage higher than the power supply voltage. . The status register 12 is used to output a status signal R / B indicating whether the chip is in a read or write ready state or a busy state to the outside of the chip.

  The parameter register 8 holds various initial setting data and defective address data including voltage adjustment data for adjusting various internal voltages output from the internal voltage generation circuit 9. These data are written in advance in the initial setting data area of the memory cell array 1. When the power is turned on, the controller 10 receives the power-on detection signal output from the power-on reset circuit 11, and the controller 10 automatically reads the initial setting data of the memory cell array 1, transfers it to the parameter register 8, and sets it automatically. To do.

  The address match detection circuit 7 detects the match between the external address and the defective address held in the parameter register 8 and outputs an address replacement control signal. As a result, control for selecting a redundant column in place of a defective column is performed.

  FIG. 4 shows the configuration of one sense amplifier P / B of the sense amplifier circuit 2. The NMOS transistor MN1 arranged between the sense node Nsen and the bit line BL functions to clamp the precharge voltage of the bit line BL and as a pre-sense amplifier that amplifies the bit line voltage. A precharge NMOS transistor Q2 is connected to the sense node Nsen, and a charge holding capacitor C1 is connected as necessary.

  The sense node Nsen is connected to one data node N1 of the data latch 21 via the transfer NMOS transistor Q3. A data storage circuit 24 for temporarily storing read data is provided between the data node N1 and the sense node Nsen. The gate of the NMOS transistor Q4 whose drain is connected to the voltage terminal VREG is the data storage node NR. A data transfer NMOS transistor Q6 is arranged between the storage node NR and the data node N1 of the data latch 21. An NMOS transistor Q5 is arranged between the NMOS transistor Q4 and the sense node Nsen in order to transfer the voltage VREG to the sense node Nsen according to the data held in the storage node NR.

  The data storage circuit 24 holds the write data of the previous cycle, and uses it as a write-back circuit for writing back “0” data to the data latch 21 only for cells where “0” is insufficiently written in the verify read operation. It is done. In other words, the control is performed so that the data latch 21 is in an all “1” data state when writing of all bits of one page is completed.

  Another data latch 22 constituting a data cache is connected to the data node N1 via a transfer NMOS transistor Q7. One page of read / write data is transferred simultaneously between the data latches 21 and 22. Data nodes N11 and N12 of the data latch 22 are connected to complementary data lines DL and DLn via column selection gates Q11 and Q12 controlled by a column selection signal CSLi.

  A data detection circuit 23 activated at the time of verify determination is connected to the data node N1 of the data latch 21. The data detection circuit 23 includes a PMOS transistor QP1 having a gate connected to the data node N1, and a switching NMOS transistor Q13 disposed between the drain and the ground terminal. As shown in FIG. 5, the source of the PMOS transistor QP1 is connected to the first detection line COMi common to the eight sense amplifiers P / B in each column. Each detection line node COMi is connected to a PMOS transistor QP30 for precharging it to “H” level.

  At the time of verify determination, data determination is performed by inputting the check signal VERCHK to the gate of the NMOS transistor Q13. The data latch 21 is in an all “1” data state (data node N1 = “H”) when writing of all bits is completed by verify reading, and corresponds to the case where writing of “0” is not completed even with one bit. The data node N1 becomes “L”.

  After the write verify, the detection line COMi is precharged to the “H” level in advance and the check signal VERCHK is input. If all the bits in the column have been written, the PMOS transistor QP1 is kept off and the detection line COMi. Is not discharged. If even one bit has not been written, the PMOS transistor QP1 is turned on, and the detection line COMi is discharged to the “L” level. By monitoring the voltage change of the detection line COMi, verification determination (pass / fail detection) can be performed.

  The pass / fail detection circuit 13 shown in FIG. 1 is connected to the detection line COMi of each column of the sense amplifier circuit 2, and has the function of performing the above-described pass / fail judgment on the verify read result of each write cycle, and the number of failures. It has a function of detecting (the number of fail bits or the number of fail columns).

  The configuration of the pass / fail detection circuit 13 is specifically shown in FIGS.

  As shown in FIG. 6, the pass / fail detection circuit 13 includes a write completion detection circuit 31 connected to the first detection line COMi of each column. This is a level transition detection circuit that detects a level transition of the detection line COMi, and is a pre-sense circuit for pass / fail judgment.

  The output of the write completion detection circuit 31 is connected to the common second detection line LSEN. As will be described later, each write completion detection circuit 13 is configured to detect a decrease in the level of the first detection line COMi and to flow a predetermined current when there is a fail bit in the column. The second detection line LSEN is configured such that a current corresponding to the total sum of currents flowing through the completion detection circuits 31, that is, the number of failures (the number of bits or the number of columns) flows.

  The pass / fail judgment is made based on the current corresponding to the number of failures flowing in the second detection line LSEN. In order to make this determination by comparison with the allowable number of failures, an allowable number-of-failures setting circuit 32 constituting a reference current source circuit is provided.

  As shown in FIG. 7, in the write completion detection circuit 31, a PMOS transistor QP41 whose detection node COMi is connected to the gate and a PMOS transistor QP42 whose node N22 of the data latch 35 is connected to the gate are connected in series to the power supply Vcc. Has been. The data latch 35 holds “defective column separation data” for excluding the defective column from the target of verification determination (pass / fail detection). That is, separation data is written in advance so that the data node N22 becomes “H” in the defective column. As a result, the PMOS transistor QP42 is turned on only for the normal column.

  The drain of the PMOS transistor QP42 is connected to the gate of the NMOS transistor Q44. As shown in FIG. 6, the drain of the NMOS transistor Q44 is connected to the second detection node LSEN common to the detection circuits 31 of all the columns, and the current source circuit 36 is connected to the source.

  The current source circuit 36 includes two current source NMOS transistors Q45 and Q46, which are selectively used. A reset NMOS transistor Q43 is connected to the gate of the NMOS transistor Q44.

  The current source transistor Q45 flows to the second detection line LSEN when the NMOS transistor Q44 is turned on in response to the “L” level transition of the first detection line COMi when the corresponding column is failed during the verify determination. The current I is determined. Since the second detection line LSEN is wired or connected to the outputs of the detection circuits 31 of all the columns, the number of failures (the number of fail bits or the number of fail columns) N depends on the number N as shown in FIG. Current Ifail1 = I × N flows.

  The current source NMOS transistor Q45 allows a current I to flow when the number of allowable failures is zero (that is, when even one is insufficiently written, “fail”). The size of the current source NMOS transistor Q46 provided along with the current source is designed so that a current of 0.5I flows when, for example, two failures are allowed. These are selected by control signals VREF and VREF1.

  The data latch 35 is written with defective column separation data according to the test result before shipment. That is, defective column separation data is written in the initial setting data storage area of the memory cell array 1 and is automatically read when the power is turned on and written in the data latch 35. This data latch 35 is normally not modified thereafter. In this embodiment, the data in the data latch 25 can be rewritten so that a defective column generated after shipment is removed from the pass / fail detection target.

  For this purpose, an NMOS transistor Q31 whose gate is driven by the column selection signal CSL and an NMOS transistor Q32 whose gate is driven by the activation signal FCEN are connected in series between the data node N21 and the ground terminal Vss. A reset NMOS transistor Q33 is connected to the data node N22.

  As will be described later, a column defect can be detected by a test after shipment. When a defective column is found, the separation data is written into the data latch 35 according to the command input. That is, the NMOS transistor Q31 is turned on by the column selection signal CSL, and the NMOS transistor Q32 is turned on by the activation signal FCEN from the controller 10, so that the data latch 35 is disconnected from the column with N21 = "L" and N22 = "H". Data is latched.

  The allowable failure number setting circuit 32 generates a current Ipass corresponding to the allowable number of failures for comparing and contrasting the current Ifail1 corresponding to the number of failures obtained at the detection node LSEN common to the detection circuits 31 of all the columns. This is composed of a plurality of current source circuits 32a to 32d.

  The current source circuit 32a has a current source NMOS transistor Q20 that supplies a current of 0.5I. The current source transistor Q20 is connected to the common node IREF via the fuse circuit via the selection transistor Q22 controlled by the signal Bpass. The current source circuit 32b includes a current source NMOS transistor Q21 for passing a current I, which is also connected to the node IREF via a selection NMOS transistor Q22 and a fuse circuit. The current source circuit 32c has two current source NMOS transistors Q21 for passing the current 2I, which are also connected to the node IREF via the selection transistor Q22 and the fuse circuit.

  Furthermore, the current source circuit 32d has four current source NMOS transistors Q21 for passing a current 4I, which are similarly connected to the node IREF via the selection transistor Q22 and the fuse circuit.

  The selection transistors Q22 of the current source circuits 32b to 32d are activated by selection signals B0, B1, and B2 that determine the allowable number of failures, respectively. The selection transistor Q22 of the current source circuit 32a is controlled by a selection signal Bpass that is always “H” when a pass / failure is detected.

  At the time of pass / fail judgment, the current Ipass corresponding to the allowable number of passes Npass flowing through the node IREF is determined by the selection signals B0 to B2, and becomes Ipass = I × Npass + 0.5I.

  A PMOS current mirror circuit 33 is provided in order to compare the current Ifail1 flowing through the detection node LSEN common to the write completion detection circuit 31 of all the columns and the current Ipass flowing through the node IREF of the allowable fail number setting circuit 32. ing. The gate and drain of the PMOS transistor QP11 constituting the current mirror circuit 33 are connected to the detection node LSEN, and the drain of the PMOS transistor QP12 is connected to the voltage detection node 35 together with the node IREF. An output circuit 37 composed of an inverter is connected. If the transistors QP11 and QP12 have the same dimensions, a current Ifail2 = Ifail1 flows through the drain of the transistor QP12.

  The current mirror circuit 33, the detection node 35, and the output circuit 27 constitute a comparison circuit. The level of the detection node 35 is determined according to the magnitude of the current Ifail2 (= Ifail1) and Ipass. Accordingly, when verify determination is performed in a certain combination state of the 3-bit selection signals B0 to B2, when the current Ifail2 exceeds Ipass, an "H" output is obtained as the output VOUT. This is a “fail” signal determined by the relationship with the allowable number of failures.

  This will be specifically described. When (B2, B1, B0) = (0, 0, 0), Ipass = 0.5I. If all the columns are verified “pass”, Ifail2 = 0, the output VOUT is “L”. On the other hand, if there is a failure in one column, Ifail2 = I, the output VOUT becomes “H”. Thereby, it can be determined whether there is one or more failures. When (B2, B1, B0) = (0, 0, 1), Ipass = I + 0.5I. Therefore, it is possible to determine whether there are two or more failures by comparing with Ifail2.

  Similarly, as summarized in FIG. 8, the number of allowable failures is determined by the selection signals (B2, B1, B0), and this makes it possible to perform pass / fail determination with the allowable number of failures set.

  Furthermore, the number of failures can be obtained by sequentially incrementing the selection signals (B2, B1, B0) and seeing where the output VOUT = “H” is obtained. That is, the pass / fail detection circuit 13 also functions as a fail number counter.

  The fail bit detection and fail column detection can be selected depending on whether the verify check signal VERCHK shown in FIG. 4 is separately applied to the eight sense amplifiers P / B in the column or simultaneously. That is, when verifying each bit in each write cycle, the operation of sequentially applying the verify check signal VERCHK to each sense amplifier P / B in the column is repeated. Thereby, a pass / failure can be detected in bit units.

  On the other hand, if the verify check signal VERCHK is simultaneously applied to eight sense amplifiers in one column, the detection line COM becomes “L” when there is even one fail bit in the column. Thereby, a column failure can be detected.

  FIG. 9 shows a data write control flow in this embodiment. The write mode is set by inputting the write command. When a write address is input (step S1), and then one page of write data is loaded into the sense amplifier circuit 2 (step S2), writing to the selected page is automatically performed under the control of the controller 10 below.

  That is, writing is performed by applying a write voltage to the selected word line corresponding to the selected page (step S3). Specifically, according to the write data “0”, “1”, Vss, Vcc−Vth (Vth is a threshold value of the selection gate transistor) from the sense amplifier circuit 2 through each selected bit line to the NAND cell channel. Voltage). The NAND cell channel to which “1” data (write inhibit) is applied rises to Vcc−Vth and becomes floating.

  When a write voltage is applied to the selected word line in this state, in the “0” write cell, electrons are injected into the floating gate and “0” data having a positive threshold voltage is written. In the “1” write cell, the channel rises in potential and no electron injection occurs.

  After the write voltage is applied, it is determined whether or not the number of write cycles has reached the maximum value Nmax (step S4), and if not, write verify is performed (step S5). The pass / fail judgment of the verify read result is a selection signal condition of (B2, B1, B0) = (0, 0, 0), that is, a condition for judging as fail if there is even one insufficiently written cell. To do. In the case of a failure, the write voltage is stepped up (step S6), and the write voltage is applied again (step S3).

  When it is confirmed that one page has been written, the write verify is “pass” and the write operation is completed. If the number of write cycles reaches the maximum value Nmax and the write is not yet completed, the write has failed. At this time, a fail number detection operation is performed (step S7). The detected number of failures is output to a host device outside the chip.

  In the above data write operation, if there is a non-writeable defect (for example, bit line short circuit or bit line open) that has occurred after product shipment, the write verify is not passed and the number of write cycles reaches the maximum value Nmax. Writing will be repeated until it reaches. This causes a problem that the writing time becomes long even in a range where a late failure is allowed.

  Therefore, in this embodiment, a subsequent bit line defect is detected, and the detected defective part is excluded from the verification determination target.

  FIG. 10 shows a circuit configuration necessary for the bit line defect check. One end of each of the bit lines BLe and BLo is connected to the sense amplifier P / B via the selection transistors Qe and Qo. The other ends of these bit lines BLe and BLo are connected to a normal ground signal line BLCRL via selection transistors Qa and Qb.

  FIG. 10 shows two bit lines BLe having an open defect and a short defect. These defect checks are automatically performed by issuing a specific command.

  FIG. 11 shows a check operation waveform for a bit line open failure. In all NAND cell units connected to the bit lines, the selection gate transistors are kept off. FIG. 11 shows the check operation of the even-numbered bit line BLe. At time t0, “H” level is applied to the selection signal BLSe, and simultaneously, “H” level (= Vcc + Vth) is applied to the gate BLCLAMP of the clamping transistor Q1 of the sense amplifier P / B, and the precharging transistor Q2 is turned on.

  As a result, the selected bit line BLe is charged up to Vcc. After returning BLSe and BLCLAMP to “L”, if the “H” level is applied to the selection signal BIASe at time t1, the normal bit line BLe is discharged. An open defective bit line is not discharged at least from the defective portion, and maintains an “H” level as indicated by a broken line.

  After a certain bit line discharge operation, the sense voltage Vsen + Vth is applied to the gate BLCLAMP of the clamping transistor Q1 at time t2 to detect “H” and “L” of the bit line BLe. Thereby, an open defective bit line can be detected. It is possible to check the odd-numbered bit line BLo as well.

  FIG. 12 shows the bit line short circuit check operation for the case where the even-numbered bit line BLe is selected. At time t0, “H” level is applied to the selection signal BLSe, and simultaneously, “H” level (= Vcc + Vth) is applied to the gate BLCLAMP of the clamping transistor Q1 of the sense amplifier P / B, and the precharging transistor Q2 is turned on. Thus, if the bit line BLe is normal, it is charged to Vcc, and if there is a short circuit, it is not charged as shown by the broken line.

  After BLSe and BCLAMP are set to “L”, a sense voltage Vsen + Vth is applied to the gate BLCLAMP of the clamping transistor Q1 at time t1 to detect “H” and “L” of the bit line BLe. Thereby, a bit line short circuit defect can be detected.

  In order to remove the new column defect detected as described above from the verification determination target, the defective column separation data is written by command input. That is, as shown in FIG. 13, a predetermined command is input, and subsequently the detected defective column address is input (step S21). As a result, in the verify determination circuit 31 of the selected column, the column selection signal CSL becomes “H”, the control signal FCEN from the controller 10 becomes “H”, and the data latch 35 has N21 = “L”, N22. The defective column separation data that becomes = “H” is written (step S22).

  As a result, it is possible to avoid a situation in which the writing time becomes long due to a late failure. When counting the number of failures, for example, if the allowable number of failures is 8, it is necessary to scan all combinations of the selection signals B0 to B2, which takes much time. When a new defective column is removed from the verification determination target as described above, it is preferable to reduce the number of allowable failures accordingly. Thereby, the time for counting the number of failures is shortened, and the total data writing time can be shortened.

  There is also a method for effectively shortening the writing time without newly writing the separated data for the newly found defective column. FIG. 14 shows a write control sequence using such a method.

  By inputting a predetermined command, write control is started. Following the command, an address is input (step S11), and then write data is loaded (step S12). The process up to this point is the same as that in the previous writing, and the writing operation is automatically performed under the control of the controller 10 below.

  Here, verify determination (pass / fail determination) is performed based on the verify read data of the previous cycle in the background of the write step S13. Specifically, in order to apply the write voltage, it takes time to charge the write-inhibited bit line and the non-selected bit line. Pass / fail judgment is performed within the preparation period for applying the write voltage. If the “pass” determination is made, the writing is terminated without applying the writing voltage.

  However, in the first write cycle, the sense amplifier circuit holds the write data itself, not the verify read data of the previous cycle. Based on this, the pass / fail judgment is performed. "Fail". In the case of “fail”, verify read is performed after the write voltage is applied (step S14).

  Next, it is determined whether or not the number N of write cycles has reached the maximum value Nmax (step S15). If it has not reached the maximum value, the write voltage is stepped up (step S16) and writing is performed again (step S16). Step S13). When the number of write cycles reaches the maximum value Nmax, the number of failures is counted (step S17), and the write is terminated.

  In the pass / file determination in the writing step S13, if there is no newly found defective column, “fail” is output due to insufficient writing of 1 bit. When a defective column is found, the pass / fail judgment circuit 13 sets the number of defective columns as the allowable number of failures. For example, if the number of defective columns is 4, the path / file determination is performed under the condition of the selection signal (B2, B1, B0) = (1, 0, 0). As described with reference to FIG. 8, under this condition, VOUT = “H” (fail) only when the number of failures is 5 or more.

  This pass / fail judgment for accepting a defective column takes time compared to that for not permitting a defective column (that is, if there is at least one fail). However, by making this determination in the background of the writing step, the writing time can be shortened as a whole.

  Note that the data of the allowable number of failures is held in, for example, the parameter register 8 and the pass / fail judgment control is performed thereby. When a defect is found after shipment and the allowable fail number is changed, a specific command is input to rewrite the allowable fail number data held in the parameter register 8.

  Also in step S17 for counting the number of failures, it is preferable to increase the number of allowable failures more than usual in accordance with the number of newly found column defects.

  Up to this point, the data writing has been described exclusively. However, the present invention can also provide an effect for erasing data. Data erasure is usually performed in units of blocks, and application of an erase voltage and erase verification are repeated. The erase verify read is different in the bias conditions from the write, but the basic method is the same, and is performed by detecting the charge or discharge state of the bit line by the sense amplifier circuit. Therefore, the above-mentioned pass / fail detection circuit 13 can determine the erase verify. In this case, the write completion detection circuit 31 functions as an erase completion detection circuit.

  When a bit line open or short failure occurs, the “pass” determination cannot be obtained, and the erase cycle is repeated up to the set maximum value, resulting in a long erase time. This is the same as the case of writing. Therefore, the erasure time can be shortened by writing defective column separation data for defects that occur after shipment.

It is a figure which shows the functional block structure of the flash memory by embodiment of this invention. It is a figure which shows the structure of the memory cell array of the flash memory. FIG. 5 is a diagram illustrating an arrangement example of sense amplifiers sharing a bit line. 2 is a diagram showing a configuration of a sense amplifier circuit of the flash memory. FIG. It is a figure which shows the example of a detection line arrangement | positioning for the verify determination connected to a sense amplifier circuit. It is a figure which shows the structure of the pass / failure detection circuit of the flash memory. It is a figure which shows the structure of the write completion detection circuit of the same pass / failure detection circuit. It is a figure for demonstrating the failure detection principle of the same pass / failure detection circuit. It is a figure which shows the write-in sequence of the flash memory. It is a figure for demonstrating the bit-line defect detection method of the flash memory. It is a figure which shows the operation | movement waveform for detecting a bit line open defect. It is a figure which shows the operation | movement waveform for detecting a bit line short defect. It is a figure which shows the flow of defective column isolation | separation data writing. It is a figure which shows another write sequence.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Sense amplifier circuit, 3 ... Row decoder, 4 ... Column decoder, 5 ... Address register, 6 ... Input / output buffer, 7 ... Address coincidence detection circuit, 8 ... Parameter register, 9 ... Internal voltage generation circuit DESCRIPTION OF SYMBOLS 10 ... Controller, 11 ... Power-on reset circuit, 12 ... Status register, 13 ... Pass / fail detection circuit, 31 ... Write completion detection circuit, 32 ... Permissible fail number setting circuit, 32a-32d ... Current source circuit, 33 ... Current mirror circuit, 35 ... voltage detection node, 37 ... output circuit, 35 ... defective column separation data latch, 36 ... current source circuit, COMi ... first detection line, LSEN ... second detection line.

Claims (5)

A memory cell array having electrically rewritable nonvolatile memory cells;
A sense amplifier circuit for reading data from the memory cell array;
A pass / fail detection circuit for detecting write or erase completion based on verify read data held by the sense amplifier circuit at the time of writing or erasing;
The non-volatile semiconductor memory device, wherein the pass / fail detection circuit has a data latch configured to be able to write defective column separation data in accordance with a command input. A memory cell array having electrically rewritable nonvolatile memory cells;
A sense amplifier circuit for reading data from the memory cell array;
A pass / fail detection circuit for detecting write or erase completion based on verify read data held by the sense amplifier circuit at the time of writing or erasing;
The pass / fail detection circuit includes:
A plurality of first detection lines that are arranged for each column in the sense amplifier circuit and that undergo a level transition at the time of pass / fail judgment;
A plurality of completion detection circuits configured to flow a predetermined current in response to level transition of each first detection line, for detecting completion of writing or erasing;
A second detection line connected in common to the outputs of the completion detection circuits, and through which a total current of the currents of the completion detection circuits flows,
An allowable fail number setting circuit provided with a plurality of current source circuits capable of setting a reference current according to the allowable fail number;
A comparison circuit that compares the current flowing through the second detection line with the reference current set by the allowable fail number setting circuit and outputs a pass / fail signal;
A non-volatile semiconductor memory device comprising: a data latch connected to each of the completion detection circuits and configured to be writable in accordance with a command input in order to hold defective column separation data. 3. A defective bit line detection mode in which a bit line of the memory cell array is charged / discharged in accordance with a command input and the sense amplifier circuit detects an open or short of the bit line. The nonvolatile semiconductor memory device described. A memory cell array having electrically rewritable nonvolatile memory cells;
A sense amplifier circuit for reading data from the memory cell array;
A pass / fail detection circuit for detecting completion of writing or erasing based on verify read data held by the sense amplifier circuit at the time of writing or erasing;
A controller that performs write sequence control that repeats write and write verify, and performs a verify determination operation by the pass / fail detection circuit in a write step;
A non-volatile semiconductor memory device comprising: In accordance with a command input, the memory cell array has a defective bit line detection mode in which the bit line of the memory cell array is charged and discharged, and the sense amplifier circuit detects an open or short of the bit line. 5. The nonvolatile semiconductor memory device according to claim 4, wherein an allowable number of failures in the detection circuit is set.

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