JP2006078935A - Address electrode driving circuit of plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an address driving circuit of a plasma display device capable of making the transition time of an address signal nearly constant without being influenced by the direction of change of an adjacent address signal to prevent a pixel from erroneous lighting and electromagnetic radiation from being caused. <P>SOLUTION: The change of the adjacent address signal generated corresponding to a display data signal is detected and the ON resistance of a transistor of a pre-buffer constituting an output driver circuit is varied according to presence of the adjacent address signal change to control the change speed (the through rate of an output stage) of an output signal so that the transmission time becomes nearly constant. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a technique effective when applied to a driving circuit of a plasma display apparatus, and more particularly to a technique effective when used for an address electrode driving circuit for driving an address line (address electrode) orthogonal to a scanning line of the plasma display apparatus. .

  Plasma display panels (hereinafter referred to as “PDP”) are suitable for flat displays because they are thin and have a wider viewing angle than liquid crystal displays, and are attracting attention as potential candidates for next-generation large-sized televisions. ing. There are two types of PDP: an AC type PDP that emits light with an AC voltage and a DC type PDP that emits light with a DC voltage. Both of them are basically a conductive layer or an insulating layer serving as an electrode on two glass substrates. Various layers are made and pasted together, and a gas such as Ne that generates ultraviolet rays by discharge is sealed inside. Among them, the DC type PDP has ribs (partition walls) for forming discharge cells. The AC type PDP has a simpler structure because the ribs are striped, whereas the AC type PDP has a simpler structure.

  In addition, the AC type PDP is selected by using a counter discharge type in which sustain discharge and selective discharge are performed with two opposing electrodes, and a third electrode in which sustain discharge is performed between two electrodes in the same plane. There are surface discharge types that perform discharge. In the counter discharge type PDP, discharge occurs only between the two electrodes facing each other, so that there is a concern that the phosphor provided on one electrode via the dielectric layer is subjected to a large impact and is likely to deteriorate. On the other hand, the surface discharge type PDP is promising as a flat display in the future because it has a drawback that the number of electrodes is large but does not have a disadvantage that the phosphor is easily deteriorated.

Here, a schematic configuration of the display panel of the surface discharge type PDP will be briefly described with reference to FIG. Note that the display panel shown in FIG. 1 is an example of a reflective display panel having excellent luminance characteristics.
On the front substrate 11, X electrodes 12x and Y electrodes 12y for sustain discharge are alternately arranged in parallel in a stripe shape. These electrodes 12x and 12y are transparent electrodes made of ITO, Cr, A bus electrode made of Cu or the like is used. Further, the electrodes 12x and 12y are covered with a transparent dielectric layer 13 made of glass or the like, and a protective film 14 made of MgO or the like is formed on the discharge surface.

  On the other hand, an address line (data electrode, address electrode) 16 for selective discharge is disposed on the rear substrate 15 in a direction orthogonal to the electrodes 12x and 12y. Further, the address lines 16 are covered with a white dielectric layer 17, and partition walls (ribs) 18 are formed in stripes along the address lines 16. Inside the partition wall 18, fluorescent layers 19a, 19b, and 19c of three colors of R (red), G (green), and B (blue) are regularly arranged for visible light emission and colorization. Has been.

  The front substrate 11 and the rear substrate 15 on which various conductive layers and insulating films are formed are bonded by a seal layer (not shown) formed around the substrate so that the partition wall 18 and the protective film 14 are in close contact with each other. . Also, a space for sandwiching the two substrates is filled with a gas for generating ultraviolet rays when a discharge occurs.

A PDP display panel 10 having the above configuration, an address driver for applying a voltage for driving the address line 17 of the display panel, a scan driver for applying a voltage for driving the X and Y electrodes 12 and 13 of the display panel, An AC type PDP is configured by a sustain driver and a control circuit that generate a voltage for sustain discharge, and a voltage is applied between the X electrode 12 and the address line 16 by the address driver and scan driver to perform selective discharge. The sustain driver performs a sustain discharge by applying a voltage between the X and Y electrodes 12 and 13 by the sustain driver, thereby performing light emission display on the display panel 10. As an invention relating to a plasma display drive circuit, for example, there is an invention described in Patent Document 1.
JP 2001-318647 A

  As shown in FIG. 2, main loads of the address driver in the AC type PDP are a coupling capacitor (hereinafter referred to as a sustain capacitor) Cs between the sustain electrode and the scan electrode, and an address signal for driving an adjacent pin. A capacitance between the wirings (hereinafter referred to as an adjacent pin capacitance) Cp. Of these load capacitors, the sustain capacitor Cs is almost constant, but the adjacent pin capacitor Cp is invisible when the adjacent address signal changes in the same direction as itself. That is, the load of the address driver varies according to the change of the adjacent address signal.

  Here, when the adjacent address signal changes in the opposite direction, the amount of change is doubled and the load appears to be larger, but by shifting the timing between when the address signal rises and when it falls , Such an increase in load can be avoided. Therefore, the load on the address driver in the case of such timing control is small when the adjacent address signal changes in the same direction as itself, and when the adjacent address signal does not change (including when the adjacent address signal changes in the opposite direction). Will grow. Moreover, in the PDP, the adjacent pin capacitance when the adjacent address signals do not change reaches almost the same size as the sustain capacitance.

  By the way, in the evaluation of the PDP, there are a black and white display mode in which white and black are alternately displayed every several lines, and a staggered display mode in which the display is inverted between adjacent dots. In the monochrome display mode, all the bits change in the same direction, that is, adjacent address signals change in the same direction, so that the load is the smallest. In the staggered display mode, the adjacent address signals change in opposite directions, so the load becomes the largest. When the load of the address driver fluctuates in this way, as shown in FIG. 3, the address output rises or falls steeply in the monochrome display mode and rises or falls gently in the staggered display mode, whereby the address signal transition time. Also changes. FIG. 4 shows the relationship between the load magnitude and the address signal transition time in a PDP using a conventional address driver.

  As a result of examination by the present inventors, when the load of the address driver in the monochrome display mode is about 20 pF and the address transition time is about 20 ns (nanosecond), the load of the address driver in the staggered display mode is about 50 pF. It was found that the transition time is about 45 ns, which is about twice as long. Here, if the address transition time is long, there is a possibility that a pixel to be lit does not illuminate or a pixel that should not be lit is lit. A design is made to increase the driving force of the address driver so that the time falls within a predetermined time.

  However, in the PDP using the address driver having such a large driving force, there is a problem that electromagnetic radiation is generated from the address line because the change of the address signal is too steep in the monochrome display mode. In order to prevent such a problem, some conventional PDPs take measures such as putting a transparent electromagnetic wave shielding film on the surface of the panel. However, when such measures are taken, another problem of increasing the cost of the PDP occurs.

The present invention has been made to solve the above-described problems, and the transition time of the address signal can be made substantially constant without being affected by the direction of change of the adjacent address signal, whereby the pixel of the pixel is changed. An object of the present invention is to provide an address driving circuit for a plasma display device that can prevent erroneous lighting and generation of electromagnetic radiation.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Outlines of representative ones of the inventions disclosed in the present application will be described as follows.
That is, a change in the adjacent address signal formed according to the display data signal is detected, and the on-resistance of the transistors constituting the output driver circuit is changed in accordance with the direction of the change in the adjacent address signal so that the transition time is substantially constant. Thus, the change rate of the output signal (the slew rate of the output stage) is controlled.

  According to the above-described means, the transition time of the address signal can be made substantially constant even if the load size of the output driver circuit varies depending on the direction of change of the adjacent address signal. It is possible to prevent the occurrence of erroneous lighting due to being too loose or the generation of electromagnetic radiation from the address line due to the change of the address signal being too steep.

  Here, the transistor whose on-resistance is changed in accordance with the direction of change of the adjacent address signal is preferably a transistor constituting a prebuffer of the output driver circuit. The transistor that changes the on-resistance according to the direction of change of the adjacent address signal can be a transistor that constitutes the final output stage in addition to the pre-buffer, but the load of the final output stage is the PDP panel to be used However, since the load of the transistor constituting the pre-buffer does not change depending on the use of the PDP panel to be used, more stable characteristics can be obtained.

  Desirably, the rising timing of the address signal is shifted from the falling timing of the address signal. If the address signal rises and falls at the same time, the adjacent pin capacitance becomes twice that when one signal does not change when the direction of change between adjacent address signals is opposite. If the falling timing is shifted, the apparent adjacent pin capacitance can be reduced. Accordingly, the variable range of the on-resistance of the transistors constituting the output driver circuit, that is, the variable range of the driving power of the driver circuit can be reduced, and an increase in circuit scale can be suppressed.

  Further, when the address driver is composed of a plurality of driver semiconductor integrated circuits, similar signals from the external terminal and other driver semiconductor integrated circuits for outputting signals indicating the direction of change of the leading address signal and the final address signal. An external terminal for inputting the address is provided, or a dummy address latch circuit and a circuit for detecting the change direction of the address signal are provided.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
That is, in the plasma display device, the transition time of the address signal can be made almost constant without being influenced by the direction of change of the adjacent address signal, thereby preventing erroneous lighting of the pixel and generation of electromagnetic radiation. An address driving circuit can be realized. In addition, it is possible to realize a plasma display device capable of displaying a good image quality with little unevenness.

Preferred embodiments of the present invention will be described below with reference to the drawings.
FIG. 5 is a block diagram showing a schematic configuration of a display device using an AC type PDP as an example of a plasma display device effective by applying the address driving circuit according to the present invention. Although the plasma display device of FIG. 5 uses a three-electrode surface discharge type PDP, the address driving circuit according to the present invention can be applied to either a three-electrode surface discharge type or a counter discharge type PDP. is there.

  The plasma display device of FIG. 5 drives a display panel 10, a digital signal processing circuit 20, a power supply circuit 30, a scanning driver 40 that scans and drives an X electrode, a sustain driver 50 that drives a Y electrode, and an address line. The address driver 60 is configured. The display panel 10 uses an AC type PDP having the same configuration as that shown in FIG.

  The digital signal processing control circuit 20 generates and supplies control pulses to the drivers 40 to 60 based on the signals such as the clock CLK, the display data DATA, the vertical synchronization signal VSYNC, and the horizontal synchronization signal HSYNC. Based on the control pulse from the digital signal processing control circuit 20, the scanning driver 40 and the address driver 60 determine where to emit light in each pixel on the display panel 10 and where not to emit light, and generate corresponding drive voltages. Output.

  Specifically, the scanning driver 40 outputs a voltage for sequentially driving the X electrodes provided on the front substrate to the selection level, and the address driver 60 selects the address line on the rear substrate at the selection level or not according to the display data. A voltage for driving to a level is output, and a voltage of a selection level is applied to an address line corresponding to a pixel to emit light. As a result, a discharge is performed between the selected electrodes, and only the selected pixels emit light once.

  Based on the control pulse from the digital signal processing control circuit 20, the sustain driver 50 applies a continuous voltage pulse having a phase opposite to that of the X electrode to the Y electrode of the front substrate, thereby causing a sustain discharge between the X and Y electrodes. Let Due to the sustain discharge, only the pixels that have previously selectively emitted light once are discharged and light emission is displayed on the display panel 10.

  FIG. 6 is a block diagram of an embodiment of the address driving circuit according to the present invention. The address drive circuit (address driver) of this embodiment receives a digital display data signal input from the digital signal processing control circuit 20 and applies a high voltage output to the address line so that a discharge occurs between the X and Y electrodes. A shift register 61 that generates and outputs a pulse, converts input serial display data into parallel data, a latch unit 62 that holds the converted display data, and a level shift unit 63 that converts a signal level, The driver unit 64 outputs voltage pulses applied to the address lines, the control unit 65 generates control signals for the shift registers 61 to 64, and the like.

  The control unit 65 sequentially fetches the serial display data DATA1 to DATAn in synchronization with the system clock signal CLK, and transfers them from the shift register 61 to the latch unit 62 in synchronization with the latch signal LAT from the digital signal processing control circuit 20. Let The address driver 60 includes a power supply terminal VDD1 to which a power supply voltage such as 5V supplied to the shift register 61, the latch unit 62, and the control unit 65 is applied, and a high power supply such as 80V supplied to the driver unit 64. A power supply terminal VDD2 to which a voltage is applied and a power supply terminal GND to which a ground potential is applied are provided.

FIG. 7 shows a detailed configuration example of the unit drive circuit including the shift register 61 to the driver unit 64 corresponding to each address output terminal in the address driver 60 of the present embodiment.
In FIG. 7, 66 is a delay circuit for delaying the latch signal LAT, F / F0 is a flip-flop constituting the shift register 61, and F / F1 synchronizes display data shifted by the shift register 61 with the latch signal LAT. F / F2 latches the data latched in the first latch F / F1 in synchronization with the delay signal LAT1 of the latch signal LAT, and 67 denotes the first latch F / F1. 2 is a rising / falling detection circuit for detecting whether the next data rises or falls based on the data latched by the two latches F / F2. In FIG. 7, the unit level shifter constituting the level shift unit 63 of FIG. 6 and the unit output driver constituting the driver unit 64 are shown as one block 68.

  In this embodiment, the rising / falling detection circuit 67 includes an exclusive OR gate G1 that obtains an exclusive OR of the output of the first latch F / F1 and the output of the second latch F / F2, and the gate G1. A NAND gate G2 that takes a logical product of the output and a signal obtained by inverting the output of the first latch F / F1 by the inverter INV1, and a NAND gate G3 that takes a logical product of the output of the gate G1 and the output of the first latch F / F1 It consists of and. The exclusive OR gate G1 outputs a low level when the two input signals match, and outputs a high level when the two input signals do not match.

  For this reason, the NAND gate G2 receiving this signal changes its data from the high level to the low level when the first latch F / F1 receives the low level data and the second latch F / F2 receives the high level data. Is detected, the output changes to a low level. On the other hand, when the NAND gate G3 detects high level data in the first latch F / F1 and low level data in the second latch F / F2, that is, detects that the data changes from the low level to the high level. , The output changes to low level. The outputs UP and DOWN of the NAND gates G2 and G3 are supplied to the level shifter & driver 68 of the adjacent terminals via the signal lines L1 and L2, respectively. Further, the detection signals UP and DOWN from the rising / falling detection circuit 67 of the adjacent terminal are input to the level shifter & driver 68 of the terminal via signal lines L3 and L4; L5 and L6.

  FIG. 8 shows a pre-buffer 682 for driving the final output stage 681 and the gate of the low-side output MOS transistor in the unit output driver 68 of FIG. 7 and a control circuit for generating a gate control signal for the pre-buffer (hereinafter referred to as a gate). A specific circuit example of 683 (referred to as a control circuit) is shown.

  As shown in FIG. 8, the pre-buffer 682 has a P-channel MOS transistor M1 connected in series between the power supply voltage VDD1 and the ground point, and a P-channel connected in parallel with the N-channel MOS transistors M4 and M1. It consists of channel MOS transistors M2 and M3. The final output stage 681 includes a P-channel MOS transistor M9 and an N-channel MOS transistor M10 connected in series between the power supply voltage VDD2 and the ground point, and operates as an inverter. Among these transistors, the MOS transistors M1 to M4 constituting the prebuffer are low breakdown voltage transistors, and the MOS transistors M9 and M10 constituting the output stage are high breakdown voltage transistors. Further, in the MOS transistors M1, M2, and M3, the element size ratio (gate width ratio) M1: M2: M3 is set to 2: 1: 1, for example, and the load resistance value for the N-channel MOS transistor M4 is set. Is configured to change according to the ON or OFF state of M1, M2, and M3.

  The gate control circuit 683 is a NAND gate that receives the output INN of the first latch F / F1 and the detection signal DOWN_L from the rising / falling detection circuit 67 of the adjacent bit on the left as one input signal of the driver. NAND gate G5 that receives G4 and the output INN of the first latch F / F1 and the detection signal DOWN_R from the rising / falling detection circuit 67 of the right adjacent bit, and the output INN of the first latch F / F1 are inverted. And an inverter INV2. A signal obtained by inverting the output INN of the first latch F / F1 by the inverter INV2 is applied to the gate terminals of the transistors M1 and M4 of the prebuffer 682, and the output of the NAND gate G4 is applied to the gate terminal of the transistor M2. The output of the NAND gate G5 is applied to the gate terminal of the transistor M3.

  Next, operations of the gate control circuit 683 and the pre-buffer 682 on the row side of the driver circuit of this embodiment will be described. Table 1 shows the magnitude relationship between the input signals INN, DOWN_L, and DOWN_R of the driver circuit of FIG. 8, the on / off states of the MOS transistors M1 to M4 and M10, and the on resistance RON of M1 to M3. The on-resistance RON is infinite when all of M1 to M3 are off, is the smallest when all of M1 to M3 are on, and increases in the order when only M1 is on when M1 and M2 or M3 are on. FIG. 9 shows the relationship between the load capacitance of the driver circuit and the fall time Tf when the transistor M10 is turned on and the output falls.

  In Table 1, “H” indicates that the signal is at a high level, “L” indicates that the signal is at a low level, and when DOWN_L and DOWN_R are “H”, each adjacent bit does not fall. When DOWN_L and DOWN_R are “L”, it means that the adjacent bits fall. Here, since FIG. 8 and Table 1 focus on the gate drive circuit of the output MOS transistor M10 on the low side of the final output stage 681 and its operation, M10 is turned on when the input signal INN is set to “H”. When the output falls, if both the left and right adjacent bits fall, the load capacity is the smallest, and if both the left and right adjacent bits do not fall, the load capacity is the largest, and one of the left and right adjacent bits When falls, the load capacity becomes an intermediate size.

  In the driver circuit of FIG. 8, when both the left and right adjacent bits fall when the output MOS transistor M10 is turned on by the input signal INN being set to "H" and the output falls, both DOWN_L and DOWN_R are set. Since it is “L”, only M1 of the MOS transistors M1 to M3 of the pre-buffer 862 is turned on. Then, the fall time Tf of the driver circuit when only M1 is turned on is indicated by the characteristic line A connecting the X marks plotted in FIG. On the other hand, when both the left and right adjacent bits fall, the load capacitance CL is the smallest. For example, if the sustain capacitance is 20 pF, the load capacitance CL is 20 pF, and the fall time Tf is a value such as 50 ns.

  Next, when the output MOS transistor M10 is turned on and the output falls, both the left and right adjacent bits do not fall. That is, if the reverse movement occurs, both DOWN_L and DOWN_R are "H". MOS transistors M1 to M3 are all turned on. Then, the fall time Tf of the driver circuit when all of M1 to M3 are turned on is indicated by a characteristic line B connecting the ♦ marks plotted in FIG. On the other hand, the load capacitance CL when the left and right adjacent bits move in the opposite direction is the largest. For example, if the adjacent pin capacitance on one side is 10 pF, the load capacitance CL combined with the sustain capacitance (20 pF) is 40 pF. It can be seen from the characteristic line B that the fall time Tf is a value such as 50 ns.

  Further, when either the left or right adjacent bit falls when the output MOS transistor M10 is turned on and the output falls, one of DOWN_L and DOWN_R becomes "L" and the other becomes "H", so the prebuffer 862 Of the MOS transistors M1 to M3, M1 and M2 or M3 are turned on. Then, the fall time Tf of the driver circuit when M1 and M2 or M3 are turned on is indicated by a characteristic line C connecting the marks (1) plotted in FIG. The load capacitance CL when either the left or right adjacent bit falls is an intermediate value between when both fall and when both fall, ie, the sustain capacitance (20 pF) and the adjacent pin capacitance on one side are 10 pF. The combined load capacitance CL is 30 pF, and it can be seen from the characteristic line C that the fall time Tf is a value such as 50 ns.

  From FIG. 9, when the pre-buffer 862 is composed of inverters of MOS transistors M1 and M4, the fall time Tf differs by ΔT0 (about 20 ns) when the load capacitance CL is 20 pF and 40 pF. When the pre-buffer 682 of FIG. 8 having M2 and M3 of FIG. 8 is used, the fall time Tf can be made substantially constant even if the load capacitance CL differs depending on how the adjacent pin signals change. I understand that I can do it.

  FIG. 10 shows a pre-buffer 684 for driving the final output stage 681 and the gate of the high-side output MOS transistor in the unit output driver 68 of FIG. 7 including the level shifter, and a gate control circuit for generating a gate control signal for the pre-buffer. A specific circuit example of 685 and the level shift circuit 686 is shown.

  As shown in FIG. 10, the pre-buffer 684 has an N channel connected in parallel with a P channel MOS transistor M14 and N channel MOS transistors M11 and M11 connected in series between the power supply voltage VDD2 and the ground point. It is composed of channel MOS transistors M12 and M13 and operates as a NAND gate. Level shift circuit 686 includes an inverter including P channel MOS transistor M5 and N channel MOS transistor M6, a P channel MOS transistor M7, and an N channel MOS transistor M8 connected in series between power supply voltage VDD2 and the ground point. It is composed of a differential circuit in which the output terminal of the inverter and the gate terminal of the P-MOS are cross-coupled, and outputs a signal obtained by level shifting the input signal INP.

  The MOS transistors M11 to M14 and M5 to M8 constituting the prebuffer 684 and the level shift circuit 686 are high breakdown voltage transistors. Further, in the MOS transistors M11, M12, and M13, the element size ratio (gate width ratio) M1: M2: M3 is set to 2: 1: 1, for example, and the value of the load resistance for the P-channel MOS transistor M14 Is configured to change according to the on or off state of M11, M12, and M13.

  The gate control circuit 685 includes an inverter INV3 that inverts the detection signal UP_L from the rising / falling detection circuit 67 of the left adjacent bit, and the first latch F / that is the output of the inverter and the other input signal of the driver. An AND gate G6 that receives a signal INP in phase with the output of F1, an inverter INV4 that inverts the detection signal UP_R from the rising / falling detection circuit 67 of the adjacent bit on the right side, the output of the inverter, and the other of the driver An AND gate G7 that receives a signal INP in phase with the output of the first latch F / F1, which is an input signal, is provided. The signal INP having the same phase as the output of the first latch F / F1 is applied to the gate terminal of M11 among the transistors of the prebuffer 684, the output of the AND gate G6 is applied to the gate terminal of the transistor M12, and the transistor M13. The output of the AND gate G7 is applied to the gate terminal, and the output of the level shift circuit 686 is applied to the gate terminal of the transistor M14.

  The operations of the high-side gate control circuit 685 and the pre-buffer 684 in this embodiment are almost the same as the operations of the low-side gate control circuit 683 and the pre-buffer 682 in FIG. Description is omitted. When the pre-buffer 684 of the embodiment of FIG. 10 is used, the rise time Tr can be made substantially constant even if the load capacitance CL differs depending on how the adjacent pin signals change.

  Next, a modification of the driver circuit 68 of the above embodiment will be described with reference to FIG. In the modification (type A) of FIG. 11, M3 is omitted from the P-channel MOS transistors M1 to M3 of the pre-buffer 682 in FIG. 8, and the logical product of the rising / falling detection signals DOWN_L and DOWN_R of adjacent bits is taken. An AND gate G8 is provided, and the output of the gate G8 and one input signal INN of the driver are input to the NAND gate G4, and the output controls the on / off of the P-channel MOS transistor M2 of the prebuffer 682. Is. Although not shown, the same change is made to the pre-buffer 684 and the gate control circuit 685 of the high-side output transistor M9. In FIG. 11, a modification (type B) in which an OR gate is used instead of the AND gate G8 is also conceivable.

  FIG. 12 shows the relationship between the load capacitance CL and the signal fall time Tf when the above modification is applied. In an address driving circuit using a type A driver circuit, when the address signal of the adjacent bit falls when the address signal of the bit of interest falls, only M1 of the MOS transistors M1 and M2 is turned on. However, at this time, since the load capacitance CL is only the sustain capacitance and is small, the signal fall time Tf is relatively short. On the other hand, when the address signal of the adjacent bit does not change, both the MOS transistors M1 and M2 are turned on. At this time, the load capacitance CL is a sum of the sustain capacitance and the two adjacent pin capacitances and is relatively large. Therefore, the sizes of the MOS transistors M1 and M2 are set so that the falling time Tf is substantially the same as when both address signals of adjacent bits fall.

  In the address driving circuit using the type A driver circuit, when one of the address signals of the adjacent bits falls when the address signal of the bit of interest falls, the MOS transistor is the same as when both fall. Only M1 out of M1 and M2 is turned on. At this time, the load capacitance CL is a sum of the sustain capacitance and one adjacent pin capacitance, and is slightly large, so that the signal fall time Tf is increased by ΔT1. However, since this time ΔT1 is about ½ of the time difference ΔT0 when the transistor M2 is not provided, the change in the fall time Tf can be reduced.

  In an address driving circuit using a type B driver circuit, when one of the adjacent bit address signals falls when the address signal of the bit of interest falls, the MOS transistors M1, M1 and M2 are not changed. Both M2 are turned on, but at this time, the load capacitance CL is slightly smaller than the sum of the sustain capacitance and one adjacent pin capacitance and does not change, so the signal fall time Tf is shortened by ΔT2. However, since the time ΔT2 is about ½ of the time difference ΔT0 when the transistor M2 is not provided, the change in the fall time Tf can be reduced.

FIG. 13 shows another embodiment of the address driving circuit according to the present invention.
In general, a plurality of address driving circuits (IC) 60 are used to drive the address lines 16 of one PDP panel 10. At this time, each address driving circuit (IC) 60 has a predetermined range. This is used to drive the adjacent address lines 16. Display data for driving the adjacent address lines 16 in the predetermined range is supplied in parallel for each data amount to be sent to each address driving circuit (IC) 60. When the first address driving circuit (IC) 60 receives display data for driving the first address driving circuit (IC) 60 for one frame period, one of the first address driving circuit (IC) 60 and the first address driving circuit (IC) 60 is adjacent. The display data supplied to the address line 16 driven by the first address drive circuit (IC) 60 adjacent to the address line 16 driven by the matched address drive circuit (IC) 60 is the first bit in this specification. The address line driven by the first address drive circuit adjacent to the address line 16 driven by the address drive circuit (IC) 60 adjacent to the first address drive circuit (IC) 60 and the other address drive circuit. The display data supplied to 16 is referred to herein as the last bit.

  The address drive circuit (IC) 60 of this embodiment includes terminals P1 and P2 for outputting detection signals UP1 and DOWN1 of the rising / falling detection circuit provided in the driver circuit of the first bit to the outside of the chip, Terminals P3 and P4 for outputting detection signals UP2 and DOWN2 of the rising / falling detection circuit provided in the final bit driver circuit to the outside of the chip, and a driver of the first bit of another address driving circuit (IC) Terminals P5 and P6 for receiving detection signals UP1 and DOWN1 output from the rising / falling detection circuit provided in the circuit as the right adjacent bit rising / falling detection signals UP-R and DOWN_R, and other addresses Detection signals UP2 and DOWN2 output to the outside of the chip from the rising / falling detection circuit provided in the driver circuit of the last bit of the drive circuit (IC) Left adjacent bit rise / fall detection signal UP-L, is provided with a and terminal P7, P8 receive as DOWN_L.

  In a PDP display device using a plurality of address drive circuits (ICs) having no external terminals P1 to P8, the leading and trailing bit driver circuits each detect rise / fall from one adjacent bit driver circuit. Since there is no signal, the address signal cannot be changed at a desired speed. However, in a PDP display device using a plurality of address driving circuits (ICs) to which this embodiment is applied, the address signal is changed at an optimum speed. Accordingly, it is possible to prevent the display image quality from being deteriorated or electromagnetic waves are radiated from the address lines depending on the display mode.

FIG. 14 shows still another embodiment of the address driving circuit according to the present invention.
The address drive circuit (IC) 60 of this embodiment is a dummy flip-flop that constitutes a shift register 61 that shifts display data for driving an address line adjacent to the first bit driver circuit and the last bit driver circuit. DFF1 and DFF2 and dummy latches (corresponding to F / F1 and F / F2 in FIG. 7) DLT1 and DLT2 for latching data shifted by the shift register 61, and signals based on the data fetched into these latches Are provided with dummy rising / falling detection circuits DTC1 and DTC2 for detecting whether the signal rises or falls.

  In the PDP display device using the address drive circuit (IC) 60 of this embodiment, the system control circuit 20 (see FIG. 5) has a first bit driver circuit and a last bit driver of the adjacent address drive circuit (IC) 60. Since the display data to be supplied to the circuit needs to be added and supplied to the shift register 61, there is a demerit that the burden on the control circuit increases, but the address drive circuit (IC) 60 of the embodiment of FIG. The address signal can be changed at an optimum speed without increasing the number of external terminals, thereby preventing the display image quality from being deteriorated or electromagnetic waves being emitted from the address lines depending on the display mode. There is an advantage of becoming.

  The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Nor. For example, in the above embodiment, the driver circuit is constituted by a MOS transistor, but it may be constituted by a bipolar transistor. In the above embodiment, the final output stage of the driver circuit is composed of a P-channel MOS transistor and an N-channel MOS transistor, but it may be an output stage in which two N-channel MOS transistors are connected in series.

  In the above description, the case where the invention made mainly by the present inventor is applied to the address drive circuit of the surface discharge type PDP which is the field of use as the background has been described, but the present invention is not limited thereto. It can be used for an address drive circuit of a counter discharge type PDP.

It is a perspective view which shows schematic structure of the display panel of surface discharge type PDP. FIG. 3 is an equivalent circuit diagram showing a state of a load connected to an address driver that drives an address line of a PDP. It is a wave form diagram which shows the change of the output of the address driver which drives the address line of PDP. It is a graph which shows the relationship between the load capacity of the address driver which drives the address line of PDP, and transition time. 1 is a block diagram showing a schematic configuration of a plasma display device effective by applying a PDP address driving semiconductor integrated circuit according to the present invention. FIG. It is a block diagram which shows schematic structure of one Example of the semiconductor collection for address drive of PDP which concerns on this invention. It is a logic block diagram which shows the Example of the drive circuit corresponding to one terminal provided in the semiconductor integrated circuit for address drive of PDP which concerns on this invention. FIG. 8 is a circuit diagram illustrating a specific circuit example of a row-side prebuffer and its control circuit of the unit output driver of FIG. 7. It is a graph which shows the relationship between the load capacity and output fall time in the unit output driver of FIG. FIG. 7 is a circuit diagram illustrating a specific circuit example of a high-side prebuffer, its control circuit, and a level shift circuit of the unit output driver of FIG. 6. FIG. 7 is a circuit diagram illustrating a specific circuit example of a row-side prebuffer and its control circuit of the unit output driver of FIG. 6. 12 is a graph showing a relationship between load capacity and output fall time in the unit output driver of FIG. 11. It is explanatory drawing which shows the other structural example of the semiconductor integrated circuit for address drive of PDP which concerns on this invention. It is a block diagram which shows the further another Example of the semiconductor integrated circuit for address drive of PDP which concerns on this invention.

Explanation of symbols

10 Display panel (PDP)
60 Address Driver 61 Shift Register 64 Driver Unit 67 Rise / Fall Detection Circuit 68 Unit Output Driver 681 Output Stage 682, 684 Pre-buffer 683, 685 Gate Control Circuit 686 Level Shift Circuit CR1-CR4 Time Constant Circuit

Claims (10)

A plurality of unit drive circuits for converting a display data signal having a predetermined amplitude into a high voltage pulse having an amplitude larger than the predetermined amplitude, and a plurality of unit drive circuits for outputting the high voltage pulses generated by the plurality of unit drive circuits, respectively. An address electrode driving semiconductor integrated circuit comprising an external terminal and generating and outputting a signal for driving an address line of a plasma display panel,
The plurality of unit drive circuits are:
Each of the unit drive circuits includes a detection circuit that detects whether the voltage pulse rises or falls based on input display data and outputs a detection signal, and the unit drive circuits are adjacent to each other. An address electrode driving semiconductor integrated circuit configured to control the speed at which the voltage pulse changes from high to low or from low to high based on the detection signal output from the detection circuit of the circuit. circuit. First detecting the voltage pulse rising or falling based on display data to be displayed on the address electrode driving semiconductor integrated circuit plasma display device adjacent to the address electrode driving semiconductor integrated circuit and outputting a detection signal A dummy detection circuit and a second dummy detection circuit;
Of the plurality of unit drive circuits, the first and last unit drive circuits each include the detection signal and the first dummy detection circuit output from the detection circuit of the unit drive circuit corresponding to one of the adjacent external terminals. Alternatively, based on the detection signal output from the second dummy detection circuit, the speed at which the voltage pulse changes from high to low or from low to high is controlled.
In the first dummy detection circuit, one of the display data supplied to the first address electrode driving semiconductor integrated circuit adjacent to the address electrode driving semiconductor integrated circuit is different from the address electrode driving semiconductor integrated circuit. The same data as the final data is supplied,
Of the display data supplied to the second address driving semiconductor integrated circuit, the other one of the second dummy detection circuits is different from the address electrode driving semiconductor integrated circuit and is adjacent to the address electrode driving semiconductor integrated circuit. 2. The address electrode driving semiconductor integrated circuit according to claim 1, wherein the same data as the head data is supplied. The unit drive circuit includes: an output stage including a first output transistor and a second output transistor connected in series between a first power supply voltage terminal and a second power supply voltage terminal; and the first output A first pre-buffer for driving the control terminal of the transistor, and a second pre-buffer for driving the control terminal of the second output transistor,
Of the transistors constituting the first pre-buffer or the second pre-buffer, the on-resistance of the load transistor is that of the unit driving circuit corresponding to the external terminal adjacent to the external terminal to be driven by the unit driving circuit. The speed of the voltage pulse changing from high to low or from low to high is controlled by being changed based on the detection signal output from the detection circuit. 2. A semiconductor integrated circuit for driving an address electrode according to 1.   The load transistor includes three transistors in parallel, and the number of transistors that are turned on among the three transistors corresponds to the external terminal adjacent to the external terminal to be driven by the unit drive circuit. Further, the voltage pulse is configured to control the speed at which the voltage pulse changes from high to low or from low to high by being changed based on the detection signal output from the detection circuit of the unit drive circuit. The semiconductor integrated circuit for driving an address electrode according to claim 3.   5. The semiconductor integrated circuit for driving an address electrode according to claim 4, wherein two of the three transistors in parallel form are formed to have the same size. The three transistors in the parallel form are turned on and off by an input signal corresponding to display data.
One of the two transistors having the same size among the three transistors in parallel form corresponds to an input signal corresponding to display data and one of the external terminals adjacent to the external terminal to be driven by the unit driving circuit. The unit drive circuit is turned on and off by a signal obtained by ANDing the detection signal output from the detection circuit of the unit drive circuit.
The other of the two transistors of the same size among the three transistors in the parallel configuration corresponds to an input signal corresponding to display data and the other external terminal adjacent to the external terminal to be driven by the unit driving circuit. 6. The address electrode drive according to claim 5, wherein an on / off operation is performed by a signal obtained by ANDing the detection signal output from the detection circuit of the unit drive circuit of the unit drive circuit. Semiconductor integrated circuit.   The load transistor is composed of two transistors in parallel, and a transistor that is turned on of the two transistors corresponds to the external terminal adjacent to the external terminal to be driven by the unit drive circuit. 4. The change rate of the output signal is controlled by being changed based on the detection signal output from the detection circuit of the unit drive circuit of the drive circuit. 2. A semiconductor integrated circuit for driving an address electrode according to 1. The logical unit or logical sum of the detection signals output from the detection circuit of the unit drive circuit of the unit drive circuit corresponding to the external terminal adjacent to the external terminal to be driven by the unit drive circuit is obtained. A logic gate circuit for generating
One of the two parallel transistors is turned on and off by an input signal corresponding to display data,
The other transistor of the two parallel transistors is turned on / off by a signal obtained by ANDing an input signal corresponding to display data and a detection signal output from the logic gate circuit. 8. The semiconductor integrated circuit for driving an address electrode according to claim 7. A first external terminal that outputs a detection signal output from a detection circuit of a unit drive circuit that receives a display data signal of the first bit among the plurality of unit drive circuits, and display data of the last bit among the plurality of unit drive circuits A second external terminal that outputs a detection signal output from the detection circuit of the unit drive circuit that receives the signal;
A third external terminal that receives a detection signal output from a first address driving semiconductor integrated circuit different from the address driving semiconductor integrated circuit and supplies the detection signal to the unit driving circuit that receives the display data signal of the first bit;
A fourth external terminal that receives a detection signal output from a second address driving semiconductor integrated circuit different from the address driving semiconductor integrated circuit and supplies the detection signal to the unit driving circuit that receives the display data signal of the last bit; The semiconductor integrated circuit for driving an address electrode according to claim 1. A plurality of unit drive circuits for converting a display data signal having a predetermined amplitude into a high voltage pulse having an amplitude larger than the predetermined amplitude, and a plurality of unit drive circuits for outputting the high voltage pulses generated by the plurality of unit drive circuits, respectively. Generate and output a signal that drives the address line of the plasma display panel with external terminals,
Each of the plurality of unit drive circuits includes a detection circuit that detects whether the voltage pulse rises or falls based on input display data and outputs a detection signal, and the unit drive circuit is connected to the adjacent external terminal. Address electrode driving semiconductor configured to control the speed at which the voltage pulse changes from high to low or from low to high based on the detection signal output from the detection circuit of the corresponding unit drive circuit An integrated circuit;
A plasma display device comprising the plasma display panel.

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