JP2006074917A - Parallel inverter power supply system and control method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable parallel and synchronous operation of multiple inverters without adding a special signal line for start-up or overloading at start-up. <P>SOLUTION: One inverter IV1 is started at a value lower than its rated voltage, for example, 100 V, which is a voltage threshold value used when many load devices detect power supply. After a certain time passes, its voltage output is interrupted. The timing edge of the voltage output interruption is grasped with voltage detectors respectively provided in all the inverters IV1 and IV2, and the phase basis of output voltage is reset to a predetermined value. After a certain time passes, all the inverters are started to their rated voltage of 440 V according to the phase basis of output voltage of each inverter. Thus, the inverters is parallel and synchronously operated without adding a special signal line for start-up or overloading at start-up. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a parallel inverter power supply system control method and a parallel inverter power supply system.

  Conventionally, only one inverter connected to a load system controls the output voltage and frequency, such as an uninterruptible power supply and an auxiliary power supply for vehicles. There is a demand to synchronize operation by connecting two or more units in parallel in order to increase capacity or provide redundancy in case of failure.

  However, in the conventional inverter control method, a plurality of inverters are connected in parallel as they are, and only started and stopped at the same time. Therefore, the AC phases of the two are not generally synchronized, resulting in a phase shift. Due to the excessive cross current between the inverters, there is a problem that the operation cannot be continued due to overcurrent protection and the loss is increased.

  A parallel inverter control method that exchanges and synchronizes instantaneous phase information between two inverters is known. If a system that executes the method is to be assembled, a signal line for information transmission is newly added. There is a problem that is necessary and causes an increase in cost.

  There is also known a parallel inverter control method in which the phase is synchronized without adding a new signal line by changing the output frequency in accordance with the inverter output active power. In this control method, if there is a phase difference between the two inverters, a cross current of the active power component is generated in the direction from which the phase has advanced, so the output frequency is set to decrease as the active power increases. Then, it is based on the principle that the phase of the inverter that is delayed in the other phase can catch up and synchronize.

As a method for starting parallel synchronous operation, Japanese Patent Laid-Open No. 11-215602 (Patent Document 1) first starts one inverter (1) of a plurality of inverters as shown in the timing chart of FIG. A method is described in which, after a voltage is output to the bus, a PLL synchronous parallel insertion is performed after matching the output voltage phase of the other inverter (2) based on the AC voltage phase of the bus voltage. However, there is a case where a rated load is connected to the output bus from the time of startup.In such a case, the inverter that has been started first is over a certain period of time until another inverter starts phase-synchronized operation in phase synchronization. It becomes necessary to carry out load operation. In a system with a large number of inverters in parallel, it is necessary to handle an overload corresponding to the number of parallel inverters with one inverter at the time of start-up, and in the worst case, start-up may be impossible.
JP 11-215602 A

  The present invention has been made in view of such a conventional problem, and is a parallel inverter power supply system capable of parallel synchronous operation without adding a special signal line for starting and without overload at the time of starting. It is an object to provide a control method and a parallel inverter power supply system.

  The present invention relates to a control method for a parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output terminal and power is shared and supplied to a load, and one of the plurality of inverters is activated. After that, the operation is temporarily stopped after a predetermined time, and the bus voltage drop timing at the time of the operation stop is detected by a voltage sensor provided in each of the plurality of inverters, and the output voltage phase reference is set to a predetermined value at that timing. Each inverter is reset all at once, and after a predetermined time from the bus voltage drop timing, the plurality of inverters are started simultaneously based on the output voltage phase reference to start a parallel synchronous operation. It is what.

  Further, the present invention is a control method for a parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output terminal and power is shared and supplied to a load, and one of the plurality of inverters is controlled. The base is started at a voltage lower than the low-grade voltage for normal operation, and the other inverters are phase-locked in parallel, and then the voltage is increased to the rated voltage all at once, and the normal operation is started. It is.

  Further, the present invention is a parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output terminal, and the power to the load is shared and each of the plurality of inverters includes an inverter control device. Each of the inverter control devices includes a priority activation determination unit that determines a priority activation command given from the outside, a startup command reception unit that receives a startup command given from the outside, and the priority activation determination unit that performs priority activation of its own inverter. When the start command receiving means receives the start command, the inverter pre-start means that once stops operation after a predetermined time and the bus voltage for detecting the output voltage of the corresponding inverter. The output voltage for the corresponding inverter at the bus voltage drop timing detected by the detecting means and the bus voltage detecting means Output voltage reference reset means for resetting the phase reference to a predetermined value determined in advance, and inverter full-scale start means for starting the corresponding inverter and raising it to the rated voltage reference after a predetermined time from the bus voltage drop timing It is a feature.

  Furthermore, the present invention provides a parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output end and share and supply power to a load, and each of the plurality of inverters includes an inverter control device. Each of the inverter control devices includes a priority activation determination unit that determines a priority activation command given from the outside, a startup command reception unit that receives a startup command given from the outside, and the priority activation determination unit that performs priority activation of its own inverter. And when the start command receiving means receives the start command, the prestart means for starting the corresponding inverter at a prestart voltage lower than the rated value, and a predetermined time after the corresponding inverter is prestarted The first inverter full-scale starting means for raising the voltage to the rated voltage, and the priority start determining means for performing the priority start of the own inverter Otherwise, when the start command receiving means receives the start command, the time measurement is started, and after the elapse of time equal to the preliminary start time, the corresponding inverter is started and raised to the rated voltage reference. And a starting means.

  According to the present invention, one inverter is started at a value lower than the rated voltage, for example, a voltage lower than a voltage threshold value at which many load devices detect power supply, and then a voltage output is temporarily output after a predetermined time. The output voltage phase reference is reset to a predetermined value by detecting the timing edge of the voltage output stop by the voltage detector provided in each inverter, and after a certain time, based on the output voltage phase reference of each inverter By starting all at once, parallel synchronous operation is possible without adding a special signal line for starting and without overload at the time of starting.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  (First Embodiment) FIG. 1 is a block diagram of a two-unit parallel inverter power supply system for implementing a control method according to a first embodiment of the present invention. The two PWM inverters IV1 and IV2 are connected in parallel to the bus and supply power to the load LD. The inverter (1) control device 1 that controls the PWM inverter (1) IV1 includes an edge detection unit 11 that detects a falling edge or a rising edge of the voltage based on a detected value between the bus-bar voltages detected by the bus-bar voltage detection sensor VS1. And a reference phase calculator 12, a voltage amplitude setting unit 13, a voltage command calculator 14, and a voltage controller 16. The inverter (2) control device 2 that controls the PWM inverter (2) IV2 has the same configuration. Each inverter control device when three or more inverters are arranged in parallel has the same configuration.

  The three-phase outputs of the PWM inverters IV1 and IV2 are provided with LC filters (filters composed of a reactor and a capacitor) FL1 and FL2 for removing harmonics caused by the PWM. Transformers TR1 and TR2 for electrically insulating the input and the AC output are installed. Here, an example will be described in which the output frequency of the inverter is 60 Hz and the output voltage is 440 V in terms of the effective value between lines.

The operation of each component will be described below with reference to FIGS. The edge detector 11 receives the voltage detection values Vuv, Vvw, and Vwu between the buses detected by the bus voltage detection sensor VS1, and calculates the voltage vector amplitude absV1 by the following equation:

In accordance with the value of the voltage vector amplitude absV1, the voltage amplitude flag FLG_V1 is obtained and output in the next conditional branch. This calculation is repeatedly executed at a sufficiently fast period with respect to the voltage cycle, for example, on the order of several tens of microseconds.

FLG_V1 = 1 when absV1> 50V or more
FLG_V1 = 0 when absV1 <50V or less
The condition amplitude 50V is selected by the voltage amplitude setting unit 13 described later as an intermediate value between the voltage command 100V and 0V output when priority startup is input by the priority startup command flag FLGmaster input from the outside. If the voltage value is between 100V and 0V, the value of 50V can be set arbitrarily.

  The reference phase calculation unit 12 receives the voltage amplitude flag FLG_V1 output from the edge detection unit 11, the preferential start flag FLGmaster input from the outside, and the start command Gst input from the outside, and performs the following calculation and conditional branching: To obtain and output the reference phase θinv. The priority start flag FLGmaster is pre-set with a priority start system inverter in the system, and in the present embodiment, the inverter (1) IV1 side is described as being given priority. Accordingly, the priority activation flag FLGmaster is sent with 1 set for the inverter (1) IV1 for priority activation and 0 for the inverter (2) IV2 for non-priority activation. When there are three or more PWM inverters, FLGmaster = 1 is set only for one priority start inverter, and all other inverters are set with FLGmaster = 0.

  The reference phase calculation unit 12 of the inverter (1) IV1 to which FLGmaster = 1 is input, for example, when the auxiliary power switch is turned on after the train is started, the start command Gst is changed from 0 indicating that the inverter operation is stopped. Starting from 0 ° at the timing of switching to 1 for instructing the start of operation, the output of the phase θinv with an output frequency of 60 Hz is started.

  Thereafter, at the timing when the voltage amplitude flag FLG_V1 output from the edge detection unit 11 is switched from 1 to 0, the phase θinv is reset to 0 °, and the output of the phase θinv with an output frequency of 60 Hz starts newly from 0 °. .

  The reference phase calculation unit 12 of the inverter (2) IV2 to which FLGmaster = 0 is input starts from 0 ° at the timing when the voltage amplitude flag FLG_V1 output from the edge detection unit 11 switches from 1 to 0, and has an output frequency of 60 Hz. The output of the phase θinv is started.

  The voltage amplitude setting unit 13 receives the voltage amplitude flag FLG_V1 output from the edge detection unit 11, the preferential start flag FLGmaster input from the outside, and the start command Gst input from the outside, and performs the following calculation and conditional branching: Thus, the voltage amplitude command absV1Ref is obtained and output.

  (A1) The voltage amplitude setting unit 13 of the inverter (1) IV1 to which FLGmaster = 1 is input is set to 100 V / at the timing when the start command Gst is switched from 0 indicating the inverter operation stop to 1 indicating the inverter operation start. The voltage amplitude command absV1Ref which increases from 0V to 100V at a constant rate of 100 msec starts to be output. After reaching 100V, the voltage is kept constant at 100V.

  The absV1Ref is switched to 0V stepwise after a certain time from the timing when the start command Gst is switched from 0 to 1, here 200 msec.

  After that, after 166.66 msec (10 cycles at 60 Hz) has elapsed from the timing when the voltage amplitude flag FLG_V1 output from the edge detection unit 11 switches from 1 to 0, a constant rate of increase of 100 V / 100 msec from 0 V to the rated voltage 440 V The output of the voltage amplitude command absV1Ref that increases at the start is newly started.

  (A2) The voltage amplitude setting unit 13 of the inverter (2) IV2 to which FLGmaster = 0 is input is 166.66 msec from the timing when the voltage amplitude flag FLG_V2 output from the falling edge detection unit 11 is switched from 1 to 0. After the elapse of 10 cycles at 60 Hz, a voltage amplitude command absV2Ref starting from 0V and increasing at a constant rate of 100V / 100 msec to the rated voltage of 440V is output.

The voltage command calculation unit 14 in each of the inverter control devices 1 and 2 receives the reference phase θinv output from the reference phase calculation unit 12 and the voltage amplitude commands absV1Ref and absV2Ref output from the voltage amplitude setting unit 13 as inputs. By calculation, three-phase voltage commands VuRef, VvRef, and VwRef having different phases by 120 ° are obtained and output.

  The voltage control unit 15 in each inverter control device 1, 2 receives the three-phase voltage commands VuRef, VvRef, VwRef output from the voltage command calculation unit 14 and the bus voltage detection values Vuv, Vvw, Vwu as input. Then, voltage feedback control is performed so as to follow the voltage command. This voltage control operation is the same as general voltage feedback control that has been performed conventionally.

  According to the present embodiment, by starting the inverters IV1 and IV2 in parallel by the above control method, parallel synchronous operation is possible without adding a special signal line for starting and without overload at the time of starting. .

  (Second Embodiment) FIG. 3 is an operation timing chart of each element in a parallel inverter power supply system for implementing a control method according to a second embodiment of the present invention. The configuration of the parallel inverter power supply system that implements the second embodiment is the same as that of the system of the first embodiment shown in FIG. The operation of the edge detection unit 11 of each of the control devices 1 and 2 is the same as that in the first embodiment.

  The reference phase calculation unit 12 receives the voltage amplitude flag FLG_V1 output from the falling edge detection unit 11, the priority start flag FLGmaster input from the outside, and the start command Gst input from the outside, and performs the following calculation: The reference phase θinv is obtained and output by conditional branching.

  The priority activation flag FLGmaster is sent with 1 set for the inverter (1) IV1 for priority activation and 0 for the inverter (2) IV2 for non-priority activation. In the case of three or more units, only one priority start inverter is 1, and all other inverters are set to 0 and sent.

  The reference phase calculation unit 12 of the inverter (1) IV1 to which FLGmaster = 1 is input starts from 0 ° at the timing when the start command Gst is switched from 0 indicating the inverter operation stop to 1 indicating the inverter operation start. Output of phase θinv with a frequency of 60 Hz is started.

  The reference phase calculation unit 12 of the inverter (2) IV2 to which FLGmaster = 0 is input is 166.66 msec (10 cycles at 60 Hz) from the timing when the voltage amplitude flag FLG_V2 output from the edge detection unit 11 is switched from 0 to 1. After the lapse of time, the output starts at 0 ° and starts to output a phase θinv having an output frequency of 60 Hz.

  The voltage amplitude setting unit 13 of each of the inverter control devices 1 and 2 includes voltage amplitude flags FLG_V1 and FLG_V2 output from the edge detection unit 11, a preferential start flag FLGmaster input from the outside, and a start command Gst input from the outside. Is input and the voltage amplitude commands absV1Ref and absV2Ref are obtained and output by the following calculation and conditional branching.

  The voltage amplitude setting unit 13 of the inverter (1) IV1 to which FLGmaster = 1 is input steps from 0V to 100V at the timing when the start command Gst is switched from 0 indicating the inverter operation stop to 1 indicating the inverter operation start. The output of the voltage amplitude command absV1Ref that increases in a manner is started.

  Thereafter, a voltage amplitude command that increases at a constant rate of 100 V / 100 msec to the rated voltage of 440 V after 250 msec (15 cycles at 60 Hz) has elapsed from the timing when the voltage amplitude flag FLG_V1 output from the edge detector 11 switches from 0 to 1. absV1Ref is output.

  The voltage amplitude setting unit 13 of the inverter (2) IV2 to which FLGmaster = 0 is input is 166.66 msec (10 cycles at 60 Hz) from the timing when the voltage amplitude flag FLG_V2 output from the edge detection unit 11 is switched from 0 to 1. After the elapse, the voltage command absV2Ref is increased from 0V to 100V in a stepwise manner.

  Thereafter, a voltage amplitude command that increases at a constant rate of 100 V / 100 msec up to the rated voltage of 440 V after 250 msec (15 cycles at 60 Hz) has elapsed since the timing when the voltage amplitude flag FLG_V2 output from the edge detector 11 switches from 0 to 1. absV2Ref is output. The operations of the voltage command calculation unit 14 and the voltage control unit 15 are the same as those in the first embodiment and perform the same functions.

  According to the second embodiment, by starting the inverters (1) IV1 and (2) IV2 in parallel by the above control method, there is no need to add a special signal line for starting, and overload at the time of starting is also possible. Parallel synchronous operation is possible without.

  (Third Embodiment) A third embodiment of the present invention will be described with reference to FIGS. In the third embodiment, switches 21 and 22 are provided on the load-side output lines of the isolation transformers TR1 and TR2 in FIG. 4, and the priority control command FLGmaster and the startup command Gst from the outside are provided to the inverter control devices 1 and 2, respectively. And a control method of the inverter for the parallel inverter power supply system provided with the switch input command units 31 and 32 for turning on / off the switches 21 and 22 according to the value. In the system shown in FIG. 4, circuit elements common to the system shown in FIG. 1 are denoted by common reference numerals.

  In the present embodiment, as shown in FIG. 5, the switch-on command units 31 and 32 provide (i) an ON command when the inverter start command Gst is switched from 0 to 1 when the priority start command FLGmaster is 1. The output to the corresponding switch 21 or 22 is closed and the output line of the inverter IV1 or IV2 is closed, (ii) the corresponding switch 21 or 22 is turned OFF after a certain period of time, and (iii) 166.66 msec (10 Hz at 60 Hz). Control is performed to turn on the same switch 21 or 22 after a period of time. The switch-in command units 31 and 32 also (iv) when the priority start command FLGmaster is 0, and (iii) the time from when the start command Gst is switched to 0 or 1 until the aforementioned (ii) OFF. Control is performed to turn on the corresponding switch 21 or 22 after the elapse of the total time from the time until ON. In addition, the arithmetic control of each other part is the same as that of the control sequence of FIG. 2 by the parallel inverter power supply system which employ | adopts 1st Embodiment.

  According to the third embodiment, in addition to the operation and effect of the first embodiment, the bus voltage is set to 100 V even in a system in which a circuit element with a slow time constant exists on the output side of the inverter. The initial cut-off up to 0V can be performed more quickly, and there is an advantage that the timing of synchronous parallel activation control can be made more accurately.

The block diagram of the parallel inverter power supply system which uses the control method of the 1st Embodiment of this invention. The start control timing chart of the parallel inverter by the 1st Embodiment of this invention. The starting control timing chart of the parallel inverter by the 2nd Embodiment of this invention. The block diagram of the parallel inverter power supply system which uses the control method of the 3rd Embodiment of this invention. The start control timing chart of the parallel inverter by the 3rd Embodiment of this invention. The start control timing chart of the parallel inverter by a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inverter (1) control apparatus 2 Inverter (2) control apparatus 11 Edge detection part 12 Reference | standard phase calculating part 13 Voltage amplitude setting part 14 Voltage command calculating part 15 Voltage control part 21, 22 Switch 31, 32 Switch input command part IV1 Inverter (1)
IV2 Inverter (2)

Claims (7)

A control method for a parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output end, and power is shared and supplied to a load.
After starting one of the plurality of inverters, the operation is temporarily stopped after a predetermined time,
The bus voltage drop timing at the time of the operation stop is detected by a voltage sensor provided in each of the plurality of inverters, and the inverters are simultaneously reset to a predetermined value with a predetermined output voltage phase reference at that timing,
A method of controlling a parallel inverter power supply system, wherein a parallel synchronous operation is started by simultaneously starting the plurality of inverters based on the output voltage phase reference after a predetermined time from the bus voltage drop timing .     2. The control method for a parallel inverter power supply system according to claim 1, wherein the starting voltage of the first one of the plurality of inverters is set to a voltage lower than a rated voltage for normal operation.     The voltage output of the first inverter among the plurality of inverters is temporarily stopped to take the reset timing of the output voltage phase reference, and the switch installed between the inverter and the bus is turned off. It implement | achieves by making it implement | achieve, The control method of the parallel inverter power supply system of Claim 1 characterized by the above-mentioned. A control method for a parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output end, and power is shared and supplied to a load.
Start up one of the multiple inverters at a voltage lower than the lower rated voltage for normal operation, and then shift to normal operation by raising the other inverters to the rated voltage all at once after phase-locked parallel startup. A control method for a parallel inverter power supply system.   5. The parallel operation according to claim 4, wherein the phase-synchronized juxtaposition of the other inverters is realized by resetting an output voltage phase reference by detecting a rising edge of a bus voltage by an inverter output started at the first low voltage. Inverter power system control method. A parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output end, and power is shared and supplied to a load.
Each of the plurality of inverters includes an inverter control device,
Each of the inverter control devices
Priority activation determining means for determining a priority activation command given from outside;
A start command receiving means for receiving a start command given from the outside;
Inverter pre-starting means for temporarily stopping the operation after a predetermined time after starting the corresponding inverter when the start-up command receiving means receives the start-up command when the priority start determining means identifies the priority start of its own inverter; ,
Bus voltage detection means for detecting the output voltage of the corresponding inverter;
Output voltage reference reset means for resetting the output voltage phase reference for the corresponding inverter to a predetermined value determined in advance at the bus voltage drop timing detected by the bus voltage detection means;
A parallel inverter power supply system comprising: an inverter full-scale starting means for starting the corresponding inverter and raising it to a rated voltage reference after a predetermined time from the bus voltage lowering timing. A parallel inverter power supply system in which a plurality of inverters are connected in parallel at an AC output end, and power is shared and supplied to a load.
Each of the plurality of inverters includes an inverter control device,
Each of the inverter control devices
Priority activation determining means for determining a priority activation command given from outside;
A start command receiving means for receiving a start command given from the outside;
In the case where the priority start determination means identifies the priority start of the own inverter, when the start command receiving means receives the start command, the preliminary start means for starting the inverter at a preliminary start voltage lower than the rating;
First inverter full-scale starting means for increasing the voltage to the rated voltage after a predetermined time after the corresponding inverter is pre-started;
When the priority activation determining means does not identify the priority activation of the own inverter, it starts timing when the activation instruction receiving means receives the activation instruction, and after the elapse of time equal to the preliminary activation time, A parallel inverter power supply system comprising: a second inverter full-scale starting means for starting and raising to a rated voltage reference.

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