JP2006073568A - Protective element and semiconductor apparatus using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a protective element which can remarkably improve ESD (electrostatic discharge) voltage without degrading high-frequency characteristics and computational power of an element to be protected, and also to provide a semiconductor apparatus using the same. <P>SOLUTION: Between two terminals of the element to be protected which contains a pn junction, a Schottky junction, or capacitance; the protective elements, each consisting of a first n<SP>+</SP>-type region, an insulation region, and a second n<SP>+</SP>-region, are connected in parallel. The first n<SP>+</SP>-type region and/or the second n<SP>+</SP>-region contains a very narrow end on the side which faces the counterpart, with the end overlapped by and in contact with a metal layer. Due to this structure, very large electrostatic discharge is available between the first and second n<SP>+</SP>-regions which are close to each other, resulting in remarkably decreasing electrostatic energy to an operating region of HEMT while barely increasing parasitic capacitance. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a protection element and a semiconductor device using the protection element, and more particularly to a protection element that significantly improves the electrostatic breakdown voltage without deteriorating the high-frequency characteristics and calculation processing speed of the protected element, and a semiconductor device using the protection element. .

  In a conventional semiconductor device, in general, in order to protect a device from static electricity, a method of connecting an electrostatic breakdown protection diode in parallel to a device including a pn junction, a Schottky junction, and a capacitor that are easily damaged by electrostatic breakdown has been adopted. .

  FIG. 24 shows an electrostatic breakdown protection circuit of a conventional semiconductor device. That is, pn junction diodes D1 and D2 are formed in the vicinity of the external input / output bonding pad 301, the anode side of the diode D1 is connected to the bonding pad 301, the cathode side is connected to the power supply potential Vcc, and the cathode of the diode D2 is bonded. The anode is connected to the pad 301 to the ground potential, and the electrode wiring 302 extending from the bonding pad 301 is connected to one end of the resistance region 303 formed by the p-type diffusion region, and the other end of the resistance region 303 is connected to the electrode wiring 304. The structure which connected to and connected to the internal circuit was employ | adopted (for example, refer patent document 1).

  Also, as shown in FIG. 25, a technique in which a protective element 360 having an n + / i / n + structure is connected between two terminals of a protected element is known in order to significantly improve the electrostatic breakdown voltage in the compound semiconductor device. The figure shows a switch circuit device composed of an FET having a source 315, a gate 317, and a drain 320, in which a protection element 360 is connected between an input terminal and a control terminal, and between an output terminal and a control terminal (for example, Patent Documents). 2).

  FIG. 26 shows the OUT-1 Pad portion of FIG. The protective element 360 is connected by disposing an n + type region 350 provided below the pad and a resistance R of an n + type impurity close to 4 μm. In some cases, a region for forming current paths I and I ′ for attenuating electrostatic energy is secured by using a pattern of the resistor R (see, for example, Patent Document 3).

FIG. 27 shows an integrated circuit device (hereinafter referred to as LSI), in which a protection element region 407 is formed around a logic circuit 408. The figure shows a protection circuit against an excessive voltage due to static electricity or the like of a MOS type IC, which is a so-called CMOS buffer circuit type protection circuit in which protective elements for a gate-grounded p-channel MOSFET 401 and a gate-grounded n-channel MOSFET 402 are arranged around the logic circuit 408. . The signal line 403 connected to the input / output terminal pad 400 is connected to the reference voltage GND through the n-channel MOSFET 402 and is connected to the power supply voltage Vcc through the p-channel MOSFET 401. (For example, refer to Patent Document 4).
JP-A-6-29466 International Publication No. 2004/027869 Pamphlet Fig. 12 International Publication No. 2004/023555 Pamphlet Figure 23 Japanese Patent Laid-Open No. 7-169918

  In general, in order to protect a device from static electricity, a method of connecting a protective diode such as a pn junction diode in FIG. 24 in parallel to a protected element (device) has been adopted.

  However, in a microwave device, an increase in parasitic capacitance caused by connecting a protective diode causes deterioration of high frequency characteristics, and the method cannot be employed. In particular, in a compound semiconductor device such as MESFET and HEMT (High Electron Mobility Transistor) used for microwave applications in the GHz band or higher, such as for satellite broadcasting, mobile phones, and wireless broadband, excellent microwaves are used. In order to ensure the characteristics, the gate length is also in the submicron order, and the gate Schottky junction capacitance is designed to be extremely small. For this reason, it is extremely vulnerable to electrostatic breakdown, and careful handling is required, including MMIC integrated with GaAs MESFET and HEMT. Furthermore, in general consumer semiconductors with low frequencies such as those for sound, video, and power supplies, protection diodes that are widely used to increase the electrostatic breakdown voltage have pn junctions. Since it greatly increases to fF or more, there has been a problem of greatly degrading the microwave characteristics of the compound semiconductor device.

  On the other hand, in FIG. 25, n + type regions 350 are provided around the common input terminal pad INPad, around the OUT-1Pad, and around the OUT-2Pad in order to improve isolation. The n + type region 350 and resistors R1 and R2 formed by ion implantation of n + type impurities are arranged close to 4 μm. These adjacent n + -type regions become a protection element 360 together with an insulating region (GaAs substrate) 355 disposed therebetween.

  Since the protection element 360 has no pn junction, it has a small number of parasitic capacitances and several fF compared with the protection diode. However, it has been found that a part of the input signal input from the common input terminal pad INPad leaks to the control terminal pad Ctl-1Pad having the high-frequency GND potential through the resistor R1. This is because the resistor R1 is arranged close to the common input terminal pad INPad over a long distance of 80 μm at a position close to the control terminal pad Ctl-1Pad in order to enhance the protective effect.

  Such a leakage of an input signal due to a parasitic capacitance of about several fF does not cause a problem in, for example, a MESFET. However, especially when connecting to a HEMT having a small off-capacitance, although it is only a few fF, it exceeds a negligible level with respect to a small off-capacitance of the HEMT, which affects the high-frequency characteristics, and the insertion loss is a protective element. There was a problem that it deteriorated more than the insertion loss when 360 is not connected.

  Further, in FIG. 26, the main current path I and the side current path I ′ are formed in the insulating region 355 by the n + type region serving as the resistance R, and a larger electrostatic energy is discharged using these. Since the protection effect against electrostatic breakdown increases as the distance at which the n + type regions serving as the terminals of the protective elements are opposed to each other is longer, the resistance (n + type region) R extends along the n + type region 350 below the pad as long as possible. Is arranged. However, the width of the resistor R is reduced to 3 μm to reduce the parasitic capacitance. However, even if the width of the resistor R is reduced, the n + -type regions serving as the terminals of the protective element 360 are small in the region where the n + -type regions are opposed to each other. Capacitance is generated and the insertion loss of the HEMT switch is deteriorated. In other words, in order to increase the electrostatic breakdown strength, the parasitic capacitance increases as the n + -type regions face each other longer. In particular, when the protective element 360 is connected to a protected element having a small off-capacitance, the degradation of the insertion loss becomes significant. It was.

  In the LSI 410 such as a CMOS logic circuit element as shown in FIG. 27, the performance of the MOSFET, which is a basic element constituting the logic circuit 408, is further improved with the miniaturization of the device. In other words, the gate length is shorter and the gate oxide film is becoming thinner, but on the other hand, the device is weak against electrostatic breakdown. In order to protect this, a protection element region 407 in which a plurality of protection elements are arranged is arranged around the logic circuit 408. However, since the protection effect increases as the size of the protection element increases, there is a problem in that the area of the protection element region 407 increases excessively with respect to the area of the logic circuit 408, and the cost of the LSI 410 increases. Further, even if the size of the protection element region 407 is increased to a certain extent, the operation as a protection element becomes non-uniform, and there is a problem that the protection effect is limited. Further, if the protective element region 407 is large, large protective elements are connected in parallel, and there is a disadvantage that the calculation processing speed of the LSI 410 is reduced due to the parasitic capacitance of the protective elements.

  The present invention has been made in view of such a problem. First, it includes two high-concentration impurity regions disposed opposite to a substrate, and an insulating region disposed around the two high-concentration impurity regions. The high-concentration impurity region has a first side surface that is a minute facing surface of the other high-concentration impurity region, and is sufficiently large with respect to the first side surface and extends away from the first side surface in a substantially vertical direction. A bar-like shape having a second side surface, a third side surface in contact with a metal layer exposed from the substrate and protruding from the electrode pad or wiring, and a fourth side surface facing the third side surface, The high concentration impurity region is connected between two terminals of the protected element as two terminals, and the one high concentration impurity region is directed from the first side surface and the fourth side surface to the corresponding side surface of the other high concentration impurity region. Before the direction of extension A first current path serving as a path for electron current and hole current formed in the insulating region; and formed in the insulating region outside the first current path and from the second side surface toward the other high-concentration impurity region. The problem is solved by attenuating the electrostatic energy applied between the two terminals of the protected element by a second current path serving as a path for electron current and hole current.

  The other high-concentration impurity region is arranged around another electrode pad or another wiring.

  The current value of the second current path is at least five times the current value of the first current path.

  In addition, the width of the high concentration impurity region on the first side surface is 5 μm or less.

  Further, by connecting a pair of the high-concentration impurity regions as two terminals between the two terminals of the protected element, the electrostatic breakdown voltage of the protected element is 300 V or more in the machine model and between the two terminals. The parasitic capacitance value is 0.7 fF or less.

  The second current path is formed with a width of 15 μm or more from the second side surface.

  Second, at least one FET having a source electrode, a gate electrode and a drain electrode connected to an operating region on the substrate, at least one input terminal connected to the source electrode or drain electrode of the FET, and the drain of the FET At least one output terminal connected to an electrode or a source electrode; a switch circuit element having a terminal for applying a DC potential to the FET; two high-concentration impurity regions disposed opposite to the substrate; and the two high-concentration regions An insulating region disposed around the impurity region, wherein at least one of the high-concentration impurity regions has a first side surface that is a minute facing surface of the other high-concentration impurity region, and the first side surface A second side surface which is sufficiently large and extends away from the first side surface in a substantially vertical direction, and is electrically exposed to any of the terminals exposed from the substrate. A bar having a third side surface in which a metal layer protruding from an electrode pad or wiring connected to the electrode and a contact is overlapped, and a fourth side surface opposite to the third side surface, and the two high-concentration impurity regions are connected to two terminals. A protection element to be connected between the two terminals of the switch circuit element, and the one high concentration impurity region extending from the first side surface and the fourth side surface toward a corresponding side surface of the other high concentration impurity region. A first current path serving as a path for electron current and hole current formed in the insulating region in a direction, and the insulating region from the second side surface toward the other high-concentration impurity region outside the first current path. The problem is solved by attenuating the electrostatic energy applied between the two terminals of the switch circuit element by the second current path that is the path of the formed electron current and hole current.

  Third, the first and second FETs having the source electrode, the gate electrode, and the drain electrode connected to the operation region on the substrate are formed, and the terminal connected to the source electrode or the drain electrode common to both FETs is a common input terminal. The terminals connected to the drain electrode or source electrode of both FETs are the first and second output terminals, respectively, and the terminals connected to one of the gate electrodes of both FETs are the first and second control terminals, respectively. A control signal is applied to the control terminal, and one of the FETs is made conductive through a resistor which is a connecting means for connecting the two control terminals and the gate electrode, and the common input terminal and the first and second A switch circuit element that forms a signal path with any one of the output terminals, two high-concentration impurity regions disposed opposite to the substrate, and the two high-concentration regions An insulating region disposed around a pure region, and at least one of the high-concentration impurity regions includes a first side surface that is a minute facing surface of the other high-concentration impurity region, and the first side surface. A metal layer protruding from an electrode pad or wiring exposed from the substrate and electrically connected to any one of the terminals, and a second side surface that is sufficiently large and extends away from the first side surface in a substantially vertical direction. Is a rod-like shape having a third side surface in contact with each other and a fourth side surface facing the third side surface, and a protective element having the two high-concentration impurity regions as two terminals is provided between the two terminals of the switch circuit element. An electron current formed in the insulating region in the extending direction of the one high concentration impurity region from the first side surface and the fourth side surface toward the corresponding side surface of the other high concentration impurity region; Hall current A first current path serving as a path, and a second current serving as a path for electron current and hole current formed in the insulating region from the second side surface toward the other high concentration impurity region outside the first current path. The problem is solved by attenuating the electrostatic energy applied between the two terminals of the switch circuit element by the path.

  The other high-concentration impurity region is a part of the connection means.

  In addition, the protection element is connected between at least one of the control terminal and the common input terminal of the switch circuit element.

  The other high-concentration impurity region is arranged around another electrode pad or another wiring electrically connected to one of the terminals of the switch circuit element.

  Further, by connecting the protection element having a pair of the high-concentration impurity regions as both terminals and having a parasitic capacitance value between both terminals of 0.7 fF or less between the two terminals of the switch circuit element, the switch circuit The electrostatic breakdown voltage of the element is 300 V or more in the machine model.

  Fourth, an integrated circuit element having a plurality of input / output terminals, a power supply terminal, and a ground terminal, two high-concentration impurity regions disposed opposite to the substrate, and insulation disposed around the two high-concentration impurity regions A protection element having a region, wherein at least one of the high-concentration impurity regions is a first side surface that is a minute facing surface of the other high-concentration impurity region, and the first side surface is sufficiently large with respect to the first side surface. A second side surface extending substantially vertically away from the side surface and an electrode pad exposed from the substrate and electrically connected to one of the terminals or a metal layer protruding from the wiring are in contact with each other. A bar having three side surfaces and a fourth side surface opposite to the third side surface, the two high-concentration impurity regions serving as two terminals, connected between two terminals of the integrated circuit element, and the first side surface and the first side surface Front from 4 sides A first current path serving as a path for electron current and hole current formed in the insulating region in the extending direction of the one high-concentration impurity region toward a corresponding side surface of the other high-concentration impurity region; Applied between the two terminals of the integrated circuit element by a second current path that is a path of electron current and hole current formed in the insulating region from the second side surface toward the other high concentration impurity region outside the path. The problem is solved by attenuating the electrostatic energy.

  The integrated circuit element is a CMOS logic circuit element.

  Further, the integrated circuit element and the protection element are integrated on the same substrate.

  Further, the protective element is disposed on the integrated circuit element.

  The wiring is a first wiring connected to a power supply terminal of the integrated circuit element and a second wiring connected to the ground terminal.

  The protection element is connected to at least one of the integrated circuit element between the input / output terminal and the power supply terminal and between the input / output terminal and the ground terminal.

  The other high-concentration impurity region is provided in the vicinity of another electrode pad or wiring connected to one of the terminals of the integrated circuit element.

  Further, by connecting the protective element having a pair of the high-concentration impurity regions as both terminals and having a parasitic capacitance value between both terminals of 0.7 fF or less between the two terminals of the integrated circuit element, the integrated circuit The electrostatic breakdown voltage of the element is 300 V or more in the machine model.

  As described above in detail, according to the present invention, the following effects can be obtained.

  First, the protection element uses a second current path formed in an insulating region where at least one terminal is a rod-shaped n + region and the second side surface of the rod-shaped n + region is directed to the n + region that is the other terminal. Can flow static electricity. Since the second current path is formed so as to extend as large as several tens of μm in the horizontal and vertical directions of the insulating region, a very large electrostatic current can flow and the protective effect is great. In addition, since the area facing the n + -type region serving as the other terminal is very small, the parasitic capacitance of this portion becomes very small and high-frequency signals do not leak. Therefore, even when the device is used in a switch circuit device having a very small off-capacitance device such as a HEMT as a basic device, it is possible to prevent deterioration of the insertion loss due to the connection of the protective element.

  Further, since the metal layer is arranged on the rod-shaped n + type region, static electricity flows evenly over the entire rod-shaped n + type region, and this can also increase the protective effect.

  Second, by connecting a protection element to the switch circuit device, the protection effect between the two terminals of the switch circuit device that is vulnerable to electrostatic breakdown can be greatly enhanced. Further, the (bar-shaped) n + type region and the metal layer serving as the terminals of the protective element can be formed in the same process as other components of the switch circuit device. That is, the protective element can be connected without increasing the number of steps.

  Further, the protective element can be disposed in an insulating region between the pads. The conventional n + / i / n + type protection element requires an area occupied by the protection element in the chip, such as increasing the distance between the opposing n + type regions in order to enhance the protection effect. The space for connecting the protective element is not required, and the protective element can be connected using a region where no other component is arranged.

  Thirdly, the protection element is further connected by using a component of the switch circuit device such as a peripheral high-concentration impurity region for securing isolation around the pad and the wiring, and a resistor as the other terminal of the protection element. Therefore, the occupied area can be reduced.

  Fourth, by connecting this protection element to an LSI such as a CMOS logic circuit instead of the conventional CMOS buffer circuit type protection circuit, the area occupied by the protection element of the logic circuit can be greatly reduced, and the LSI can be downsized. Cost reduction can be realized.

  For example, when the logic circuit element and the protection element region are integrated on one chip, the protection element is utilized by using wiring and input / output terminal pads connected to the power supply terminal and the ground terminal arranged on the outer periphery of the logic circuit element region. Therefore, the protective element can be connected with a chip size substantially equivalent to a chip having only a logic circuit.

  Further, since the protective element can be formed by one chip and stacked on the logic circuit element, the protective element can be connected with the chip size of only the logic circuit element, and the protective effect can be increased.

  That is, the protection element of the present invention has a very large second current path between the two terminals of the protection element even though the first side surface has a very small parasitic capacitance because the width of the first side surface is very small. Since it has the ability to flow current, the protected element can be protected from a very large electrostatic voltage. Specifically, by connecting a protective element having a pair of rod-shaped n + type regions as both terminals, the protected element can be protected from an electrostatic breakdown voltage of 300 V or more with a machine model (200 pF, 0Ω), and The parasitic capacitance value at that time is 0.7 fF (at 0 V bias) or less.

  Furthermore, the ability to protect against electrostatic breakdown can be increased by connecting a plurality of rod-shaped n + type regions in parallel.

  Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS. First, a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic diagram illustrating a protection element 200 according to the first embodiment. 1A and 1D are plan views, FIG. 1B is a cross-sectional view taken along line aa in FIG. 1A, and FIG. 1C is a line bb in FIG. 1A. It is sectional drawing.

  The protective element 200 includes two high-concentration impurity regions 201 disposed opposite to the substrate 101 and an insulating region 203 disposed around the high-concentration impurity region 201.

  The substrate 101 may be any semiconductor substrate such as a silicon semiconductor substrate, a compound semiconductor substrate, or an HEMT epitaxial substrate, and the high concentration impurity region 201 is provided on these substrates. The two high-concentration impurity regions 201 are impurity regions of the same conductivity type, and the case of n-type impurities will be described below as an example.

The two high-concentration impurity regions 201 are provided at a distance allowing the passage of electrostatic energy, for example, about 4 μm, and both impurity concentrations are 1 × 10 ¹⁷ cm ⁻³ or more. The periphery of the high concentration impurity region 201 is an insulating region 203. Here, the insulating region 203 is not an electrically complete insulation but an insulated region obtained by ion implantation of impurities into a part of the semi-insulating substrate or the substrate 101. The impurity concentration in the insulating region is preferably about 5 × 10 ¹⁴ cm ⁻³ or less, and the resistivity is preferably 1 × 10 ³ Ωcm or more. Furthermore, the insulating region may be formed of non-doped polysilicon.

  At least one high-concentration impurity region 201 has a rod shape having a first side surface S1, a second side surface S2, a third side surface S3, and a fourth side surface S4.

  The first side surface S1 is a minute facing surface with the other high-concentration impurity region 201. The second side surface S2 is a surface that is sufficiently larger than the first side surface S1 in the substrate depth direction and extends from the first side surface S1 in a substantially vertical direction. As shown in FIGS. 1A and 1B, for example, the width w1 of the rod-shaped high-concentration impurity region 201 is 5 μm or less (here, 3 μm) at least in the first side surface S1, and the width (length) of the second side surface S2. ) W2 is, for example, about 10 μm to 50 μm.

  An insulating film 205 is provided on the third side surface S3 facing the upper surface of the substrate, and the metal layer 201M contacts through a contact hole (shown by a broken line) in the insulating film 205. The fourth side surface S4 is a surface facing the substrate depth direction. The metal layer 201M is patterned in a shape overlapping with the rod-shaped n + type region 201 and is continuous with the neighboring electrode pad 201P or the wiring 201W. That is, the metal layer 201M has a shape protruding from the electrode pad 201P or the wiring 201W (FIGS. 1A and 1B). Although not shown, the width w1 of the rod-like high-concentration impurity region 201 may not be uniform. For example, a portion close to the electrode pad 201P or the wiring 201W may be wide and narrow toward the first side surface S1.

  In the present specification, hereinafter, the high concentration impurity region which is in contact with the metal layer 201M protruding from the electrode pad 201P or the wiring 201W is referred to as a rod-shaped n + type region 201. Further, even when illustration is omitted in the plan view because of overlapping, it is assumed that the rod-shaped n + type region 201 is disposed below the metal layer 201M.

  The width w3 of the surface of the metal layer 201M is 3 μm, which is the same as that of the rod-shaped n + type region 201, and the width w4 of the bottom surface in contact with the third side surface S3 is 2 μm (FIG. 1B). The metal layer 201M protrudes in a direction perpendicular to one side of the electrode pad 201P or in a direction perpendicular to the extending direction of the wiring 201W. Although not shown, the width w3 of the surface of the metal layer 201M may not be uniform. For example, the portion connected to the electrode pad 201P or the wiring 201W may be wide and narrow toward the first side surface S1.

  FIG. 1 shows a case where the high concentration impurity region serving as the other terminal of the protection element 200 is also a rod-shaped n + type region 201. That is, the other terminal similarly has the first side surface S1 to the fourth side surface S4, and the metal layer 201M protruding from the electrode pad 201P or the wiring 201W is in contact with each other as shown in FIG.

  The metal layer 201M is an ohmic metal layer that is in ohmic contact with the rod-shaped n + -type region 201 or a Schottky metal layer that is in Schottky junction. Alternatively, another metal layer may be superimposed on the ohmic metal layer or the Schottky metal layer to reduce series resistance.

  The protection element 200 of the present embodiment has a structure in which the insulating region 203 is arranged around the two rod-shaped n + type regions 201 as described above, and the rod-shaped n + type region 201 is connected to the two terminals of the protected element. At this time, when the separation distance of the rod-shaped n + type region 201 is set to about 4 μm, the electrostatic energy applied from the outside toward the two terminals of the protected elements to which the two rod-shaped n + type regions 201 are connected is changed to the insulating region 203. It can be discharged through.

  This separation distance of 4 μm is an appropriate distance for passing electrostatic energy, and if the separation distance is 10 μm or more, the discharge between the protective elements 200 is not reliable. Further, for example, too close to 1 μm or less is not preferable because it causes insufficient withstand voltage and increases parasitic capacitance. The same applies to the impurity concentration of the rod-shaped n + -type region 201 and the resistance value of the insulating region 203.

  1C and 1D are schematic views showing current paths during discharge. In the present embodiment, two current paths I1 and I2 are formed in the insulating region 203 around both terminals during discharge as shown by the arrows in the figure. The current path indicated by the arrow is a conceptual diagram, and details of the first current path I1 and the second current path I2 will be described later.

  For example, focusing on the rod-shaped n + region 201 located on the left side of FIG. 1D, the first current path I1 is directed from the first side surface S1 and the fourth side surface S4 to the corresponding side surface of the right rod-shaped n + region 201. This is a path of electron current and hole current formed in the insulating region 203 in the extending direction of the rod-shaped n + type region 201. In other words, the current path between the first side surface S1 and the fourth side surface S4 from the fourth side surface S4 to the fourth side surface S4 of the other rod-shaped n + region 201 as shown in FIG. A current path formed in the overlapping substrate depth direction.

  On the other hand, the second current path I2 is formed outside the first current path I1 in the insulating region 203 from the second side surface S2 of the left bar-shaped n + type region 201 in FIG. Electron current and hole current paths.

  In the rod-shaped n + type region 201 of the present embodiment, the first side surface S1 that is a surface facing the other rod-shaped n + type region 201 is minute, and the metal layer 201M is in contact with the whole. As a result, it is possible to significantly reduce the parasitic capacitance and form the second current path I2 having a very large current value.

  Accordingly, the electrostatic energy applied between the two terminals of the protection element 200 can be discharged between the two terminals of the protection element 200 using the first current path I1 and the second current path I2, and can be significantly attenuated.

  That is, the rod-shaped n + -type region 201 may be a discontinuous region as long as it is a region that contacts the same (one) metal layer 201M. In such a case, since the discontinuous regions are in contact with the same metal layer 201M to form the second current path I2, the rod-shaped n + type region 201 that collectively serves as one terminal of the protection element 200 is formed. And The rod-shaped n + type region 201 may be continuous or discontinuous when, for example, a high concentration impurity region for improving isolation is disposed below the electrode pad 201P or the wiring 201W. Good.

  In addition, since the metal layer 201M is disposed so as to allow the electrostatic current to flow through the entire rod-shaped n + type region 201, it is sufficient that there is a region where the two layers are in direct contact with each other, and the patterns do not have to match completely.

  2 and 3 show the case where the other terminal of the protection element 200 is another high-concentration impurity region 202. FIG. As shown in the drawing, in the protection element 200 of this embodiment, at least one terminal may be a rod-shaped n + region 201. In other words, the other terminal may be another high-concentration impurity region having a shape different from the rod-shaped n + type region 201. Alternatively, other high-concentration impurity regions that the metal layer 201M does not contact may be used. Hereinafter, another high-concentration impurity region will be described as an n + -type region 202.

  FIG. 2 shows a case where an n + type region 202 having the same shape as the rod-shaped n + type region 201 extends in a direction orthogonal to the rod-shaped n + type region 201. FIGS. 2A and 2C are plan views. FIG. 2B is a sectional view taken along the line dd. 3 shows a case where the n + -type region 202 has a shape similar to that of the pad, FIGS. 3A and 3C are plan views, and FIG. 3B is a sectional view taken along the line ff. . Note that the cross-sectional view taken along the line cc in FIG. 2A and the line ee in FIG. 3A is the same as FIG.

  The first current path I1 is formed in the insulating region 203 in the extending direction of the rod-shaped n + type region 201 from the first side surface S1 and the fourth side surface S4 to the corresponding side surface of the n + type region 202, as in FIG. Electron current and hole current paths.

  That is, the current path between the first side surface S1 and the current path formed in the substrate depth direction, overlapping the rod-shaped n + type region 201 and its extending direction from the fourth side surface S4 to the n + type region 202. .

  On the other hand, the second current path I2 is a path of electron current and hole current formed in the insulating region 203 from the second side surface S2 of the rod-shaped n + type region 201 toward the n + type region 202 outside the first current path I1.

  In the case where both terminals are rod-shaped n + type regions 201 as shown in FIG. 1, the current path formed from the fourth side surface S4 toward the other fourth side surface S4 is only the extending direction of the rod-shaped n + type region 201.

  On the other hand, as shown in FIGS. 2 and 3, when the other terminal is the n + type region 202, the shape is formed from the fourth side surface S4 of the rod-shaped n + type region 201 toward the corresponding side surface (bottom surface) of the n + type region 202. Even a current path that deviates from the direction overlapping with the extending direction of the rod-shaped n + region 201 may be present. In the present embodiment, the current paths formed in the direction deviating from the direction overlapping with the extending direction of the rod-shaped n + region 201 in this way are all second current paths I2.

  In the case of the n + type region 202, the metal layer may not be disposed as shown in FIGS. When the metal layer contacts the n + -type region 202, an ohmic metal layer (ohmic junction) or a Schottky metal layer (Schottky junction) may be used.

  A connection example of the protection element 200 will be described with reference to FIG. FIG. 4A shows a case where the protected element 100 is a GaAs MESFET, FIG. 4A is a plan view, FIG. 4B is a cross-sectional view taken along the line gg of FIG. 4A, and FIG. FIG. 4A is an equivalent circuit diagram.

  4A and 4B, the protected element 100 is a MESFET, and a gate electrode that forms a Schottky junction with the operation layer 62 provided on the GaAs surface which is the semi-insulating substrate 101 (203). 67, a source region 64 and a drain region 63 made of high-concentration impurity regions provided at both ends of the operation layer 62, and a source electrode 66 and a drain electrode 65 provided on the surface thereof. These are arranged in a shape in which comb teeth are engaged with the operation region 68.

  The gate electrode 67, the source electrode 66, and the drain electrode 65 are connected to the gate pad GP, the source pad SP, and the drain pad DP through the wiring 130, respectively. These are connected to the gate terminal G, the source terminal S, and the drain terminal D, respectively. Further, an n + type impurity region is formed below each pad to improve isolation.

  The source pad SP and the gate pad GP are arranged close to each other, and the metal layer 201M protrudes vertically from the side of the opposing pad. The metal layer 201M is in contact with a rod-shaped n + type region 201 that is provided on the lower substrate and serves as a terminal of the protection element 200.

  In addition, a wiring 130 from the gate pad GP to the drain pad DP is formed, and a metal layer 201M protruding from the wiring 130 and a rod-shaped n + region 201 that contacts the metal layer 201M are disposed. An n + -type peripheral high-concentration impurity region is formed below the drain pad to improve isolation, and this is used as another n + -type region 202 of the protection element 200.

  Thereby, the protection element 200 can be connected between the gate terminal G and the source terminal S and between the gate terminal G and the drain terminal D.

  4B and 4C, in the MESFET, the gate terminal G side is made negative between the gate terminal G and the source terminal S or between the gate terminal G and the drain terminal D having a small gate Schottky junction capacitance. When applying a surge voltage, it is most vulnerable to electrostatic breakdown. In this case, static electricity is applied in a reverse bias to the Schottky barrier diode 61 formed at the interface between the operation region 68 and the gate electrode 67 provided on the surface of the operation region 68.

  In other words, protection from electrostatic breakdown may be achieved by reducing the electrostatic energy applied to the Schottky junction of the gate electrode 67 which is a weak junction. Therefore, in the present embodiment, the protection element 200 is connected in parallel between the two terminals of the MESFET 100, and this serves as a bypass for partially discharging the electrostatic energy applied between the corresponding two terminals. By providing a path, the weak joint is protected from electrostatic breakdown.

  Here, FIG. 4 is an example of connection, and for example, a pattern in which the rod-shaped n + type region 201 and the metal layer 201M protrude from the drain pad DP toward the wiring 130 may be used.

  Further, in the MESFET, since the gate Schottky junction is most vulnerable to electrostatic breakdown, an example in which a protective element is connected between the gate terminal G and the source terminal S and between the gate terminal G and the drain terminal D is shown. Alternatively, a protective element may be connected in parallel between the source terminal S and the drain terminal D.

  Furthermore, the protected element 100 is not limited to a MESFET, and the protective element 200 may be connected to a junction FET having a pn junction, a silicon bipolar transistor (such as an npn transistor), a capacitor, a MOSFET, or the like.

  Hereinafter, with reference to FIG. 5 to FIG. 13, the point that the protective effect is greatly improved by making at least one of the protection elements 200 a rod-shaped n + type region 201 and contacting the metal layer 201 </ b> M will be described in detail with reference to simulation results. .

  In recent years, semiconductor device simulation technology has been developed, and it has become possible to perform detailed simulation not only on the electrical characteristics of devices but also on electrostatic breakdown. As a result, it has become possible to appropriately design a protection element as a countermeasure against electrostatic breakdown.

  Specifically, first, charges are accumulated in the capacitor at a predetermined voltage by a mixed mode simulation. Then, while monitoring the temperature of the crystal, the charge is discharged to both ends of the element to be measured. It is assumed that the device breakdown occurs when the temperature of the crystal reaches about 80% of the temperature at which the crystal melts, and simulates the electrostatic breakdown level of the element under measurement in the machine model.

More recently, the electrostatic breakdown level was measured by the TLP (Transmission Line Pulse) method as another electrostatic breakdown strength level evaluation method, and it was found that the measured value easily coincided with the TLP simulation value at the same time. Have been bathed.
In this specification, first, an electrostatic breakdown level in a machine model is simulated in a mixed mode. Then, the physical state of the protective element at the time of electrostatic breakdown is analyzed in detail using a TLP simulation. Then, by combining these simulations, it will be explained that a protection element having a low parasitic capacitance and an excellent electrostatic breakdown protection level can be designed.

  FIG. 5 is a diagram showing the structure used for the simulation when the protection element 200 (hereinafter referred to as “a structure”) in which both terminals shown in FIG. 1 are rod-shaped n + type regions 201 is designed. 5A is a perspective view, and FIG. 5B is a cross-sectional view taken along the line hh of FIG. 5A.

In the a structure, a rod-shaped n + type region 201 of 3 × 10 ¹⁸ cm ⁻³ is arranged at a separation distance of 4 μm on a silicon substrate 101 having an impurity concentration of 5 × 10 ¹⁴ cm ^{−3 and} a thickness of 50 μm to be an anode electrode and a cathode electrode. A metal layer 201M is formed. With this level of impurity concentration, the silicon substrate 101 substantially functions as the insulating region 203.

  The width w1 of the first side surface S1 of the rod-shaped n + type region 201 is 3 μm, and the width w2 of the contact portion of the metal layer 201M is 2 μm. In addition, the depth (for example, the gate width in the case of an FET) as a device size in the simulation was calculated at 1 μm.

  Moreover, the simulation method performed is as follows.

  In the simulation of the above machine model, 1000 V was applied at 200 pF, and the current value at the time of failure was calculated. Specifically, the value of the current flowing between the cathode and the anode when the temperature reached 1350 K at any location inside the crystal was calculated. This current value is the current value that flows in the first current path I1 during electrostatic breakdown as it is.

  The current value at the time of electrostatic breakdown obtained by the machine model simulation is used for TLP simulation. In the TLP simulation, this current value was instantaneously applied to the protective element, and the electron current density distribution at that time was calculated.

  FIG. 5C shows the result. That is, the value of current that flows when the a structure reaches breakdown in the machine model evaluation method is shown. The first current path I1 is 1.19 A when the width w1 = 1 μm, and 3.57 A, which is three times as large as the width w1 = 3 μm.

  FIG. 6 is a distribution of electron current density and hole current density in the cross section of the hh line when 1.19 A is applied in the TLP simulation (a structure having a width w1 = 1 μm).

In the electron current density distribution of FIG. 6A, the p0 region has the highest density among the regions extending over the two rod-shaped n + type regions 201 (electron current density 1.0 × 10 ⁷ cm ^{−3 to} 1.8 ×. 10 ⁷ cm ⁻³ ) region. Here, the sum of the electron current and the hole current is the total current, but the electron current is larger than the hole current. In other words, in this embodiment, an electron current is a representative current, and a region (p0 to p5 region) having an electron current density of 1 × 10 ⁵ cm ⁻³ or more is defined as a current path of the protection element 200. That is, this region is a first current path I1 region and a second current path I2 region indicated by arrows in FIGS.

  The reason why the current path up to the p5 region is used is that when the current value is calculated by integrating the electron current density in the depth direction, it is found that about 90% of the total current value flows from the p0 region to the p5 region. This is because the region where the electron current density is smaller than the p5 region is considered not to affect the operation.

  Since the drawing is a cross-sectional view taken along the line hh of the protection element 200, it is a cross-sectional view of the electron current density of the first current path I1. Thus, the first current path I1 is formed so as to overlap with the rod-shaped n + type region 201 and expand in the substrate depth direction. The hole current density distribution in FIG. 6B is similar to that in FIG. Therefore, the electron current density distribution was used to calculate the current value flowing through the second current path I2. It should be noted that the Hall current density distribution and the electron current density distribution almost coincide with each other when the electrostatic current flows, conductivity modulation occurs over the entire area of the current path, and the electrostatic current value has increased. Show.

  FIG. 7 is the same diagram as the electron current density distribution diagram of FIG. 6A, and a diagram obtained by rotating the diagram by 180 degrees, and a rod-shaped n + region 201 is arranged between them. It is a top view showing electron current density distribution. Although the first current path I1 and the second current path I2 are formed, the first current path I1 is mostly a rod-shaped n + region 201 except for the current path between the first side surfaces S1, which are opposing surfaces. Are not shown in the figure.

  On the other hand, the second current path I2 is formed on the outside of the first current path I1 from the second side surface S2 of the rod-shaped n + type region 201 toward the second side surface S2 of the rod-shaped n + type region 201 facing the second current path I2. It can be seen that I2 is spreading greatly.

  In the plan view, the current path is from the p0 region to the p5 region. As described above, when the other terminal is the n + type region 202, the extending direction of the rod-shaped n + region 201 even in the current path from the fourth side surface of the rod-shaped n + region 201 to the bottom surface of the n + region 202. There is a current path that deviates from In the plan view shown in FIG. 7, all current paths formed deviating from the extending direction of the rod-shaped n + type region 201 are the second current paths I2.

  FIG. 8 is a perspective view showing the first current path I1 and the second current path I2 of the a structure. The region where the electrostatic current actually flows is distributed in a three-dimensional region obtained by rotating the electron current density distribution diagram of FIG. 6A around the rod-shaped n + type region 201, and is the region shown in FIG. Here, between the first side surface S1 and the fourth side surface S4 of the bar-shaped n + type region 201 with hatching, the current path in the extending direction of the bar-shaped n + type region 201 is the first current path I1, and the first current The current path formed outside the path I1 is the second current path I2. This figure shows why the current flowing through the second current path I2 is much larger than the current flowing through the first current path I1.

  FIG. 9 is a diagram illustrating the second current path I2 based on the simulation. 9A is a cross-sectional view of the X = 0 plane of FIG. 8 (see FIG. 5B), and shows a current value calculated by dividing the second current path I2 from the rod-shaped n + region 201 every 10 μm. It is. FIG. 9B shows the calculation result. FIG. 6 and FIG. 7 are two-dimensional representations of the electron current density and the hole current density in the p0 to p5 regions where the density values are divided at regular intervals.

  Both the machine model simulation and the TLP simulation are two-dimensional simulations. The current flowing through the first current path I1 is a two-dimensional current, but the current flowing through the second current path I2 is a three-dimensional current. That is, by integrating and rotating the electron current density distribution obtained by the TLP simulation, the electron current density distribution data is converted into a current value and three-dimensionalized, and the current value flowing through the second current path I2 is calculated.

  That is, as shown in FIG. 9A, the electron current density distribution of FIG. 6A is integrated and rotated, and the current value of the three-dimensional current in the second current path I2 is calculated and expressed for each of the I21 to I25 regions. .

  As shown in FIG. 9B, the current value of the second current path I2 is the sum of the first region I21 to the fifth region I25, and the width w1 = 1 μm and 3 μm are both 25.4A. Thus, even if the actual calculation results are compared, the current flowing through the first current path I1 is 3.57 A, whereas the current flowing through the second current path I2 is 25.4 A, which is the first current path I1. It was clarified that the current was much larger than the current flowing through.

  The sum of the first current path I1 and the second current path I2 is a current value that can flow through the protection element 200 having the a structure, and is 26.59 A when the width w1 = 1 μm, and 28.97 A when the width w1 = 3 μm. .

  FIG. 10 shows the results of a simulation similar to the above performed with a pn junction diode. FIG. 10A is a cross-sectional view of the structure used for the simulation of the pn junction diode, and FIG. 10B is a distribution diagram of electron current density.

As shown in FIG. 10A, the simulation structure of the pn junction diode is as follows. The n-type region 502 (impurity concentration 1 × 10 5) is formed from a surface to a depth of 0.2 μm on a 50 μm thick silicon substrate with an impurity concentration 5 × 10 ¹⁴ cm ^{−3. 17} cm ⁻³ ), and a p + type region 501 of 3 × 10 ¹⁸ cm ⁻³ is formed to a depth of 0.02 μm from the surface so as to form a junction with the n-type region 502 over a distance of 4 μm. . A cathode electrode 504 and an anode electrode 503 are formed. As a result of a machine model simulation with a depth of 1 μm, it was found that the diode was destroyed at 0.45 A.

  FIG. 10B is a cross-sectional view of the electron current density distribution when 0.45 A is applied in the TLP simulation, and it can be seen that the electron current is concentrated in the vicinity of the pn junction. That is, the first current path I1 does not spread, and the temperature of the high-density portion of the current at 0.45 A per 1 μm depth becomes 80% of the silicon melting temperature, resulting in electrostatic breakdown. Normally, a pn junction diode is designed only with a current that passes perpendicularly through the pn junction surfaces of the p + -type region 501 and the n-type region 502, and no space is particularly secured around the diode. is not. For this reason, a current path corresponding to the second current path I2 of the protective element 200 is hardly formed, and even if formed, the simulation result is not affected.

  Furthermore, similar simulations were performed for the n + / i / n + structures shown in FIGS.

  FIG. 11 is a view of the structure of FIG. 3 as seen from an angle, representing the structure of FIG. 2 and FIG. 3 (referred to as the “b structure”) in the protective element 200 having the rod-shaped n + type region 201 of the present embodiment. The n + type region 202 serving as another terminal has a structure in which the surface facing the rod-shaped n + type region 201 has a width of 50 μm on the left and right sides, and here, the metal layer 206 is contacted. The rest is the same as the a structure.

  Further, FIG. 12 shows an example of a structure in which the facing surface (corresponding to the first side surface S1 of the present embodiment) is wide (long distance). The conventional protection element 360 shown in FIGS. 25 and 26 has a long distance between the opposing surfaces in order to enhance the protection effect. In order to compare this structure with the protection element 200 of the present embodiment, calculation was performed with the structure of FIG.

  First, FIG. 12A shows the simplest structure of n + / i / n + by making the resistance of the n + type region below the pad and the resistance of the n + type region face each other over a long distance. Since this structure is a two-dimensional structure, a certain width may be cut out to simulate it as one unit. That is, in the application patterns as shown in FIGS. 12B and 12C, the number of units corresponding to the size of each shape is estimated, and the number of units is multiplied by the value of one unit. calculate.

  In the simulation, the n + type region 350 below the pad of FIG. 25 and two n + type regions 510 corresponding to the resistance R are arranged to face each other with a separation distance (w12) of 4 μm, and the width w13 of one n + type region 510 is set to the resistance R. The calculation was made with an equivalent 3 μm. The simulation was performed with the width w11 = 1 μm of the pattern as one unit. This one-unit structure is referred to as a c structure.

  Since the calculated value of the pattern in FIG. 12 is proportional to the distance of the opposing surface, the d structure (FIG. 12B) corresponding to the INPad portion in FIG. The calculated value of the e structure (FIG. 12C) corresponding to is obtained by multiplication. That is, the distance between the opposing surfaces in the case of FIG. 12B is 80 μm, which is 80 times of one unit, and the distance of the opposing surfaces in FIG. 12C is 60 μm, which is 60 times of one unit.

  The above calculation is for the first current path I1. FIG. 12B shows only the first current path I1, and the calculated value is the current value. On the other hand, in the case of FIG. 12C, a side current path I '(corresponding to the second current path I2 of the present embodiment) is included at the end of the opposing surface. Therefore, the calculated value of the second current path I2 is added to the calculated value of the first current path I1. The side current path I 'will be described later.

  FIG. 13 is a table summarizing the simulation results of all the protection element structures described so far. Each of the current values flowing at the time of electrostatic breakdown and the cause of deteriorating the performance of the protection element parasitic on the protection element. Capacitance values are being compared. The capacity value is a capacity value when 0 V is applied between the anode and the cathode.

  As described above, the current value of the first current path I1 per 1 μm of the protection element 200 (a structure, b structure) having the rod-shaped n + type region 201 of this embodiment as at least one terminal is 1.19A. In the second current path I2, the a structure is 25.4A and the b structure is 28.4A.

  Further, the width w1 of the rod-shaped n + type region 201 was also compared between the case of 3 μm, which is a general process design rule, and the case of 1 μm, which is a fine process design rule.

  As a performance index of the electrostatic breakdown protection element, “current value / capacitance value” indicating how much a large current can flow with a low parasitic capacitance value can be considered. The larger this index is, the higher the performance of the protection element. Comparing the index by structure, the diode is very small as 0.049, 11.3 for the c structure and d structure, and 15.0 for the e structure.

  Here, since the current path I ′ between the side surfaces of the n + type region 510 is formed in the e structure as shown in FIG. 26, a high performance index is shown in the conventional structure, but the width where the n + type region 510 is opposed is long. The capacitance value becomes as high as 6.76 fF.

  However, in the present embodiment, even if the width is 3 μm by a general process, a high performance index of 69.0 for the a structure and 59.2 for the b structure is shown. Furthermore, if the width of the fine process is 1 μm, it is 190 for the a structure and 164 for the b structure, and it is clear that the protection element has very high performance. Although the b structure has a slightly lower performance than the a structure, the shape of the n + -type region 202 to be another terminal can be made freely, so that the occupied area can be reduced compared to the a structure and there is an advantage that a little more current can flow. .

  Hereinafter, the e structure in which the side current path is formed, and the a structure and b structure of the present embodiment will be further compared and described.

  In an actual device, as shown in FIG. 25, the e structure has a part of the resistor R formed in another n + type region close to the n + type region 350 below OUT-1 Pad, and a protection element 360 having an n + / i / n + structure. Is formed. At this time, by reducing the width w13 of the resistor R to 3 μm, the opposite surface and bottom surface of the n + type region below the OUT-1 Pad, the opposite surface of the resistor R, and the side surface opposite to the bottom surface and the opposite surface can be used. A large current path (hereinafter, main current path I) can be formed (FIGS. 12C and 26). Thereby, although the metal layer does not overlap the resistor R, the parasitic capacitance is suppressed to be relatively small, and electrostatic energy is discharged in the protective element in the middle of the signal path from the control terminal to the gate electrode 317. The electrostatic breakdown voltage of the protective element can be improved. The main current path I increases in proportion to the distance between the opposing surfaces. In other words, the e structure aims to increase the electrostatic breakdown voltage by increasing the distance between the opposing surfaces. For convenience of layout in which the resistor R needs to be routed, a current path I 'is also formed on the side surfaces along with the main current path I as shown in FIG. At this time, the current path I 'is a current path formed by chance due to continuity of resistance.

  The switch circuit device is a pattern for transmitting a signal from the control terminal pad Ctl-1Pad to the gate electrode 317 via a resistor formed in the n + type region. That is, in FIG. 25, the protection element 360 can be connected in the course of the path from the control terminal to the gate electrode 317 without overlapping the metal layer on the n + -type region (resistance R).

  In other words, it can be said that the protection element 360 having the e structure can be realized only by the pattern of the switch circuit device as shown in FIG.

  In addition, since the e structure aims at increasing the electrostatic breakdown voltage by increasing the distance between the opposing surfaces, the parasitic capacitance becomes very large. Although this parasitic capacitance is not a problem in a switch circuit device using a GaAs MESFET having a large off-capacitance as a key device, the switch IC using a pHEMT having a small off-capacitance as a key device deteriorates high-frequency characteristics such as insertion loss and isolation. The problem of end up occurs.

  On the other hand, the a structure and b structure of the present embodiment make the distance between the opposing surfaces necessary for the e structure very small.

  As already mentioned, the development of device simulation technology has made it possible to grasp in detail the situation of electron current density distribution and hole current density distribution when static electricity is applied.

  Specifically, capacity calculation by mixed mode simulation, which was impossible in the past, calculation of electrostatic breakdown voltage of machine model by mixed mode simulation, calculation of electron current density distribution of electrostatic current by TLP method, hole current density This is because the distribution can be calculated.

  The present applicant performed a detailed simulation as described above for the side current path I 'formed along with the main current path of the e structure. As a result, it was found that the current path I 'on the side surface has a capability of flowing an extremely large electrostatic current as compared with the main current path I.

  Therefore, in this embodiment, the opposing surface is made minute as in the a structure and the b structure, and the metal is superposed. As a result, a huge electrostatic current can be passed while the parasitic capacitance is extremely small. Furthermore, since the rod-shaped n + type region 201 and the metal layer 201M can be arranged in a very small space, there is almost no pattern restriction like the e structure, and the versatility of the connection of the protection element 200 can be greatly improved.

  In the d structure, the actual measured value of the electrostatic breakdown voltage of the actual device (FIG. 25) was 1800V. When this shape is simulated by a machine model, the current value is 99.2A as shown in the figure. These two numerical values are considered to be proportional, and 1800 / 99.2 = 18.1 (V / A) is a proportional coefficient between the electrostatic breakdown voltage actual measurement value and the machine model simulation current value. This proportionality factor is used when designing the protection element from the required electrostatic breakdown voltage, which will be described later.

  A second embodiment of the present invention will be described with reference to FIGS. The second embodiment is an example in which the protective element 200 of the first embodiment is connected to a compound semiconductor SPDT (Single Pole Double Throw) switch circuit device. FIG. 14 is a circuit schematic diagram, and FIG. This is a switch circuit device in which a circuit is integrated on one chip.

  As shown in FIG. 14, the switch circuit device of the second embodiment is a basic SPDT switch circuit device, and the source electrodes (or drain electrodes) of the first FET 1 and the second FET 2 are connected to the common input terminal IN. The gate electrodes of FET1 and FET2 are connected to first and second control terminals Ctl1 and Ctl2 via resistors R1 and R2, respectively, and the drain electrodes (or source electrodes) of FET1 and FET2 are first and second, respectively. Are connected to the output terminals OUT1 and OUT2.

  The control signals applied to the first and second control terminals Ctl1 and Ctl2 are complementary signals, and the FET on the side to which the H level signal is applied is turned ON, and the input signal applied to the common input terminal IN is changed. The signal is transmitted to one of the output terminals. The resistors R1 and R2 are arranged for the purpose of preventing high-frequency signals from leaking through the gate electrode with respect to the DC potential of the control terminals Ctl1 and Ctl2 that are AC grounded.

  When passing a signal through the output terminal OUT1, for example, 3V is applied to the control terminal Ctl1, and 0V is applied to the control terminal Ctl2. Conversely, when passing a signal through the output terminal OUT2, a bias signal of 3V is applied to the control terminal Ctl2 and 0V is applied to Ctl1. is doing.

  As shown in FIG. 15, FET 1 and FET 2 for switching are arranged on the substrate at the center. In the present embodiment, a case where the basic device is a HEMT will be described as an example. A plurality of pads P are arranged around the substrate and around the FET1 and FET2. Specifically, the pad P is a pad IC, O1, O2, C1, C2 corresponding to the common input terminal IN, the first and second output terminals OUT1, OUT2, and the first and second control terminals Ctl1, Ctl2. Resistors R1 and R2 are connected to the gate electrode of each FET. The second metal layer indicated by a dotted line is a gate metal layer (Pt / Mo) 20 formed simultaneously with the formation of the gate electrode 17 of each FET. A third metal layer indicated by a solid line is a pad metal layer (Ti / Pt / Au) 25 for connecting each element and forming a pad. The first metal layer is an ohmic metal layer (AuGe / Ni / Au) that is ohmicly bonded to the substrate, and forms the source electrode, drain electrode, and extraction electrodes at both ends of each resistor. It is not shown because it overlaps the metal layer.

  The gate electrode 17 of the FET 1 and the control terminal pad C1 are connected by a resistor R1, and the gate electrode 17 of the FET 2 and the control terminal pad C2 are connected by a resistor R2.

  The pad metal layer 25 of the nine third metal layers having a comb shape extending toward the center of the chip is the drain electrode 16 (or source electrode) connected to the output terminal pad O1, and below this is the first layer. There is a drain electrode (or a source electrode) formed of an ohmic metal layer as an eye metal layer. Further, a pad metal layer 25 of nine third metal layers having a comb shape extending outward from the center of the chip is a source electrode 15 (or drain electrode) connected to the common input terminal pad IC. There is a source electrode (or drain electrode) formed of an ohmic metal layer of the first metal layer.

  These two electrodes are arranged in a shape in which comb teeth are engaged with the operation region 12, and a gate electrode 17 formed of the gate metal layer 20 of the second metal layer is arranged in the shape of 17 comb teeth.

  The operation region 12 is provided on the substrate 30 as indicated by a dashed line. A source region and a drain region are formed in the operation region 12 and are connected to the source electrode 15 and the drain electrode 16, respectively. The gate electrode 17 forms a Schottky junction with the surface of the operation region 12 between the source region and the drain region.

  The gate electrode 17 of the FET 1 has its comb teeth bundled by the gate wiring 120 outside the operation region 12 and is connected to the control terminal pad C1 through the resistor R1. Similarly, the comb electrode teeth of the gate electrode 17 of the FET 2 are bundled by the gate wiring 120 and connected to the control terminal pad C2 through the resistor R2. The resistors R1 and R2 are each formed by a high concentration impurity region.

  Each pad P is formed of a pad metal layer 25, and a peripheral high-concentration impurity region 150 (indicated by a two-dot chain line) connected to the pad P in a direct current manner is arranged below each pad P to improve isolation. The peripheral high-concentration impurity region 150 is directly connected to each pad P and is provided on the entire surface under the pad P (or around the pad P) so as to protrude from the pad P. Further, it may be provided around the pad P at a distance of about 5 μm or less and connected in a direct current manner through the substrate. If the separation distance is about 5 μm or less, it can be said that the pad P and the peripheral high-concentration impurity region 150 are sufficiently DC connected.

  For the same reason, a peripheral high-concentration impurity region 150 connected to the gate wiring 120 in a direct current manner is disposed around the gate wiring 120, and the gate wiring 120 is similar to the gate electrode 17 in the substrate and Schottky. A junction is formed. Also in this case, the gate wiring 120 is provided on the entire lower surface (or the lower periphery of the gate wiring 120) from the gate wiring 120 or at a distance of about 5 μm or less from the gate wiring 120.

  In the common input terminal pad IC, a metal layer 201M protrudes perpendicularly to one side of the pad, and a rod-shaped n + type region 201 is provided immediately below the metal layer 201M. Further, the control terminal pad C1 also has a metal layer 201M protruding perpendicularly to one side of the pad, and a rod-shaped n + type region 201 is provided immediately below the metal layer 201M.

  As described above, in the switch circuit device according to the present embodiment, the metal layer 201M protruding from the common input terminal pad IC is in contact with the rod-shaped n + type region 201 and becomes one terminal of the protection element 200. That is, the common input terminal pad IC also serves as the electrode pad 201P of the protection element 200, and one terminal of the protection element 200 is electrically connected to the common input terminal IN. Similarly, the control terminal pad C1 also serves as the electrode pad 201P of the protection element, and the other terminal of the protection element 200 is electrically connected to the control terminal Ctl1.

  The output terminal pad O1 also has a metal layer 201M projecting perpendicularly to one side of the pad, and a bar-shaped n + region 201 is provided immediately below the metal layer 201M. The output terminal pad O1 also serves as the electrode pad 201P of the protection element, and one terminal of the protection element 200 is electrically connected to the output terminal OUT1. Further, the resistor R1 connected to the control terminal pad C1 extends in a direction orthogonal to the vicinity of the rod-shaped n + type region 201 connected to the output terminal pad O1. That is, the resistor R1 serves as the other terminal on which the rod-shaped n + type region 201 of the protection element 200 is disposed so as to be opposed. Thus, the n + type region 202 which becomes the other terminal does not have to be in direct contact with the metal layer, and the n + type region 202 is electrically connected to the control terminal Ctl1 through the control terminal pad C1.

  It should be noted that the second side surface S2 of the rod-shaped n + type region 201 and the metal layer 201M need only have a length of about 10 μm to 50 μm as in the output terminal pad O1 portion of the figure, and the connecting portion with the pad P has a wide shape. It may be.

  Thereby, the protection element 200 can be connected between the common input terminal IN and the control terminal Ctl1 and between the control terminal Ctl1 and the output terminal OUT1 of the switch circuit device.

  The HEMT substrate structure will be described with reference to the cross-sectional view of FIG. 16A is a cross-sectional view taken along line ii in FIG. 15, FIG. 16B is a cross-sectional view taken along line j-j in FIG. 15, and FIG. 16C is a cross-sectional view taken along line kk in FIG.

The HEMT substrate 30 is formed by laminating a non-doped buffer layer 32 on a semi-insulating GaAs substrate 31. The buffer layer 32 is often formed of a plurality of layers. Then, an n ⁺ AlGaAs layer 33 serving as an electron supply layer, a non-doped InGaAs layer 35 serving as a channel (electron travel) layer, and an n ⁺ AlGaAs layer 33 serving as an electron supply layer are sequentially stacked on the buffer layer 32. A spacer layer 34 is disposed between the electron supply layer 33 and the channel layer 35.

On the electron supply layer 33, a non-doped AlGaAs layer 36 serving as a barrier layer is stacked to ensure a predetermined breakdown voltage and a pinch-off voltage, and an n ⁺ GaAs layer 37 serving as a cap layer is stacked on the uppermost layer. A metal layer such as a pad, a source electrode, and a drain electrode (or a resistance extraction electrode) is connected to the cap layer 37, and the impurity concentration is increased to a high concentration (about 1 to 5 × 10 ¹⁸ cm ⁻³ ). Resistance and drain resistance are reduced to improve ohmic properties.

In the HEMT, electrons generated from donor impurities in the n ⁺ AlGaAs layer 33 serving as an electron supply layer move to the channel layer 35 side, and a channel serving as a current path is formed. As a result, electrons and donor ions are spatially separated with the heterojunction interface as a boundary. Although electrons travel through the channel layer 35, the channel layer 35 does not have donor ions that cause a decrease in electron mobility, and thus has a very low influence of Coulomb scattering and can have high electron mobility.

In this specification, the high-concentration impurity region of HEMT means a region where a cap layer (described later) is exposed by being isolated by an insulating region. The insulating region is not electrically completely insulated, but is an insulated region in which an impurity (B ⁺ ) is ion-implanted to provide a carrier trap level in the epitaxial layer as shown in the figure. For example, the operation region 12 is formed by separating the region indicated by the alternate long and short dash line in FIG. Impurities are also present in the insulating region as an epitaxial layer, but are inactivated by B ⁺ implantation. It is assumed that the insulating region 203 of the protection element 200 is formed by the above insulating region.

That is, the HEMT forms a necessary pattern by separating the substrate by the insulating region 203 selectively formed on the substrate. Therefore, the structure of the source region 37s, the drain region 37d, the peripheral high concentration impurity region 150, and the resistance is the same as the HEMT epitaxial layer structure, and the cap layer 37 (impurity concentration of about 1 to 5 × 10 ¹⁸ cm ⁻³ ) is used. Therefore, it can be said to be a high concentration impurity region functionally.

  A source electrode 45 and a drain electrode 46 formed of an ohmic metal layer of the first metal layer are connected to the cap layer 37 of the substrate that becomes the source region 37 s or the drain region 37 d in the operation region 12. A source electrode 15 and a drain electrode 16 are formed on the upper layer by a pad metal layer 25.

  Further, a part of the operation region 12, that is, the cap layer 37 between the source region 37s and the drain region 37d is etched, and the gate formed by the gate metal layer 20 of the second metal layer on the exposed non-doped AlGaAs layer 36. The electrode 17 is disposed.

  As described above, in the FET, the electrostatic breakdown voltage is lowest at the Schottky junction between the gate electrode 17 and the operation region 12. That is, when the electrostatic energy applied between the gate and drain terminals or between the gate and source terminals reaches the gate Schottky junction, the reached electrostatic energy is between the gate electrode and the source electrode or between the gate electrode and the drain electrode. When the electrostatic breakdown voltage is exceeded, the gate Schottky junction is destroyed.

  In the present embodiment, the protective element 200 is connected between the common input terminal IN and the control terminal Ctl1 and between the output terminal OUT1 and the control terminal Ctl1 of the switch circuit device, so that it is applied between the common input terminal IN and the control terminal Ctl1. The electrostatic energy can be attenuated before the electrostatic energy reaches between the gate electrode 17 and the drain electrode 16 of the FET 1 or between the gate electrode 17 and the source electrode 15.

  FIG. 16B shows that the two terminals of the protective element 200 are both rod-shaped n + type regions 201 (a structure). In this case, the metal layer overlapping the rod-shaped n + type region 201 from the common input terminal pad IC and control terminal pad C1. 201M protrudes. In this case, the metal layer 201M is formed of the pad metal layer 25.

  That is, the common input terminal pad IC and the control terminal pad C1 also serve as the electrode pads 200P of the protection element 200, respectively. The two terminals of the protection element 200 are spaced apart by a distance of 4 μm across the insulating region 203.

  As a result, the protective element 200 is connected between the common input terminal IN and the control terminal Ctl1, that is, between the source and gate terminals (or between the drain and gate terminals) of the FET 1, and the electrostatic energy applied during this period is attenuated. Can be made.

  Further, by connecting between the common input terminal pad IC and the control terminal pad C1, static electricity can be discharged at the earliest stage.

  In FIG. 16C, only one terminal of the protective element 200 has a structure of the rod-shaped n + type region 201 (b structure). The resistor R <b> 1 is a high-concentration impurity region that is isolated by forming the insulating region 203, and a part of the resistor R <b> 1 is used as the n + -type region 202 that serves as the other terminal of the protection element 200.

  In other words, the two terminals of the protective element 200 are spaced apart by a distance of 4 μm across the insulating region 203, and between the control terminal Ctl1 and the output terminal OUT1, that is, between the drain and gate terminals (or between the source and gate terminals) of the FET1. ) Is connected to the protective element 200.

  Further, it can be connected on the way from the control terminal pad C1 to which a signal is applied to the operation region. As a result, the electrostatic energy applied between the control terminal Ctl1 and the output terminal OUT1 is consumed as a part of heat by the resistor R1, and further consumed by the discharge in the protective element 200, until reaching the operation region 12. It can be attenuated below the breakdown voltage of the operating region 12.

  17 and 18 show another embodiment of the switch circuit device of FIG. 17 is a plan view, and FIGS. 18A and 18B are cross-sectional views taken along lines l-l and m-m in FIG. 17, respectively.

  When only one terminal of the protective element 200 has the rod-shaped n + type region 201, the n + type region 202 serving as the other terminal is not limited to the resistor R <b> 1 but may be the peripheral high concentration impurity region 150. That is, it is a structure in which one terminal of the protective element 200 protrudes toward the pad P or a structure in which one terminal of the protective element 200 protrudes from the pad P.

  For example, on the FET1 side in FIG. 17, the rod-shaped n + type region 201 of the protection element 200 is disposed to face one side of the peripheral high concentration impurity region 150 of the common input terminal pad IC. That is, the control terminal pad C1 also serves as one electrode pad 201P of the protection element 200, and the metal layer 201M that overlaps the rod-shaped n + type region 201 protrudes from the control terminal pad C1. One terminal of the protection element 200 is connected to the control terminal Ctl1.

  The other terminal of the protection element 200 is a part of the peripheral high-concentration impurity region 150 of the common input terminal pad IC, and this is used as the n + -type region 202. That is, in this case, the other terminal of the protection element 200 is electrically connected to the common input terminal IN.

  Thereby, the electrostatic energy applied between the common input terminal IN and the control terminal Ctl1 can be attenuated to a voltage lower than the breakdown voltage of the operation region 12.

  Similarly, the rod-shaped n + type region 201 of the protection element 200 is arranged to face one side of the peripheral high concentration impurity region 150 of the output terminal pad O1. In this case, a metal layer 201 </ b> M that overlaps the rod-shaped n + type region 201 protrudes from the metal wiring 130 connected to the gate wiring 120. In this case, the metal wiring 130 and the metal layer 201M are formed by the pad metal layer 25, and the rod-shaped n + type region 201 is electrically connected to the control terminal Ctl-1 via the resistor R1.

  The other terminal of the protective element 200 is a part of the peripheral high-concentration impurity region 150 of the output terminal pad O1, and this is used as the n + -type region 202. That is, in this case, the other terminal of the protective element is electrically connected to the output terminal OUT1.

  That is, by arranging the rod-shaped n + type region 201 and the peripheral high concentration impurity region 150 with a separation distance of 4 μm across the insulating region 203, the protective element is provided between the gate and drain terminals of the FET 1 and between the gate and source terminals. 200 can be connected.

  In this way, by connecting the two terminals of the switch circuit device in parallel with the two terminals of the protective element, most of the electrostatic energy applied from the outside between the two terminals is discharged inside the protective element. Almost all electrostatic energy applied from outside can be consumed. In other words, the protected element can be protected from static electricity by greatly reducing the electrostatic energy that enters the protected element.

  Furthermore, between the two terminals, the width of the opposing surface is very small, so that the second current path has a capability of flowing a huge electrostatic current even though it has very little parasitic capacitance. It has an electric breakdown protection effect.

  In particular, in the case of HEMT, the insertion loss of the basic device is smaller than that of GaAsFET. Therefore, if there is a portion where a high-frequency signal leaks even a little in the high-frequency signal path in the chip, the insertion loss as a switch circuit device increases. Becomes prominent. Further, the insulating region 203 is not electrically completely insulated but a depletion layer extends into the insulating region 50, and a signal leaks due to the change of the depletion layer.

  However, according to the present embodiment, the capacitance component at this portion can be reduced by reducing the area of the opposing surface of the protection element 200. Therefore, leakage of high frequency signals can be prevented, and electrostatic breakdown can be prevented while reducing insertion loss.

  In addition, by connecting the protection element 200 having the a structure between the pads, it is possible to discharge at the initial stage where static electricity is applied. Further, by connecting the protection element 200 having the b structure using the resistance R, the electrostatic energy is consumed as a part of the heat by the resistance R1, and further consumed by the discharge of the protection element 200 until reaching the operation region 12. In addition, it can be attenuated to a voltage lower than the breakdown voltage of the operation region 12.

  In the figure, a single-layer structure of only the pad metal layer 25 is shown, but each pad P may have a two-layer structure in which the gate metal layer 20 and the pad metal layer 25 are laminated in this order on the substrate.

  As described above, the rod-shaped n + type region 201 serving as a terminal of the protection element 200 can be arranged by using, for example, the pads of the switch circuit device. In the switch circuit device, the wiring 130 also serves as the wiring 201W to which the rod-shaped n + type region 201 is connected, and the terminal pads IC, C1, O1, etc. also serve as the electrode pad 201P of the protection element 200. When the other terminal is an n + type region 202 that is not a rod-shaped n + type region 201, the peripheral high concentration impurity region 150 or the resistance R of each pad (or wiring) can be used. Therefore, the occupation area on the chip of the protection element 200 can be reduced.

  In the wireless communication market such as cellular phones, there is a need for guaranteeing an electrostatic breakdown voltage value of 100 V or more with a machine model. Conventionally, since a pHEMT switch capable of guaranteeing an electrostatic breakdown voltage value of 100 V or more cannot be realized, for example, an external inductor is attached to the common input terminal IN and the output terminal OUT to prevent the pHEMT switch IC from being electrostatically damaged. .

  However, when an inductor is externally attached, there is a problem that matching is shifted and insertion loss is increased, a mounting area is increased, and an inductor is relatively expensive compared to a capacitor and a resistor, resulting in an increase in cost.

  Since the switch IC cannot measure and sort the electrostatic breakdown voltage at the time of shipment, there is only a method to meet the market needs of the electrostatic breakdown voltage value of 100V with the design guarantee, but about 800V is necessary to guarantee 100V. It is.

  Here, as described above, in the d structure of FIG. 12B, the proportional coefficient of the current value that is the proportional coefficient of the electrostatic breakdown voltage actual measurement value and the machine model simulation current value was 18.1 (V / A). . That is, in order to guarantee the electrostatic breakdown voltage of 800 V, a protective element capable of a machine model simulation current value of 800 / 18.1 (proportional coefficient) = 44.2 A is required. Generally, the protection effect increases as the size of the protection element increases, and it is easy to obtain a machine model simulation current value of 44.2A.

  However, if the size of the protection element is simply increased, the insertion loss may deteriorate due to the parasitic capacitance of the protection element. That is, it is a problem to increase the insertion loss of the pHEMT switch characterized by the low insertion loss due to the connection of the protective element.

  Specifically, the off capacitance of the pHEMT switch is about 90 fF, and if it is not a protective element having a negligible parasitic capacitance, for example, about 1 fF or less with respect to this capacitance value, the insertion loss increases due to the connection of the protective element. become. For example, when the pHEMT switch is formed in the pattern shown in FIG. 25, the insertion loss is increased by 0.15 dB at 2 GHz as compared with the insertion loss of the original pHEMT switch.

  In the pattern of FIG. 25, a protection element having a d structure is connected between the common input terminal pad INPad and the control terminal pad Ctl-1Pad or between the common input terminal pad INPad and the control terminal pad Ctl-2Pad. Also, an e-structure protection element is connected between the control terminal pad Ctl-2Pad and the output terminal pad OUT-1Pad or between the control terminal pad Ctl-1Pad and the output terminal pad OUT-2Pad.

  The capacitance values of the d-structure and e-structure protection elements are 8.8 fF and 6.76 fF, respectively (see FIG. 13). Thus, when the capacitance value becomes a level that cannot be ignored with respect to the OFF capacitance 90 fF of the pHEMT switch, the insertion loss increases.

  That is, a protection element having a current value / capacitance value of 44 (A) / 1 (fF) = 44 or more is required. In the protection element 200 of this embodiment, either the a structure or the b structure can satisfy this requirement.

  For example, a current value of 28.97 × 2 = 57.94 A can be obtained by connecting two a structures each having a width w1 = 3 μm of the rod-shaped n + type region 201 in parallel. Further, the capacitance value is 0.42 × 2 = 0.84 fF and 1 fF or less, and both the current value and the capacitance value can satisfy the above requirements.

  Similarly, a current value of 31.97 × 2 = 63.94 A can be obtained by connecting two b structures having a width w1 = 3 μm in parallel. The capacitance value is also 0.54 × 2 = 1.08 fF and a capacitance value close to 1 fF, and both the current value and the capacitance value can satisfy the above requirements.

  When the control terminal Ctl1 is connected to the gate electrode of the FET2, the control terminal Ctl2 is connected to the gate electrode of the FET1, and a signal is passed to the output terminal OUT1, for example, 3V is applied to the control terminal Ctl2, and 0V is applied to the control terminal Ctl1. Conversely, when a signal is passed through the output terminal OUT2, a reverse type switch circuit device in which a bias signal of 3V is applied to the control terminal Ctl1 and 0V is applied to Ctl2 can be similarly implemented.

  Although the case where the insulating region 203 is an HEMT insulating region has been described as an example, the present invention can also be applied to a silicon substrate by forming an insulating region by implanting or diffusing impurities in the substrate. The insulating region may be polysilicon.

  15 and 17 can also be applied to MESFETs having a substrate of GaAs. Therefore, the protection element 200 may be connected to the MMIC using MESFETs. Since the GaAs substrate is a semi-insulating substrate, in this case, an n + type region is formed in the GaAs substrate by ion implantation or the like.

  FIG. 19 illustrates a third embodiment of the present invention. The protection element 200 according to the first embodiment can also be connected to an integrated circuit device (hereinafter referred to as LSI) having a logic circuit using a MOSFET or the like as a basic element.

  FIG. 19 is a plan view, and the semiconductor device of the present invention is obtained by integrating a logic circuit element and a protection element on the same substrate. Specifically, a logic circuit region 103 arranged in the central portion, The protection element region 102 provided on the outer periphery of the circuit region 103 and the wirings 111 and 112 extending outside the logic circuit region 103 are provided. The logic circuit is connected to the power supply terminal Vcc or the ground terminal GND by the first wiring 111 (inner wiring connected to the power supply terminal pad V) and the second wiring 112 (outer wiring connected to the ground terminal pad G). The

  The logic circuit region 103 is disposed near the center of the semiconductor device, and the power supply wiring and the GND wiring are connected to the power supply terminal pad V, the ground terminal pad G, and the wirings 111 and 112, respectively. The logic circuit region 103 is a CMOS logic circuit configured by, for example, an n-channel MOSFET and a p-channel MOSFET.

  A plurality of input / output terminal pads IO for signals connected to the logic circuit are arranged in the protection element region 102 surrounding the logic circuit region 103. In the input / output terminal pad IO, a metal layer 201M protrudes perpendicularly to one side of the pad, and a rod-shaped n + type region 201 is provided immediately below the metal layer 201M.

  Thus, in the integrated pattern, the metal layer 201M protruding from the input / output terminal pad IO of the logic circuit element contacts the rod-shaped n + region 201 and becomes one terminal of the protection element 200. That is, the input / output terminal pad IO is electrically connected to the input / output terminal also serving as the electrode pad 201P of the protection element 200.

  A peripheral high-concentration impurity region 150 is also formed around the first wiring 111 and the second wiring 112, and the rod-shaped n + type region 201 of the protective element serves as the other terminal (n + type region 202) arranged to face each other. That is, the other terminal is also electrically connected to the power supply terminal Vcc or the ground terminal GND by using the wiring connected to the power supply terminal Vcc or the ground terminal GND.

  Also in the case of LSI, the rod-shaped n + type region 201 is provided so as to protrude from the metal layer 201M at least in a portion where the metal layer 201M contacts the rod-shaped n + type region 201. That is, in the case of GaAs and SiLSI, the distance between the edge of the rod-shaped n + type region 201 and the contact portion edge of the metal layer 201M is set so that the depletion layer does not reach the opposite edge from either edge in normal operation. To design. The distance between the edge of the rod-shaped n + -type region 201 and the contact portion edge of the metal layer 201M is sufficient to be 0.2 μm.

  As a result, the protective element 200 is connected between the power supply terminal and the input / output terminal of the logic circuit element, and between the ground terminal and the input / output terminal of the logic circuit element, and static electricity entering the logic circuit can be prevented.

  The n-channel type MOSFET and the p-channel type MOSFET constituting the CMOS logic circuit have a structure in which the gate oxide film becomes thinner and the gate length becomes shorter as the performance improves, and the structure is vulnerable to electrostatic breakdown. Therefore, by disposing the protective element region around the logic circuit region, the static electricity can be discharged before the static electricity enters the logic circuit region.

  Conventionally, a protection element region in which a CMOS buffer circuit type protection circuit in which ggnMOS (gate grounded nMOS) and ggpMOS (gate grounded pMOS) are connected is disposed is very large compared to the logic circuit region. However, according to the present embodiment, it is only necessary to project the rod-shaped n + type region 201 from the input / output terminal pad toward the surrounding first wiring 111 and second wiring 112, and a large electrostatic current can flow. Therefore, the area of the protection element region can be reduced. Further, since the parasitic capacitance is small, the protected element (LSI) can be surely protected from static electricity without reducing the calculation processing speed of the logic circuit element.

  In the case of a silicon LSI in which logic circuit elements and protection elements are integrated on one chip as described above, it is often difficult to form the insulating region 203 in the bulk. In such a case, high-resistance polysilicon may be provided in the protective element region 102, and the protective element 200 having an n + / i / n + structure may be formed therein.

  In the above example, the protection element 200 protrudes from the input / output terminal pad IO toward both the first wiring 111 and the second wiring 112, but only in the direction of the first wiring 111 and only in the direction of the second wiring 112. A protruding pattern may be used. As a result, the protection element 200 is connected between the input / output terminal and the power supply terminal if it protrudes in the direction of the first wiring 111, and the connection is made between the input / output terminal and the ground terminal in the direction of the second wiring 112. become.

  Although not shown, the chip 160 is formed with a passivation film such as a silicon nitride film, a silicon oxide film, and a polyimide-based insulating film so as to cover a pad provided in the periphery. Is open for.

  For example, the chip 160 is die-bonded to the island of the lead frame with an adhesive, and the power supply terminal pad V, the ground terminal pad G, and the input / output terminal pad IO on the surface of the chip 160 are wire-bonded at one end of a bonding wire such as a gold wire. The other end of the bonding wire is wire-bonded by stitch bonding to the tip of the corresponding lead for leading out.

  In this way, an integrated circuit having a plurality of input / output terminals, a power supply terminal, and a ground terminal is used as a protected element, and is connected in parallel with two terminals of the protective element 200 to two terminals of the protected element. As a result, most of the electrostatic energy applied from the outside between the two terminals is discharged inside the protective element 200, and the electrostatic energy applied from the outside inside the protective element 200 can be almost consumed. In other words, the protected element can be protected from static electricity by greatly reducing the electrostatic energy that enters the protected element.

  Furthermore, between the two terminals, the width of the opposing surface is very small, so that the second current path has a capability of flowing a huge electrostatic current even though it has very little parasitic capacitance. It has an electric breakdown protection effect.

  20 to 23 show a fourth embodiment. The fourth embodiment has a structure in which a chip 180 in which a protection element 200 is integrated on an LSI is provided on an LSI.

  FIG. 20 is a perspective view. As shown in the figure, the semiconductor device has a structure in which a logic circuit element and a protection element are formed as individual chips and stacked on a frame or the like.

  Specifically, as shown in the figure, the lower layer chip 170 is a chip on which logic circuits are integrated, and the upper layer chip 180 is a chip 180 on which protection elements 200 are integrated. The lower layer chip is fixed on the island 190, and the upper layer chip 180 is disposed on the lower layer chip 170. The logic circuit element is a CMOS logic circuit as in FIG. 19, and a GND wiring 112 and a ground terminal pad G connected to the ground terminal are formed around the chip. Further, a power supply terminal pad V and an input / output terminal pad IO are arranged inside the GND wiring 112, and each pad or the GND wiring 112 is connected to a logic circuit. Although illustration is omitted, the power supply wiring 111 is disposed below the upper chip.

  In the chips 170 and 180, a passivation film such as a silicon nitride film, a silicon oxide film, and a polyimide insulating film is formed so as to cover a pad provided in the periphery, and the upper part of the pad is opened for bonding connection. Yes.

  The input / output terminal pad IO, the ground terminal pad G, and the power supply terminal pad V are arranged near the pads and connected to the corresponding leads 191 by bonding wires 192 or the like, as in FIG.

  The protection element 200 has a plurality of rod-shaped n + regions 201 formed on a semiconductor substrate, and a metal layer 201M protruding from the electrode pad 201P or the wiring 201W is in contact with the rod-shaped n + region 201.

  The electrode pad 201P of the protection element 200 is also connected to the lead 191 disposed in the vicinity of each pad by a bonding wire 192 or the like, similarly to the logic circuit element in the lower layer. Thereby, the power supply terminal pad V, the ground terminal pad G, the input / output terminal pad IO of the lower layer chip 170 and the electrode pad 201P connected to the corresponding terminal of the protection element are electrically connected.

  For example, the metal layer 201M protrudes from the wiring 201W1 extending in the center of the chip and contacts the rod-shaped n + type region 201. The wiring 201W1 is connected to the lead 191 to which the Vcc potential is applied via the electrode pad 201P1.

  The metal layer 201M protrudes from a plurality of electrode pads 201P3 arranged on both sides of the wiring 201W1, and contacts the rod-shaped n + type region 201. The electrode pad 201P3 is connected to the input / output terminal pad IO, and is connected to the lead 191 to which the input / output signal is applied.

  Further, the wiring 201W2 arranged around the chip of the protective element is also in contact with the rod-shaped n + type region 201 and connected to the ground terminal pad G through the electrode pad 201P2 provided at the corner portion, and a ground potential is applied. Connect to lead 191.

  As a result, the protection elements are connected between the Vcc-input / output terminal of the logic circuit element and the GND-input / output terminal of the two terminals, respectively, and static electricity entering the logic circuit can be prevented.

  In the case of a stacked mounting structure, the upper layer chip can be a chip having only a protective element, and there is no need to consider any substrate specifications and processes necessary for the logic circuit. Therefore, an insulating region necessary for the protective element can be easily obtained. Since it is chip-on-chip, the pads of the protected elements corresponding to the protective elements can be arranged close to each other, and an efficient layout becomes possible. Further, since the chip area and the chip mounting area can be reduced, the outer size can be reduced.

  FIG. 21 to FIG. 23 are pattern examples of the protection element chip 180 serving as the upper layer chip. FIG. 21 shows a case where both terminals of the protection element are rod-shaped n + type regions 201, FIG. 21A is a chip plan view, and FIG. 21B is an enlarged view of the protection element 200.

  The center is a wiring 201W1 and an electrode pad 201P1 connected to a power supply terminal, and both sides thereof are an electrode pad 201P3 connected to an input / output terminal. The wiring 201W2 and the electrode pad 201P2 arranged around the chip are connected to the ground terminal.

  The two terminals of the protection element 200 are both rod-shaped n + type regions 201, and the parasitic capacitance is very small while obtaining a sufficient protection effect. In other words, the calculation processing speed of the logic circuit is not reduced at all.

  In such a case, the second current path I2 is formed as shown by the arrow in FIG. 21B, but static electricity is applied simultaneously between the adjacent protection elements 200 (that is, different input / output terminals of the logic circuit—power supply or ground terminal). There are few cases to do. Therefore, a necessary area can be shared between adjacent protection elements 200, and an increase in chip area can be suppressed even when a large number of protection elements 200 are formed on a substrate.

  FIG. 22 shows a rod-shaped n + type region in which one terminal protrudes toward the pad, and the other terminal is a pad. FIG. 22A is a chip plan view, and FIG. 22B is an enlarged view of the protective element 200.

  The center is a wiring 201W1 and an electrode pad 201P1 connected to a power supply terminal, and both sides thereof are an electrode pad 201P3 connected to an input / output terminal. The wiring 201W2 and the electrode pad 201P2 arranged around the chip are connected to the ground terminal.

  As shown in the figure, the electrode pad 201P3 connected to the input / output terminal does not have the rod-shaped n + type region 201. In such a case, as shown in FIG. 22B, the second current path I2 is formed using the n + type region 202 provided around the pad and a part of the other side close to the rod-shaped n + type region 201. The As is clear from comparison with FIG. 21, the area as the protection element 200 can be greatly reduced.

  FIG. 23 shows a case where one terminal is a rod-shaped n + type region protruding from a pad and the other terminal is a wiring. FIG. 23A is a chip plan view, and FIG. 23B is an enlarged view of the protective element 200.

  The center is a wiring 201W1 and an electrode pad 201P1 connected to a power supply terminal, and both sides thereof are an electrode pad 201P3 connected to an input / output terminal. The wiring 201W2 and the electrode pad 201P2 arranged around the chip are connected to the ground terminal.

  As shown in the drawing, the wirings 201W1 and W2 connected to the power supply terminal and the ground terminal do not have the rod-shaped n + type region 201. In such a case, as shown in FIG. 23B, the second current path I2 is formed using the n + type region 202 provided around the wiring adjacent to the rod-shaped n + type region 201. Since the other terminal is continuous, a region necessary as a protection element can be effectively used as compared with the above figure.

It is (A) top view, (B) sectional view, (C) sectional view, (D) top view explaining a protection element of the present invention. It is (A) top view, (B) sectional drawing, (C) top view explaining the protection element of this invention. It is (A) top view, (B) sectional drawing, (C) top view explaining the protection element of this invention. It is (A) top view, (B) sectional drawing, (C) circuit schematic diagram explaining the protection element of this invention. It is (A) perspective view, (B) sectional drawing, and (C) simulation result explaining the protection element of this invention. It is a figure which shows the simulation result of the protection element of this invention. It is a figure which shows the simulation result of the protection element of this invention. It is a figure explaining the current pathway of the protection element of the present invention. It is the (A) conceptual diagram explaining the current path | route of the protection element of this invention, (B) It is a simulation result. It is a figure explaining the simulation of this invention. It is a figure explaining the simulation of this invention. It is a figure explaining the simulation of the conventional structure. It is a figure which compares the simulation result of the conventional structure and this invention. It is a circuit diagram of a semiconductor device of the present invention. It is a top view explaining the semiconductor device of this invention. It is sectional drawing explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is sectional drawing explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a perspective view explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a top view explaining the semiconductor device of this invention. It is a figure explaining a prior art. It is a figure explaining a prior art. It is a figure explaining a prior art. It is a figure explaining a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 12 Operation area | region 17 Gate electrode 16, 46 Drain electrode 15, 45 Source electrode 20 Gate metal layer 25 Pad metal layer 30 Substrate 31 Semi-insulating GaAs substrate 32 Buffer layer 33 Electron supply layer 35 Channel (electron travel) layer 34 Spacer layer 36 Barrier layer 37 Cap layer 37s Source region 37d Drain region 66 Source electrode 65 Drain electrode 63 Drain region 64 Source region 67 Gate electrode 62 Operation layer 68 Operation region 61 Schottky barrier diode 100 Protected device 102 Protection device region 103 Logic circuit region 111 , 112 wiring 120 gate wiring 130 wiring 150 peripheral high concentration impurity region 170 LSI chip 180 protection element chip 190 island 191 lead 192 bonding wire 200 protection element 01 Rod-shaped n + type region 202 N + type region 201W, 201W1, 201W2 wiring 201P, 201P1, 201P2, 201P3 Electrode pad 201M Metal layer 203 Insulating region 205 Insulating film 206 Metal layer 301 Bonding pad 302, 304 Electrode wiring 315 Source 317 Gate 320 Drain 350 n + type region 360 protection element 401 p channel type MOSFET
402 n-channel MOSFET
407 Protection element region 408 Logic circuit 501 p-type region 502 n-type region 503 anode electrode 504 cathode electrode 510 n-type region I1 first current path I2 second current path S1 first side surface S2 second side surface S3 third side surface S4 fourth Side IC, INPad Common input terminal pad C1, C2, Ctl-1Pad, Ctl-2Pad Control terminal pad O1, O2, OUT-1Pad, OUT2-Pad Output terminal pad IN Common input terminal Ctl1, Ctl2 Control terminal OUT1, OUT2 Output terminal R1, R2 Resistance V Power terminal pad G Ground terminal pad IO I / O terminal pad Vcc Power terminal GND Ground terminal D1, D2 Diode

Claims (26)

Two high-concentration impurity regions disposed opposite to the substrate, and an insulating region disposed around the two high-concentration impurity regions,
At least one of the high-concentration impurity regions is a first side surface that is a minute facing surface of the other high-concentration impurity region, and is sufficiently large with respect to the first side surface and spaced apart from the first side surface in a substantially vertical direction. A second side surface extending in the form of a bar, a third side surface in contact with a metal layer exposed from the substrate and projecting from the electrode pad or wiring, and a fourth side surface facing the third side surface,
The two high-concentration impurity regions are connected as two terminals between the two terminals of the protected element, and the one high-concentration impurity region is connected from the first side surface and the fourth side surface to the corresponding side surface of the other high-concentration impurity region. A first current path serving as a path for electron current and hole current formed in the insulating region in the extending direction of the concentration impurity region; and the other high concentration impurity region from the second side surface outside the first current path. A protective element, wherein electrostatic energy applied between two terminals of the protected element is attenuated by a second current path serving as a path of an electron current and a hole current formed in the insulating region toward.   The protection element according to claim 1, wherein the other high-concentration impurity region is disposed around another electrode pad or another wiring.   2. The protection element according to claim 1, wherein a current value of the second current path is five times or more of a current value of the first current path.   The protective element according to claim 1, wherein a width of the high concentration impurity region on the first side surface is 5 μm or less.   By connecting a pair of the high-concentration impurity regions as the two terminals between the two terminals of the protected element, the electrostatic breakdown voltage of the protected element is 300 V or more in the machine model and the parasitic between the two terminals The protective element according to claim 1, wherein a capacitance value is 0.7 fF or less.   The protection element according to claim 1, wherein the second current path is formed with a width of 15 μm or more from the second side surface. At least one FET having a source electrode, a gate electrode and a drain electrode connected to an operating region on the substrate; at least one input terminal connected to the source electrode or drain electrode of the FET; and a drain electrode or source electrode of the FET A switch circuit element having at least one output terminal connected to the terminal, and a terminal for applying a DC potential to the FET;
Two high-concentration impurity regions disposed opposite to the substrate, and an insulating region disposed around the two high-concentration impurity regions,
At least one of the high-concentration impurity regions is a first side surface that is a minute facing surface of the other high-concentration impurity region, and is sufficiently large with respect to the first side surface and spaced apart from the first side surface in a substantially vertical direction. A second side surface that extends from the substrate, a third side surface that is exposed from the substrate and is electrically connected to any one of the terminals, and a metal layer that protrudes from the wiring and is in contact with the third side surface, and the third side surface A bar having a fourth side facing
A protective element having two terminals of the two high-concentration impurity regions is connected between the two terminals of the switch circuit element, and extends from the first side surface and the fourth side surface to the corresponding side surface of the other high-concentration impurity region. A first current path serving as a path for electron current and hole current formed in the insulating region in the extending direction of the one high-concentration impurity region, and the other side from the second side surface outside the first current path. The electrostatic energy applied between the two terminals of the switch circuit element is attenuated by a second current path that is a path for electron current and hole current formed in the insulating region toward the high concentration impurity region. Semiconductor device. First and second FETs having a source electrode, a gate electrode, and a drain electrode connected to an operation region on the substrate are formed, and a terminal connected to the source electrode or drain electrode common to both FETs is used as a common input terminal, and both FETs The terminals connected to the drain electrode or the source electrode are first and second output terminals, respectively, and the terminals connected to either of the FET gate electrodes are first and second control terminals, respectively. A signal is applied, and one of the FETs is made conductive through a resistor which is a connection means for connecting the two control terminals and the gate electrode, and the common input terminal and any of the first and second output terminals A switch circuit element that forms a signal path with either of them,
Two high-concentration impurity regions disposed opposite to the substrate, and an insulating region disposed around the two high-concentration impurity regions,
At least one of the high-concentration impurity regions is a first side surface that is a minute facing surface of the other high-concentration impurity region, and is sufficiently large with respect to the first side surface and spaced apart from the first side surface in a substantially vertical direction. A second side surface that extends from the substrate, a third side surface that is exposed from the substrate and is electrically connected to any one of the terminals, and a metal layer that protrudes from the wiring and is in contact with the third side surface, and the third side surface A bar having a fourth side facing
A protective element having two terminals of the two high-concentration impurity regions is connected between the two terminals of the switch circuit element, and extends from the first side surface and the fourth side surface to the corresponding side surface of the other high-concentration impurity region. A first current path serving as a path for electron current and hole current formed in the insulating region in the extending direction of the one high-concentration impurity region, and the other side from the second side surface outside the first current path. The electrostatic energy applied between the two terminals of the switch circuit element is attenuated by a second current path that is a path for electron current and hole current formed in the insulating region toward the high concentration impurity region. Semiconductor device.   9. The semiconductor device according to claim 8, wherein the other high-concentration impurity region is a part of the connection means.   The semiconductor device according to claim 8, wherein the protection element is connected between at least one of the control circuit element and the common input terminal.   9. The other high-concentration impurity region is disposed around another electrode pad or another wiring that is electrically connected to one of the terminals of the switch circuit element. A semiconductor device according to 1.   9. The semiconductor device according to claim 7, wherein a current value of the second current path is five times or more of a current value of the first current path.   9. The semiconductor device according to claim 7, wherein a width of the high-concentration impurity region on the first side surface is 5 μm or less.   By connecting the protective element having a parasitic capacitance value of 0.7 fF or less between the two terminals of the switch circuit element with the pair of high-concentration impurity regions as both terminals, 9. The semiconductor device according to claim 7, wherein the electrostatic breakdown voltage is 300 V or more in a machine model.   9. The semiconductor device according to claim 7, wherein the second current path is formed with a width of 15 μm or more from the second side surface. An integrated circuit element having a plurality of input / output terminals, a power supply terminal and a ground terminal;
A protective element having two high-concentration impurity regions disposed opposite to the substrate and an insulating region disposed around the two high-concentration impurity regions;
At least one of the high-concentration impurity regions is a first side surface that is a minute facing surface of the other high-concentration impurity region, and is sufficiently large with respect to the first side surface and spaced apart from the first side surface in a substantially vertical direction. A second side surface that extends from the substrate, a third side surface that is exposed from the substrate and is electrically connected to any one of the terminals, and a metal layer that protrudes from the wiring and is in contact with the third side surface, and the third side surface A bar having a fourth side facing
The two high-concentration impurity regions are connected as two terminals between two terminals of the integrated circuit element, and the one high-concentration impurity region extends from the first side surface and the fourth side surface to the corresponding side surface of the other high-concentration impurity region. A first current path serving as a path for electron current and hole current formed in the insulating region in the extending direction of the concentration impurity region; and the other high concentration impurity region from the second side surface outside the first current path. A semiconductor device characterized in that electrostatic energy applied between two terminals of the integrated circuit element is attenuated by a second current path that is a path of an electron current and a hole current formed in the insulating region toward the substrate.   The semiconductor device according to claim 16, wherein the integrated circuit element is a CMOS logic circuit element.   The semiconductor device according to claim 16, wherein the integrated circuit element and the protection element are integrated on the same substrate.   The semiconductor device according to claim 16, wherein the protection element is disposed on the integrated circuit element.   17. The semiconductor device according to claim 16, wherein the wiring is a first wiring connected to a power supply terminal of the integrated circuit element and a second wiring connected to the ground terminal.   17. The semiconductor device according to claim 16, wherein the protection element is connected to at least one of the input / output terminal and the power supply terminal and the input / output terminal and the ground terminal of the integrated circuit element.   17. The semiconductor device according to claim 16, wherein the other high-concentration impurity region is provided in the vicinity of another electrode pad or wiring connected to any one of the terminals of the integrated circuit element.   The semiconductor device according to claim 16, wherein a current value of the second current path is five times or more of a current value of the first current path.   The semiconductor device according to claim 16, wherein a width of the high concentration impurity region on the first side surface is 5 μm or less.   By connecting the protection element having a parasitic capacitance value of 0.7 fF or less between the two terminals of the integrated circuit element by using the pair of high-concentration impurity regions as both terminals, The semiconductor device according to claim 16, wherein the electrostatic breakdown voltage is 300 V or more in a machine model. The semiconductor device according to claim 16, wherein the second current path is formed with a width of 15 μm or more from the second side surface.

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