JP2006067565A - Method of switching pll characteristics and pll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a PLL circuit where operation noise is reduced in the case of improving quick responsiveness by raising a natural angular frequency in the case of frequency pull-in. <P>SOLUTION: A loop filter which is a component of the PLL circuit includes a switching element 17 for switching a capacitance value which connects and disconnects a capacitive element Cz2 to a capacitive element Cz1 according to a switching signal 16, and a switching element 18 for switching a resistance value which short-circuits and opens between both ends of a resistance element Rz1 according to the natural angular frequency switching signal 16 in order to keep a damping factor at a constant value. It further includes an operational amplifier for charging the capacitive element Cz2 at the same potential as the capacitive element Cz1 when the capacitive element Cz2 is isolated from the capacitive element Cz1. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention mainly relates to a PLL characteristic switching method and a PLL circuit that can realize a reduction in operation noise of the PLL circuit.

  FIG. 12 is a block diagram showing a configuration of a prior art PLL circuit. FIG. 13 is a circuit diagram showing a configuration of a loop filter, that is, a low-pass filter, which is one of the components of the PLL circuit of FIG. FIG. 14 is a timing chart showing the operation of the PLL circuit of FIG.

  In this PLL circuit, as shown in FIG. 12, the divided signal 6 obtained by dividing the output signal 9 of the voltage controlled oscillator 1 by 1 / M by the variable frequency divider 2 and the reference signal 7 output from the temperature compensated crystal oscillator 11. Is detected by the phase comparator 3. A voltage pulse having a pulse width corresponding to the phase difference between the frequency-divided signal 6 and the reference signal 7 detected by the phase comparator 3 is sent from the phase comparator 3 to the charge pumps 4 and 10. The charge pumps 4 and 10 output a voltage or current corresponding to the output of the phase comparator 3. The charge pump 4 is directly connected to the loop filter 5. The charge pump 10 is connected to the loop filter 5 via a switch element (SW1) 14 that is switched on or off in response to a natural angular frequency switching signal 16. Therefore, when the natural angular frequency switching signal 16 is in the first state, only the output of the charge pump 4 is supplied to the loop filter 5. When the natural angular frequency switching signal 16 is in the second state, both the outputs of the charge pumps 4 and 10 are supplied to the loop filter 5. The outputs of the charge pumps 4 and 10 are smoothed by the loop filter 5 and transmitted to the voltage controlled oscillator 1 as the control voltage 13. At this time, the natural angular frequency ωn of the PLL circuit is different between when only the output of the charge pump 4 is supplied to the loop filter 5 and when both outputs of the charge pumps 4 and 10 are supplied to the loop filter 5. In the latter case, the natural angular frequency ωn is higher than in the former case.

  The natural angular frequency switching signal 16 is also input to the loop filter 5 so that the value of the resistor constituting the loop filter 5 can be switched according to the state of the natural angular frequency switching signal 16. This is to prevent the damping factor ζ of the PLL circuit from changing even if the natural angular frequency ωn is switched by intermittently supplying the output of the charge pump 10 to the loop filter 5 as described above.

  As shown in FIG. 13, the loop filter 5 includes a capacitive element Cp connected between the output terminal of the charge pump 4 and the ground, and a resistor connected between the output terminal of the charge pump 4 and the ground. It comprises a series circuit of elements Rz1, Rz2 and a capacitive element Cz, and a switch element (SW2) 17 connected in parallel to the resistance element Rz2. The switch element (SW2) 17 is switched between on and off according to the state of the natural angular frequency switching signal 16. The output terminal of the charge pump 4 is connected to the control voltage terminal of the voltage controlled oscillator 1 as it is.

  As described above, the output signal 9 of the voltage controlled oscillator 1 is frequency-divided by 1 / M by the variable frequency divider 2 and is fed back to the phase comparator 3 as the frequency-divided signal 6. Therefore, the frequency fo of the output signal 9 of the voltage controlled oscillator 1 is expressed as follows, where M is the frequency division ratio of the variable frequency divider 2 and fref is the frequency of the reference signal 7.

fo = M × fref (1)
Further, the natural angular frequency ωn and the damping factor ζ, which are generally indices of the loop characteristics of the PLL circuit, are expressed as follows.

ωn = (K × ω2) ^1/2
... Formula (2)

ζ = (1/2) × (K ÷ ω2) ^1/2
... Formula (3)
However, ω2 = 1 / (Cz × Rz)
K = (Kvco × Icp × Rz) / (2π × M)
10 × Cp <Cz
Icp: When the switch element (SW1) 14 is on, the charge pumps 4 and 10
When the switch element (SW1) 14 is off,
Output current of charge pump 4 alone
Kvco: Gain of voltage controlled oscillator 1
Rz: resistance elements Rz1, Rz2 when the switch element (SW2) 17 is OFF
When the switch element (SW2) 17 is on, the resistance is
Resistance value of anti-element Rz1 alone
Cz: Capacitance value of the capacitive element Cz Here, it is widely known that the optimum damping factor ζ is approximately 0.7 from the high-speed response of the PLL circuit.

  In this prior art, in order to achieve both high-speed response and high C / N, the natural angular frequency ωn is switched between frequency pull-in and steady-state.

  First, in a steady state, the natural angular frequency switching signal 16 is “L”, the switch element (SW1) 14 is off, and the current supplied to the loop filter 5 is only the output current of the charge pump 4. . Therefore, the natural angular frequency ωn of the PLL circuit is low, and the PLL circuit is in a locked state.

  Thereafter, when the frequency division ratio M of the variable frequency divider 2 is switched, the natural angular frequency switching signal 16 becomes “H” for a certain period from that moment. In response to this natural angular frequency switching signal 16, the switch element (SW1) 14 is turned on. As a result, the current supplied to the loop filter 5 increases to a value obtained by adding the output currents of the charge pumps 4 and 10 to the output current of only the charge pump 4. As a result, the natural angular frequency ωn is increased, and the frequency pull-in operation is performed at high speed. At this time, the switch element (SW2) 17 is turned on. As a result, both ends of the resistance element Rz2 are short-circuited, and the damping factor ζ is adjusted to approximately 0.7, which is the same as in the steady state.

  For example, only at the time of frequency pull-in, the value of the current Icp is quadrupled and the value of the resistance element Rz is halved, so that the natural angle is kept constant from the equations (2) and (3) while keeping the damping factor ζ constant The frequency ωn can be doubled. As a result, frequency and phase acquisition can be completed at high speed.

  Thereafter, the natural angular frequency switching signal 16 is set to “L” to turn off the switch elements (SW1, SW2) 14 and 17 and keep the value of the damping factor ζ constant while keeping the natural angular frequency ωn constant. To achieve high C / N.

FIG. 14 shows the relationship between the change in the frequency fo of the output signal of the voltage controlled oscillator 1 and the change in the natural angular frequency switching signal 16. In the figure, before the time t1, the frequency fo is stable and the PLL circuit is in a locked state. The period from time t1 to time t2 is a frequency pull-in period. A period from time t2 to time t3 is a phase pull-in period. After time t3, the frequency fo is stable and the PLL circuit is in a locked state.
“Substrate Injection and Crosstalk in CMOS Circuits” Bell Laboratories, Lucent Technologies IEEE1999 CUSTOM INTEGRATED CIRCUITS CONFERRENCE

  However, in the configuration of the prior art, as an adverse effect of switching the natural angular frequency ωn, when the natural angular frequency switching signal 16 is “H”, the current supplied to the loop filter 5 is charged from the output current of only the charge pump 4. The output current is increased to the sum of the output currents of the pumps 4 and 10. As a result, the operating current of the PLL circuit also increases, a part of the current flows into the semiconductor substrate, and interferes with other blocks such as a transmitting circuit and a receiving circuit integrated with the PLL circuit on the same semiconductor substrate. Thereby, various characteristics of the transmission / reception circuit are deteriorated. That is, there is a problem that the operation noise of the PLL circuit is large.

  For example, the above interference occurs in the following structure.

FIG. 15 is a cross-sectional view showing the vertical structure of two diodes separated by an insulator. In FIG. 15, reference numeral 101 denotes a P ⁻ type semiconductor Si substrate. Reference numerals 102 and 103 denote P ⁺⁺ type regions formed on the P ⁻ type semiconductor Si substrate 101. Reference numerals 104 and 105 denote N ⁺ -type regions formed on the P ⁺⁺ -type regions 102 and 103, respectively. Reference numeral 106 denotes a separation insulator embedded in the semiconductor Si substrate 101. Reference numeral 107 denotes a parasitic resistance formed between the P ⁺⁺ type regions 102 and 103. Reference numeral 108 denotes a parasitic capacitance formed between the P ⁺⁺ type regions 102 and 103. Such an element causes the interference.

  Accordingly, an object of the present invention is to provide a PLL circuit capable of reducing the operating noise when the natural angular frequency is increased to increase the high-speed response.

  In order to solve the above problems, a PLL characteristic switching method of the present invention includes a voltage controlled oscillator, a phase comparator that compares the phase of an output signal of the voltage controlled oscillator and a reference signal, a capacitor and a resistor. A PLL characteristic switching method for switching a response characteristic of a PLL circuit configured to include at least a loop filter that applies a low frequency component of an output signal to a voltage controlled oscillator as a control voltage, and that operates at a predetermined natural angular frequency and a damping factor. In order to switch the natural angular frequency, the step of switching the capacitance value according to the switching signal and the value of the resistor according to the switching signal in conjunction with the switching of the capacitance value in order to maintain the damping factor at a constant value Switching.

  According to this method, since the natural angular frequency is increased by switching the capacitance value in the loop filter instead of switching the current of the charge pump, the current flowing through the semiconductor substrate on which the PLL circuit is formed Does not increase even if the natural angular frequency is increased in order to obtain high-speed response. Therefore, when the natural angular frequency is increased at the time of frequency pulling to increase the high-speed response, it is possible to reduce the operation noise.

  In addition, the PLL circuit of the present invention includes a voltage controlled oscillator, a phase comparator that compares the phase of the output signal of the voltage controlled oscillator and a reference signal, and a low-frequency component of the output signal of the phase comparator that controls the voltage controlled oscillator. And a loop circuit that operates at a predetermined natural angular frequency and damping factor. The loop filter has a capacitance and resistance series circuit connected to the output terminal of the phase comparator, capacitance switching means for switching the capacitance value in accordance with the switching signal to switch the natural angular frequency, and a constant damping factor. In order to maintain the resistance value, resistance switching means for switching the resistance value in accordance with the switching signal is provided in conjunction with the switching of the capacitance value.

  According to this configuration, since the natural angular frequency is increased by switching the value of the capacitance in the loop filter instead of switching the current of the charge pump, the current flowing through the semiconductor substrate on which the PLL circuit is formed Does not increase even if the natural angular frequency is increased in order to obtain high-speed response. Therefore, when the natural angular frequency is increased at the time of frequency pulling to increase the high-speed response, it is possible to reduce the operation noise.

  In the PLL circuit of the present invention, the capacitor is composed of first and second capacitor elements provided in parallel, and the capacitor switching means is connected between the first capacitor element and the second capacitor element, A capacitance value switching switch element that switches between on and off according to the switching signal, and a charging circuit that charges the second capacitance element to the same potential as the first capacitance element when the capacitance value switching switch element is in the off state. It is preferable to become.

  According to this configuration, when the second capacitive element is connected to the first capacitive element for switching the natural angular frequency, the second capacitive element is charged to the same potential as the first capacitive element. The potential of the connection point between the first capacitor element and the resistor does not fluctuate due to the connection of the second capacitor element to the first capacitor element. Therefore, high-speed response is not impaired.

  In the above configuration, the charging circuit is connected between the voltage follower that receives the potential of the first capacitive element, the output terminal of the voltage follower, and the second capacitive element, and the capacitance value switching switch element is in the OFF state. And a charge control switch element that is conductive when the capacitance value changeover switch element is open, and is opened when the capacitance value changeover switch element is in the ON state. In the above configuration, the voltage follower includes, for example, an operational amplifier whose output terminal is connected to the inverting input terminal.

  The charging circuit is composed of a voltage follower in which the potential of the first capacitive element is input and the output terminal is connected to the second capacitive element, and the voltage follower has a function of being in a high impedance output state, and the capacitance value is switched. It is preferable that a normal output state is obtained when the switch element is in an off state, and a high impedance output state is established when the capacitance value switching switch element is in an on state. In the above configuration, the voltage follower is composed of an operational amplifier whose output terminal is connected to the inverting input terminal, for example.

  In the above PLL circuit, the resistor is directly connected to the first capacitor element, and the second capacitor element is connected to the connection point between the resistor and the first capacitor element via the capacitance value changeover switch element. In the configuration, the charging circuit may have the following configuration. That is, the charging circuit includes an amplifier circuit that amplifies a potential difference appearing between both ends of the resistor with reference to a potential at a connection point between the first capacitor element and the resistor, and between the output terminal of the amplifier circuit and the second capacitor element. And a charge control switch element that conducts when the capacitance value changeover switch element is in the off state and opens when the capacitance value changeover switch element is in the on state.

  The amplifier circuit includes, for example, a first operational amplifier in which an output terminal is connected to an inverting input terminal and a non-inverting input terminal is connected to a connection point between the resistor and the first capacitive element, and an output terminal of the first operational amplifier. A first resistance element connected at one end, an inverting input terminal is connected to the other end of the first resistance element, and a non-inverting input terminal is connected to a terminal opposite to the connection point of the first capacitance element in the resistor The charge control switch element includes a second operational amplifier having an output terminal connected thereto, and a second resistor element connected between the output terminal and the inverting input terminal of the second operational amplifier.

In the above PLL circuit, the resistor is directly connected to the first capacitor element, and the second capacitor element is connected to the connection point between the resistor and the first capacitor element via the capacitance value changeover switch element. In the configuration, the charging circuit may have the following configuration. That is, the charging circuit includes an amplifier circuit that amplifies a potential difference appearing between both ends of the resistor with reference to a potential at a connection point between the first capacitor element and the resistor, and an output terminal of the amplifier circuit is connected to the second capacitor element. Is done. Here, the amplifier circuit has a function of being in a high impedance output state, and is in a normal output state when the capacitance value changeover switch element is in an off state, and in a high impedance output state when the capacitance value changeover switch element is in an on state. For example, the amplifier circuit includes a first operational amplifier in which an output terminal is connected to an inverting input terminal and a non-inverting input terminal is connected to a connection point between the resistor and the first capacitive element, and an output terminal of the first operational amplifier. A non-inverting input terminal at a terminal opposite to the connection point between the first resistance element having one end connected to the first resistance element, an inverting input terminal connected to the other end of the first resistance element, and the first capacitor element at the resistor. A second operational amplifier having an output terminal connected to the charge control switch element and a second resistance element connected between the output terminal and the inverting input terminal of the second operational amplifier.

  In the above-described PLL circuit, the resistor is composed of a series circuit of first and second resistance elements, and the resistance switching means is a resistance value switching circuit connected in parallel to one of the first and second resistance elements. It consists of a switch element. The resistance value changeover switch element is turned off when the capacitance value changeover switch element is turned off, and turned on when the capacitance value changeover switch element is turned on.

  As described above, in the present invention, even when the natural angular frequency of the PLL circuit is set high at the time of frequency pull-in, the PLL circuit is reduced in operating noise. As a result, for example, when circuit blocks other than the PLL circuit such as a transmission circuit and a reception circuit are integrated on the same semiconductor substrate, it is possible to reduce deterioration in characteristics of the transmission / reception circuit due to interference.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
The PLL circuit according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a PLL circuit according to the first embodiment of the present invention. FIG. 2 is a circuit diagram showing the configuration of a loop filter, that is, a low-pass filter, which is one of the components of the PLL circuit of FIG. FIG. 3 is a timing chart showing the operation of the PLL circuit of this embodiment.

  In this PLL circuit, as shown in FIG. 1, the output signal 9 of the voltage controlled oscillator 1 is divided by 1 / M by the variable frequency divider 2 and the reference signal 7 output from the temperature compensation crystal oscillator 11. Is detected by the phase comparator 3. A voltage pulse having a pulse width corresponding to the phase difference between the frequency-divided signal 6 detected by the phase comparator 3 and the reference signal 7 is sent from the phase comparator 3 to the charge pump 4. The charge pump 4 outputs a voltage or current corresponding to the output of the phase comparator 3. The charge pump 4 is directly connected to the loop filter 5. The output of the charge pump 4 is smoothed by the loop filter 5 and transmitted to the voltage controlled oscillator 1 as the control voltage 13.

  The natural angular frequency switching signal 16 is input to the loop filter 5, and the capacitance and resistance values constituting the loop filter 5 are switched according to the state of the natural angular frequency switching signal 16. This is for switching the natural angular frequency ωn while keeping the damping factor ζ of the PLL circuit constant.

  As shown in FIG. 2, the loop filter 5 includes a capacitive element Cp connected between the output terminal of the charge pump 4 and the ground, and a resistor connected between the output terminal of the charge pump 4 and the ground. A series circuit of the elements Rz1, Rz2 and the capacitive element Cz1, an operational amplifier 12 having a non-inverting input terminal connected to a connection point of the resistive element Rz2 and the capacitive element Cz1, and a switching element having one end connected to the output terminal of the operational amplifier 12 ( SW1) 14, a capacitive element Cz2 connected between the other end of the switch element (SW1) 14 and the ground, and a switch connected between the connection point of the resistive element Rz2 and the capacitive element Cz1 and the capacitive element Cz2. It comprises an element (SW2) 17 and a switch element (SW3) 18 connected in parallel to the resistance element Rz1.

  The operational amplifier 12 has an output terminal and an inverting input terminal connected to each other, and constitutes a voltage follower. This voltage follower, together with the switch element (SW1) 14, constitutes a charging circuit that charges the capacitive element Cz2.

  The switch elements (SW1, SW2, SW3) 14, 17, and 18 are switched between on and off according to the state of the natural angular frequency switching signal 16. The output terminal of the charge pump 4 is connected to the control voltage terminal of the voltage controlled oscillator 1 as it is.

  As described above, the output signal 9 of the voltage controlled oscillator 1 is frequency-divided by the variable frequency divider 2 and is fed back to the phase comparator 3 as a frequency-divided signal 6. Therefore, the frequency fo of the output signal 9 of the voltage controlled oscillator 1 is expressed by the equation (1) as in the prior art, where M is the frequency division ratio of the variable frequency divider 2 and fref is the frequency of the reference signal 7. The

  Also in this embodiment, in order to achieve both high-speed response and high C / N, the natural angular frequency ωn is switched between frequency pull-in and steady-state.

  First, in a steady state, the natural angular frequency switching signal 16 is “L”, the switch element (SW1) 14 is turned off, the switch element (SW2) 17 is turned on, and the switch element (SW3) 18 is turned on. Yes. Therefore, the natural angular frequency of the PLL circuit is low, and the PLL circuit is locked.

  Thereafter, when the frequency division ratio M of the variable frequency divider 2 is switched, the natural angular frequency switching signal 16 becomes “H” for a certain period from that moment. In response to the natural angular frequency switching signal 16, the switch element (SW1) 14 is turned on, the switch element (SW2) 17 is turned off, and the switch element (SW3) 18 is turned off. As a result, the capacitance value, which is an element for determining the natural angular frequency ωn, changes from the state of Cz1 + Cz2 to the state of Cz1 only, and the natural angular frequency ωn becomes higher from Equation (2). At this time, the damping factor ζ tends to change as the value of the capacitance, which is an element that determines the damping factor ζ, changes from the state of Cz1 + Cz2 to the state of only Cz1. However, the resistance value, which is another factor that determines the damping factor ζ, changes from the state of Rz2 to the state of Rz1 + Rz2. As a result, even if the natural angular frequency ωn is higher than the expression (3), the damping factor ζ is maintained at a constant value, that is, a value of approximately 0.7. Even at the moment when the PLL circuit is released from the sleep mode, the natural angular frequency switching signal 16 becomes “H”, so the same operation as described above is executed.

  The PLL circuit in which the natural angular frequency ωn is high enters a high-speed response state and converges to the desired control voltage 13 in a short time. In general, when the PLL circuit is in a steady state, the potentials at both ends of the resistance elements Rz1 and Rz2 are almost zero. That is, it means that the control voltage 13 is substantially equal to the potential across the capacitor Cz1. A voltage equal to the voltage of the capacitive element Cz1 is charged to the capacitive element Cz2 via the operational amplifier 12 and the switch element (SW1) 14.

  After a certain fixed time has elapsed, the natural angular frequency switching signal 16 switches to “L”. In response to this signal, the switch element (SW2) 17 is turned on, and the capacitive element Cz2 charged to the same potential as the capacitive element Cz1 is connected in parallel to the capacitive element Cz1. As a result, the value of the capacity which is only Cz1 increases as Cz1 + Cz2, and the natural angular frequency ωn becomes lower than the equation (2). At the same time, the resistance value of Rz2 + Rz1 becomes smaller by Rz1, and the damping factor ζ can be maintained at approximately 0.7 from Equation (3).

  It should be noted that it is sufficient that the natural angular frequency switching signal 16 is “H” as long as the control voltage 13 is approximately the desired voltage, and the output current of the charge pump 4 is capacitively connected to the capacitive element Cz1. The time until the battery is charged to a desired voltage is a guide. Further, the operational amplifier 12 is preferably a CMOS type in order to suppress the input current from degrading various characteristics of the PLL circuit. At the same time, when the voltage of the capacitive element Cz1 is not charged to the capacitive element Cz2 accurately, the frequency stability immediately after the natural angular frequency switching signal 16 is switched from “H” to “L” deteriorates, resulting in high-speed response. There will be an impact. Therefore, the operational amplifier 12 is preferably a low offset voltage type.

  FIG. 3 shows the relationship between the change in the frequency fo of the output signal of the voltage controlled oscillator 1 and the change in the natural angular frequency switching signal 16. In the figure, before the time t1, the frequency fo is stable and the PLL circuit is in a locked state. The period from time t1 to time t2 is a frequency pull-in period. A period from time t2 to time t3 is a phase pull-in period. After time t3, the frequency fo is stable and the PLL circuit is in a locked state.

  The above operations are summarized as follows. In the PLL circuit according to the first embodiment of the present invention shown in FIG. 1 to FIG. 3, switching of the output current of the charge pump 4 is stopped, and the natural frequency from the moment when the frequency division ratio M of the variable frequency divider 2 is switched. When the angular frequency switching signal 16 is “H” for a certain period of time, the switch element (SW1) 14 is turned on and the switch element (SW2) 17 is turned off in response to this signal, so that the capacitive element Cz1 has the same potential as the charged potential. The capacitive element Cz2 is charged so that During this time, the switching element (SW3) 18 is turned off, and the damping factor ζ is adjusted to approximately 0.7 while the natural angular frequency ωn is increased.

  After that, the natural angular frequency switching signal 16 becomes “L”, the switch element (SW1) 14 is turned off and the switch element (SW2) 17 is turned on in response to this signal, and the capacitive element charged to the same potential as the capacitive element Cz1. Cz2 is connected in parallel with the capacitive element Cz1. At the same time, the switch element (SW3) 18 is turned on, and the natural angular frequency ωn is lowered while keeping the damping factor ζ at approximately 0.7. For example, by only doubling the capacitance value Cz and doubling the resistance value Rz only at the time of frequency pull-in, the natural angular frequency ωn can be obtained from the equations (2) and (3) while keeping the damping factor ζ constant. Can be doubled.

  According to this embodiment, the natural angular frequency ωn is increased by switching the capacitance value in the loop filter 5 instead of switching the charge pump current as in the prior art. In order to obtain high-speed response, the current flowing through the semiconductor substrate on which the is formed does not increase even if the natural angular frequency ωn is increased. Therefore, when the natural angular frequency is increased to increase the high-speed response, the operation noise can be reduced.

  Further, when the capacitive element Cz2 is additionally connected to restore the natural angular frequency ωn, the capacitive element Cz2 is additionally connected after charging the capacitive element Cz2 to the same potential as the capacitive element Cz1. For this reason, when the capacitance element Cz1 alone is switched to the parallel circuit of the capacitance elements Cz1 and Cz2, the potential at the connection point between the capacitance element Cz1 and the resistance element Rz2 does not fluctuate. As a result, high-speed response is not impaired.

  In summary, while maintaining high-speed response and high C / N during normal operation, interference with other blocks such as transmission circuits and reception circuits integrated on the same semiconductor substrate is reduced, and various characteristics of transmission / reception circuits are degraded. It can be prevented.

(Second Embodiment)
A PLL circuit according to the second embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 4 is a circuit diagram showing a configuration of a loop filter which is one of the components of the PLL circuit of this embodiment. FIG. 3 is a timing chart showing the operation of the PLL circuit according to the second embodiment.

  In the second embodiment of the present invention, the switch element (SW1) 14 is unnecessary as compared with the first embodiment of the present invention. However, instead, a function is required to prevent the output voltage of the operational amplifier 12 from being transmitted to the capacitive element Cz2. For this reason, the operational amplifier 12 used in the second embodiment of the present invention needs to be able to make its output high impedance (Hi-Z).

  The contents of the operation are the same as those of the first embodiment of the present invention except that the output of the operational amplifier 12 is set to high impedance (Hi-Z) at the timing when the switch element (SW1) 14 is turned off. This is exactly the same as the first embodiment.

  FIG. 5 shows the relationship between the change in the frequency fo of the output signal of the voltage controlled oscillator 1 and the change in the natural angular frequency switching signal 16. In the figure, before the time t1, the frequency fo is stable and the PLL circuit is in a locked state. The period from time t1 to time t2 is a frequency pull-in period. A period from time t2 to time t3 is a phase pull-in period. After time t3, the frequency fo is stable and the PLL circuit is in a locked state.

  According to this embodiment, the same effects as those of the first embodiment can be obtained.

(Third embodiment)
A PLL circuit according to a third embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 6 is a circuit diagram showing the configuration of a loop filter which is one of the components of the PLL circuit of this embodiment.

  This embodiment is structurally different from the first embodiment of the present invention in the following points. That is, in this embodiment, in place of the voltage follower constituted by the operational amplifier 12, a non-inverting amplifier constituted by the operational amplifier 12 and the resistance elements Rop 1 and Rop 2 and a voltage follower constituted by the operational amplifier 8 are used. The non-inverting amplifier and the voltage follower together with the switch element (SW1) 14 form a charging circuit that charges the capacitive element Cz2.

  As shown in FIG. 6, the loop filter 5 includes a capacitive element Cp connected between the output terminal of the charge pump 4 and the ground, and a resistor connected between the output terminal of the charge pump 4 and the ground. A series circuit of the elements Rz1, Rz2 and the capacitive element Cz1, an operational amplifier 8 having a non-inverting input terminal connected to the connection point of the resistive element Rz2 and the capacitive element Cz1, and a resistive element Rop2 having one end connected to the output terminal of the operational amplifier 8 An operational amplifier 12 having an inverting input terminal connected to the other end of the resistance element Rop2, a resistance element Rop1 connected between the output terminal and the inverting input terminal of the operational amplifier 12, and one end connected to the output terminal of the operational amplifier 12. Switch element (SW1) 14, and the capacitive element Cz2 connected between the other end of the switch element (SW1) 14 and the ground, A switch element (SW2) 17 that is connected between the connection point and the capacitive element Cz2 elements Rz2 and a capacitor Cz1, a switch element (SW3) 18 Metropolitan connected in parallel to the resistive element Rz1.

  The non-inverting input terminal of the operational amplifier 12 is connected to the terminal opposite to the capacitive element Cz1 in the series circuit of the resistance elements Rz1 and Rz2, and the operational amplifier 12 has a voltage appearing at both ends of the series circuit of the resistance elements Rz1 and Rz2. Is supplied to the capacitive element Cz2.

  In the operational amplifier 8, an output terminal and an inverting input terminal are connected to each other to constitute a voltage follower.

  The voltage follower and the non-inverting amplifier constitute a charging circuit that charges the capacitive element Cz2 together with the switch element (SW1) 14.

  The switch elements (SW1, SW2, SW3) 14, 17, and 18 are switched between on and off according to the state of the natural angular frequency switching signal 16. The output terminal of the charge pump 4 is connected to the control voltage terminal of the voltage controlled oscillator 1 as it is.

  In the first embodiment of the present invention, when the capacitance value of the loop filter 5 is switched from Cz1 to Cz1 + Cz2, the potential at both ends of the capacitance element Cz1 is directly applied to the capacitance element Cz2 using the voltage follower formed by the operational amplifier 12. Thus, the capacitive element Cz2 was charged, and then the capacitance value was switched to a large value.

  On the other hand, in the third embodiment of the present invention, the PLL circuit charges the capacitive element Cz2 by utilizing the fact that the potentials at both ends of the resistance elements Rz1 and Rz2 are substantially 0 in the steady state. Thereafter, the capacitance value is switched to a larger value.

  When the natural angular frequency switching signal 16 is “H”, the switch element (SW3) 18 is off. At this time, when the potential at the connection point between the capacitive element Cz1 and the resistive element Rz2 is considered as a reference, the potential at both ends of the resistive element Rz2 + Rz1 is VRz, the control voltage 13 is Vt, and the potential of the capacitive element Cz is Vcz. The output voltage Vout of the non-inverting amplifier formed from the resistor elements Rop1 and Rop2 is expressed by the following equation.

Vout = {(Vcz−Vt) / Rop2} × Rop1 + Vt (4)
As the operation of this non-inverting amplifier, the same potential as that of the non-inverting input terminal appears at the inverting input terminal of the operational amplifier 12 due to the effect of an imaginary short of negative feedback. For this reason, a current corresponding to the potential difference between the voltage Vt and the voltage Vcz flows through the resistance element Rop2. This current flows to the resistance element Rop1. As a result, the voltage Vout is as shown in Equation (4). Further, considering that the potentials at both ends of the resistance elements Rz1 and Rz2 become almost zero in the steady state, the PLL circuit means that the potential at both ends of the capacitive element Cz1 appears in the voltage Vout in the steady state. As a result, as in the first embodiment of the present invention, when switching the capacitance value from Cz1 to Cz1 + Cz2, the capacitance element Cz2 is charged to the same potential as that of the capacitance element Cz1, and then the capacitance value is switched to a large value. it can.

  The effect of this embodiment is the same as that of the first embodiment.

(Fourth embodiment)
A PLL circuit according to the fourth embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 7 is a circuit diagram showing the configuration of a loop filter which is one of the components of the PLL circuit of this embodiment.

  In the fourth embodiment of the present invention, the switch element (SW1) 14 is unnecessary as compared with the third embodiment of the present invention. However, instead, a function is required to prevent the output voltage of the operational amplifier 12 from being transmitted to the capacitive element Cz2. For this reason, the operational amplifier 12 used in the fourth embodiment of the present invention needs to be able to make its output high impedance.

  The contents of the operation are the third embodiment of the present invention except that the output of the operational amplifier 12 is set to high impedance at the timing when the switch element (SW1) 14 is turned off in the third embodiment of the present invention. Is exactly the same.

  The effect of this embodiment is the same as that of the first embodiment.

(Fifth embodiment)
A PLL circuit according to a fifth embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 8 is a circuit diagram showing the configuration of a loop filter which is one of the components of the PLL circuit of this embodiment.

  In the fifth embodiment of the present invention shown in FIG. 8, the circuit connection of the resistance elements Rz1, Rz2 and the capacitive element Cz1 connected in series is compared with the first to fourth embodiments of the present invention. , It is opposite to the ground. That is, the resistor element Rz1 is grounded, and the capacitor element Cz1 is connected to the output terminal of the charge pump 4. However, the operation is exactly the same as in the first embodiment of the present invention, and when switching the capacitance value, which is a basic requirement, from Cz1 to Cz1 + Cz2, the capacitive element Cz2 is charged to the same potential as the capacitive element Cz1. After that, switching the capacitance value to a larger value is the same as in the first embodiment of the present invention.

  The effect of this embodiment is the same as that of the first embodiment.

(Sixth embodiment)
A PLL circuit according to a sixth embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 9 is a circuit diagram showing the configuration of a loop filter which is one of the components of the PLL circuit of this embodiment.

  In the sixth embodiment of the present invention, the switch element (SW1) 14 is unnecessary as compared with the fifth embodiment of the present invention. However, instead, a function is required to prevent the output voltage of the operational amplifier 12 from being transmitted to the capacitive element Cz2. For this reason, the operational amplifier 12 used in the sixth embodiment of the present invention needs to be able to make its output high impedance.

  The contents of the operation are the fifth embodiment of the present invention except that the output of the operational amplifier 12 is set to high impedance at the timing when the switch element (SW1) 14 is turned off in the fifth embodiment of the present invention. Is exactly the same.

  The effect of this embodiment is the same as that of the first embodiment.

(Seventh embodiment)
A PLL circuit according to a seventh embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 10 is a circuit diagram showing the configuration of a loop filter which is one of the components of the PLL circuit of this embodiment.

  In the seventh embodiment of the present invention shown in FIG. 10, the circuit connection of the resistor elements Rz1, Rz2 and the capacitor element Cz1 connected in series is compared with the first to fourth embodiments of the present invention. It is opposite to the ground. That is, the resistor element Rz1 is grounded, and the capacitor element Cz1 is connected to the output terminal of the charge pump 4. However, the operation is exactly the same as in the third embodiment of the present invention, and when switching the capacitance value, which is a basic requirement, from Cz1 to Cz1 + Cz2, the capacitive element Cz2 is charged to the same potential as the capacitive element Cz1. After that, switching the capacitance value to a larger value is the same as in the first embodiment of the present invention.

  The effect of this embodiment is the same as that of the first embodiment.

(Eighth embodiment)
A PLL circuit according to an eighth embodiment of the present invention will be described with reference to FIGS. The overall configuration of the PLL circuit of this embodiment is as shown in FIG. 1 as in the first embodiment. Only the internal configuration of the loop filter is different from that of the first embodiment. FIG. 11 is a circuit diagram showing the configuration of a loop filter which is one of the components of the PLL circuit of this embodiment.

  In the eighth embodiment of the present invention, the switch element (SW1) 14 is unnecessary as compared with the seventh embodiment of the present invention. However, instead, a function is required to prevent the output voltage of the operational amplifier 12 from being transmitted to the capacitive element Cz2. For this reason, the operational amplifier 12 used in the eighth embodiment of the present invention needs to be able to make its output high impedance.

  The contents of the operation are the seventh embodiment of the present invention except that the output of the operational amplifier 12 is set to high impedance at the timing when the switch element (SW1) 14 is turned off in the seventh embodiment of the present invention. Is exactly the same.

  The effect of this embodiment is the same as that of the first embodiment.

  As described above, in the present invention, the PLL circuit is reduced in operating noise, and interference occurs when other circuit blocks other than the PLL circuit such as the transmission circuit and the reception circuit are integrated on the same semiconductor substrate as the PLL circuit. It is possible to reduce the deterioration of the characteristics of the transmission / reception circuit.

1 is a block diagram showing a configuration of a PLL circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 1st Embodiment of this invention. FIG. 10 is a timing diagram illustrating an operation of the PLL circuit according to the first, third, fifth, and seventh embodiments of the present invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 2nd Embodiment of this invention. It is a timing diagram which shows the operation | movement of the PLL circuit of 2nd, 4th, 6th, and 8th embodiment of this invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 3rd Embodiment of this invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 4th Embodiment of this invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 5th Embodiment of this invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 6th Embodiment of this invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 7th Embodiment of this invention. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of the 8th Embodiment of this invention. It is a block diagram which shows the structure of the PLL circuit of a prior art. It is a circuit diagram which shows the structure of the loop filter in the PLL circuit of a prior art. FIG. 6 is a timing diagram illustrating the operation of a prior art PLL circuit. It is a longitudinal cross-sectional view which shows the structure of a semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Voltage control oscillator 2 Variable frequency divider 3 Phase comparator 4 Charge pump 5 Loop filter 6 Frequency division signal 7 Reference signal 8 Operational amplifier 9 Output signal 10 Charge pump 11 Temperature compensation crystal oscillator 12 Operational amplifier 13 Control voltage 14 Switch element (SW1)
16 Natural angular frequency switching signal 17 Switch element (SW2)
18 Switch element (SW3)

Claims (12)

A voltage-controlled oscillator; a phase comparator that compares the output signal of the voltage-controlled oscillator with a reference signal; and a low-frequency component of the output signal of the phase comparator that includes a capacitor and a resistance as a control voltage for the voltage-controlled oscillator A PLL characteristic switching method for switching a response characteristic of a PLL circuit configured to include at least a given loop filter and operating at a predetermined natural angular frequency and a damping factor,
Switching the value of the capacitance according to a switching signal to switch the natural angular frequency;
And a step of switching the value of the resistor in response to the switching signal in conjunction with the switching of the value of the capacitance in order to maintain the damping factor at a constant value. A voltage-controlled oscillator; a phase comparator that compares the phase of the output signal of the voltage-controlled oscillator with a reference signal; and a loop filter that provides a low-frequency component of the output signal of the phase comparator as a control voltage to the voltage-controlled oscillator. A PLL circuit configured to include at least a predetermined natural angular frequency and a damping factor,
The loop filter includes a capacitance and resistance series circuit connected to an output terminal of the phase comparator, capacitance switching means for switching the value of the capacitance in response to a switching signal in order to switch the natural angular frequency, and A PLL circuit comprising resistance switching means for switching the value of the resistor in response to the switching signal in conjunction with switching of the capacitance value in order to maintain the damping factor at a constant value. The capacitor includes first and second capacitor elements provided in parallel,
The capacitance switching means is connected between the first capacitive element and the second capacitive element, and is switched between on and off in response to the switching signal, and the capacitance value switching switch. 3. The PLL circuit according to claim 2, further comprising a charging circuit that charges the second capacitor element to the same potential as the first capacitor element when the element is in an off state.   The charging circuit is connected between a voltage follower that receives the potential of the first capacitive element, an output terminal of the voltage follower, and the second capacitive element, and the capacitance value switching switch element is in an OFF state. 4. The PLL circuit according to claim 3, further comprising a charge control switch element that is conductive when the capacitance value changeover switch element is open and is opened when the capacitance value changeover switch element is on.   5. The PLL circuit according to claim 4, wherein the voltage follower comprises an operational amplifier having an output terminal connected to an inverting input terminal. The charging circuit includes a voltage follower having an input of the potential of the first capacitive element and an output terminal connected to the second capacitive element,
The voltage follower has a function of being in a high impedance output state, and is in a normal output state when the capacitance value changeover switch element is in an off state, and in a high impedance output state when the capacitance value changeover switch element is in an on state. The PLL circuit according to claim 3.   7. The PLL circuit according to claim 6, wherein the voltage follower comprises an operational amplifier having an output terminal connected to an inverting input terminal. The resistor is directly connected to the first capacitor element, and the second capacitor element is connected to a connection point between the resistor and the first capacitor element via the capacitance value switching switch element,
The charging circuit includes an amplifier circuit that amplifies a potential difference appearing between both ends of the resistor with reference to a potential at a connection point between the first capacitor element and the resistor, an output terminal of the amplifier circuit, and the second capacitor 4. The PLL according to claim 3, further comprising: a charge control switch element that is connected to the element and that conducts when the capacitance value changeover switch element is in an off state and opens when the capacitance value changeover switch element is in an on state. circuit.   The amplifier circuit includes: a first operational amplifier having an output terminal connected to an inverting input terminal and a non-inverting input terminal connected to a connection point between the resistor and the first capacitive element; and an output terminal of the first operational amplifier. A first resistance element having one end connected to the first resistance element, and an inverting input terminal connected to the other end of the first resistance element, and a non-inversion to a terminal opposite to the connection point of the first capacitance element in the resistance. A second operational amplifier having an input terminal connected and an output terminal connected to the charge control switch element; and a second resistance element connected between the output terminal and the inverting input terminal of the second operational amplifier. The PLL circuit according to claim 8. The resistor is directly connected to the first capacitor element, and the second capacitor element is connected to a connection point between the resistor and the first capacitor element via the capacitance value switching switch element,
The charging circuit includes an amplifier circuit that amplifies a potential difference appearing between both ends of the resistor with reference to a potential at a connection point between the first capacitive element and the resistor, and an output terminal of the amplifier circuit is the second terminal. Connected to the capacitive element,
The amplifying circuit has a function of being in a high impedance output state, is in a normal output state when the capacitance value changeover switch element is in an off state, and is in a high impedance output state when the capacitance value changeover switch element is in an on state. The PLL circuit according to claim 3.   The amplifier circuit includes: a first operational amplifier having an output terminal connected to an inverting input terminal and a non-inverting input terminal connected to a connection point between the resistor and the first capacitive element; and an output terminal of the first operational amplifier. A first resistance element having one end connected to the first resistance element, and an inverting input terminal connected to the other end of the first resistance element, and a non-inversion to a terminal opposite to the connection point of the first capacitance element in the resistance. A second operational amplifier having an input terminal connected and an output terminal connected to the charge control switch element; and a second resistance element connected between the output terminal and the inverting input terminal of the second operational amplifier. The PLL circuit according to claim 10. The resistor comprises a series circuit of first and second resistance elements,
The resistance switching means comprises a resistance value switching switch element connected in parallel to any one of the first and second resistance elements,
4. The PLL circuit according to claim 3, wherein the resistance value changeover switch element is turned off when the capacitance value changeover switch element is in an off state, and is turned on when the capacitance value changeover switch element is in an on state.

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