JP2006066965A - Data receiver for estimating bit rate, bit rate estimating method, program and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data receiver capable of estimating the bit rate of a data transmitter and causing the data transmitter to synchronize a clock when a synchronization clock is not supplied from a network; and to provide a bit rate estimating method, a program, and a recording medium. <P>SOLUTION: The data buffer 10 of the data receiver 4 receives data and accumulates the received data. A bit rate estimating means 13 inputs the accumulated data amount from the data buffer 10 and a target data amount from a target data amount display means 12, calculates a target deviation amount on the basis of the data amounts, and applies proportional, integrating and differential operations to estimate a bit rate. A data extracting means 11 inputs the estimated bit rate estimated by the means 13, and extracts the data from the buffer 10 at the estimated bit rate. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a case where a data receiving device is connected to a data receiving device when the same clock as the data transmitting device cannot be supplied from the network to the receiving device under a communication system in which the data transmitting device and the data receiving device are connected via an asynchronous network. The present invention relates to a technique for estimating a bit rate and a clock frequency for synchronization when processing data transmitted from a transmission apparatus.

  In a communication system in which a data transmission device and a data reception device are connected via an asynchronous network such as an Ethernet (registered trademark) / Ethernet (registered trademark) network, the data reception device reproduces and synchronizes the clock of the data transmission device. There is an adaptive clock method. This adaptive clock method is, for example, ITU-T recommendation I.D. The principle is described in 363.1 “B-ISDN ATM Adaptation Layer specification: Type 1 AAL”. According to this recommendation, the principle of the adaptive clock method is that when the data transmission device transmits data at a constant bit rate, the data transmission device and the data reception device are connected via an asynchronous network. This is because the average value of the amount of received data per unit time observed on the receiving apparatus side stochastically matches the bit rate of the original data transmitting apparatus. That is, the data receiving apparatus can estimate the bit rate of the data transmitting apparatus by dividing the amount of data received in a certain time period by the time period. The data receiving device regenerates the clock of the data transmitting device by controlling the clock of the data receiving device so as to match the bit rate. Since the clock frequency and the bit rate have a fixed constant multiple relationship, it is possible to estimate the clock frequency by estimating the bit rate.

  When the data receiving apparatus estimates the bit rate of the data transmitting apparatus, there are two problems described below. The first problem relates to the elimination of errors caused by fluctuations, and the second problem relates to the high-speed tracking capability. The fluctuation that is the first problem is due to jitter added by a network existing in the middle from the data transmission device to the data reception device. For example, even if the data transmission device transmits data at a constant speed, The speed of data received by the data receiving apparatus is not constant. If the error due to this fluctuation is not excluded, the data receiving apparatus cannot estimate the accurate data transmission rate, that is, the bit rate. The second problem, which is high-speed tracking, is that the data receiving apparatus can estimate the data transmission speed of the data transmitting apparatus in a short time when the data receiving apparatus starts up or when the transmission speed of the data transmitting apparatus is changed. This is an important function as a device. The fluctuation, which is the first problem, can be eliminated by averaging the values observed from the data reception status. However, this averaging deteriorates the high-speed followability, which is the second problem. Therefore, there is a need for an averaging process that can achieve the contradictory requirements of fluctuation suppression and high-speed tracking.

  As a method of calculating the average value of the amount of data received by the data receiving device, a method of directly measuring the amount of received data and dividing it by time can be considered. However, in this method, since the upper limit value of the amount of data to be received cannot be known in advance, the hardware amount of the counter for measuring the data amount cannot be determined. In addition, since a considerable amount of data is required to estimate an accurate bit rate, there is a problem in that it takes time until reception of a considerable amount of data is completed, and control is delayed.

  Therefore, as another method, a method of temporarily storing data sequentially received by the data receiving apparatus in a data buffer and extracting the data from the data buffer at an estimated bit rate is conceivable. In this case, when the extraction speed matches the data transmission speed (bit rate of the data transmission apparatus), the amount of data existing in the data buffer is determined by the input data speed (data storage speed) and the output data speed (removal speed). Since it is balanced, it maintains a certain value. Conversely, if the output data rate is controlled so that the amount of data existing in the data buffer becomes a constant value, the output data rate matches the bit rate of the data transmitting apparatus. If the bit rate can be estimated accurately, the clock of the data transmission device is a fixed constant multiple of the bit rate, and therefore the clock can also be estimated accurately.

  As a means for realizing the conventional adaptive clock method, there is disclosed one that controls the difference between the average value of the amount of data existing in the data buffer and a predetermined threshold value (for example, see Non-Patent Document 1). .)

Hirotoshi Yamada and four others "Study on" adaptive clock method "in AAL type 1", IEICE General Conference, no. B-8-23, pp. 409, 1997

  In the conventional adaptive clock method, the amount of data stored in the data buffer is controlled to be a constant value, but the constant value is a value that is not set in advance. Therefore, the constant value may become extremely large, which causes a problem that the capacity of the data buffer of the data receiving device is exceeded.

  In order to solve this problem, a method of setting a target value for the accumulated data amount and controlling the average value of the accumulated data amount to approach the target value can be considered. The average value of the accumulated data amount is used in order to eliminate the influence of delay variation of data transmitted from the data transmission device to the data reception device. However, since the average value of the accumulated data amount is used, it is delayed to feed back the error between the true bit rate and the estimated bit rate to the control system compared to the case where the accumulated data amount itself is used. There was a problem that.

  Further, in the conventional adaptive clock method, control is performed by paying attention to whether the target deviation amount is larger or smaller with reference to a state where the target deviation amount is 0, and the fluctuation amount of the target deviation amount is not considered. For this reason, when the target deviation amount is greater than 0, the estimated bit rate is controlled to be faster. However, if the target deviation amount is greater than 0, the estimated bit rate is the true bit rate. In this case, there is a problem that the control becomes excessive because it means faster.

  When the data transmission device and the data reception device are connected via a packet network such as an Ethernet (registered trademark) network, the data reception device receives the data encapsulated for each packet by the data transmission device. . The data receiving apparatus receives such burst-transmitted data and stores it in the data buffer. At this time, since the buffer amount increases rapidly, the estimated bit rate value is greatly affected. Therefore, to accurately estimate the bit rate, it is necessary to remove this influence.

  Therefore, the present invention has been made in view of such problems, and an object of the present invention is to estimate the bit rate of the data transmission device and synchronize the clock with the data transmission device when the synchronization clock is not supplied from the network. A data receiving apparatus, a bit rate estimating method, a program, and a recording medium are provided.

  In order to solve the above problems, the present invention provides a data receiving apparatus that is connected to a data transmitting apparatus that transmits data at a constant bit rate via a communication network, receives the data, and estimates a bit rate from the data. The data received by the data buffer is accumulated, the accumulated data amount output means outputs the amount of data accumulated in the data buffer (accumulated data amount), and the target data amount output means outputs the target value of the accumulated data amount. (Target data amount) is output, and based on the accumulated data amount output by the accumulated data amount output unit by the bit rate estimating unit and the target data amount output by the target data amount output unit, the proportional, integral and A differential operation is performed to estimate the bit rate, and the data fetching means is operated at the bit rate estimated by the bit rate estimating means. Wherein the retrieving data from Tabaffa.

  In the present invention, the data received by the data buffer is stored, and the amount of data received by the stored data amount output means and the amount of data extracted from the data buffer (the amount of extracted data) The amount of data accumulated in the buffer (accumulated data amount) is calculated, the accumulated data amount is output, the target data amount output means outputs the target value (target data amount) of the accumulated data amount, and the bit rate Based on the accumulated data amount output by the accumulated data amount output means and the target data amount output by the target data amount output means, the estimation means performs proportional, integral and differential operations to estimate the bit rate, The data fetching means fetches data from the data buffer at the bit rate estimated by the bit rate estimating means, and determines the amount of fetched data. And outputs the product data amount output means.

  Further, according to the present invention, the difference calculation means of the bit rate estimation means calculates the difference (target deviation amount) between the accumulated data amount and the target data amount and outputs the target deviation amount. An integral operation is performed on the quantity and a predetermined coefficient (coefficient 1) is multiplied, and an operation result is output. A differential operation 2 means performs a differential operation on the target deviation amount and multiplies the predetermined coefficient (coefficient 2). The calculation result is output, and the addition means performs an addition operation on the target deviation amount output by the difference calculation means, the calculation result output by the integral calculation 1 means, and the calculation result output by the differential calculation 2 means. The result is output, and the multiplication 3 means multiplies the operation result output by the addition means by a predetermined coefficient (coefficient 3) to output the operation result, and the operation result output by the multiplication 3 means is estimated as the bit rate. It is characterized by doing.

  Further, according to the present invention, the difference calculation means of the bit rate estimation means calculates the difference (target deviation amount) between the accumulated data amount and the target data amount and outputs the target deviation amount. The amount is integrated and multiplied by a predetermined coefficient (coefficient 4), and the calculation result is output. The smoothing calculation means performs the smoothing calculation on the target deviation amount to obtain the calculation result (smoothing target deviation amount). The differential operation 5 means performs a differentiation operation on the smoothing target deviation amount and multiplies a predetermined coefficient (coefficient 5), outputs the operation result, and the addition means is output by the smoothing operation means. The smoothing target deviation amount, the calculation result output by the integration calculation 4 means, and the calculation result output by the differentiation calculation 6 means are subjected to addition calculation to output the calculation result, and the multiplication 6 means is output by the addition means Multiply the calculated result by a predetermined coefficient (coefficient 6) And outputs the operation result, and estimates the calculation result outputted by the multiplication 6 means as a bit rate.

  Further, the difference calculation means of the bit rate estimation means of the present invention calculates the difference (target deviation amount) between the accumulated data amount and the target data amount and outputs the target deviation amount, and the integration calculation 7 means has the target deviation amount. Is subjected to integral calculation and multiplied by a predetermined coefficient (coefficient 7), and the calculation result is output. The smoothing calculation means performs smoothing calculation on the target deviation amount and outputs the calculation result (smoothing target deviation amount). Then, the differential operation 8 means performs the differential operation on the smoothing target deviation amount and multiplies the predetermined coefficient (coefficient 8), outputs the operation result, and the addition means outputs the smoothing output from the smoothing operation means. The calculation target deviation amount, the calculation result output by the integration calculation means 7 and the calculation result output by the differentiation calculation means 8 are added and the calculation result is output. The averaging calculation means is output by the addition means. Averaging operation is performed on the calculated operation results The multiplication 9 means outputs the operation result by multiplying the operation result output by the averaging operation means by a predetermined coefficient (coefficient 9), and the operation result output by the multiplication 9 means is output as a bit. It is estimated as a rate.

  Further, the present invention is characterized in that the estimated bit rate is multiplied by a predetermined constant, and the calculation result is used as an estimated value of the frequency of the clock synchronized with the data transmitting apparatus.

  According to the present invention, the data receiving apparatus estimates the bit rate based on the target deviation amount. Thereby, when the target deviation amount is positive, that is, when the accumulated data amount is larger than the target data amount, it is determined that the estimated bit rate (estimated bit rate) is slower than the bit rate (true bit rate) of the data transmitting apparatus. Therefore, control can be performed to increase the estimated bit rate. On the other hand, when the target deviation amount is negative, it can be determined that the estimated bit rate is faster than the true bit rate, and therefore control can be performed to decrease the estimated bit rate.

  Further, the data receiving apparatus estimates the bit rate by performing a differential operation on the target deviation amount in order to consider the fluctuation amount of the target deviation amount. Accordingly, when the target deviation amount is increasing, it can be determined that the estimated bit rate is slower than the true bit rate, and therefore control can be performed to increase the estimated bit rate. On the other hand, when the target deviation amount is decreasing, it can be determined that the estimated bit rate is faster than the true bit rate, and therefore control can be performed to decrease the estimated bit rate.

  In addition, the data receiving apparatus performs an integration operation on the target deviation amount to estimate the bit rate. As a result, the offset that occurs when the bit rate is estimated based on the target deviation amount and the differential of the target deviation amount (the difference between the estimated bit rate and the true bit rate / in this case, the target deviation amount is constant at 0) Not) can be removed. That is, the data receiving apparatus performs an addition operation on the target deviation amount, the result of the differential operation, and the result of the integration operation to estimate the bit rate, so that the bit rate corresponding to the result of the integration operation is obtained unless the target deviation amount becomes zero. Can be corrected, and as a result, the offset can be removed.

  Further, the data receiving apparatus performs a smoothing operation on the target deviation amount to estimate the bit rate. Thereby, since the rapid change of the target deviation amount is suppressed, the fluctuation of the estimated bit rate can be suppressed and the true bit rate can be converged. For example, when the data receiving apparatus receives burst data from the packet network, the accumulated data amount increases rapidly, and the target deviation amount and its differential value change rapidly, so that the estimated bit rate also varies greatly. . The smoothing process of the target deviation amount can appropriately estimate the bit rate even when such burst data is received. Note that the integral calculation of the target deviation amount is not subject to smoothing processing because it has the property that even if the input changes suddenly, the calculation result does not change suddenly.

  Further, the data receiving apparatus adds the target deviation amount, the result of the differential operation, and the result of the integration operation, performs an averaging operation, and estimates the bit rate. In consideration of the property that the bit rate estimated by the averaging operation asymptotically approaches the true bit rate, errors due to jitter fluctuations can be suppressed.

  According to the present invention, feedback is performed by performing a unique calculation on the difference between the data amount stored in the data buffer and the target data amount in the data receiving apparatus, estimating the bit rate, and extracting data from the data buffer at the bit rate. Control was done. By this feedback control, the estimated bit rate gradually approaches the bit rate of the data transmission apparatus. Therefore, even when the synchronous clock is not supplied from the communication network, the data receiving apparatus can estimate the bit rate at which the data transmitting apparatus transmits data. Further, the data receiving apparatus can synchronize the clock for operating the data receiving apparatus with the clock for operating the data transmitting apparatus.

Embodiments of the present invention will be described below with reference to the drawings.
〔Constitution〕
FIG. 1 is a block diagram showing a configuration of an embodiment of a communication system including a data receiving apparatus of the present invention. This communication system includes terminal devices 1 and 5, data transmission devices 2 and 4, and a communication network 3. The terminal device 1 outputs data at a constant bit rate. The data transmission device 2 receives the data output from the terminal device 1 and transmits it to the data reception device 4 via the communication network 3 at a constant bit rate. The communication network 3 is a network that connects the data transmission device 2 and the data reception device 4. The data receiving device 4 receives the data transmitted by the data transmitting device 2 via the communication network 3 and outputs the data to the terminal device 5. During these reception processing and output processing, the speed of the received data and the transmission data The bit rate, which is the speed of the transmission data, is adjusted so as to eliminate the difference from the speed (data output speed to the terminal device 5). The terminal device 5 inputs the data output from the data receiving device 4. In this case, the terminal device 1 and the data transmission device 2 are usually installed at positions close to each other, and both devices may operate based on the clock of the same clock source. Further, the data receiving device 4 and the terminal device 5 do not use the clock source used by the data transmitting device 2. The communication network 3 may be a packet network. In the case of a packet network, the data transmission device 2 encapsulates the data packet output by the terminal device 1, and the data reception device via the packet network. 4 to send.

  FIG. 2 is a block diagram showing a functional configuration of the first embodiment of the data receiving apparatus 4 shown in FIG. The data receiving device 4 includes a data buffer 10, a data extraction unit 11, a target data amount display unit 12, a bit rate estimation unit 13, and a clock generation unit 14. The data buffer 10 receives and accumulates data transmitted from the data transmission device 2 via the communication network 3, and stores the amount of data accumulated in the data buffer 10 as the accumulated data amount in the bit rate estimation means 13. Output. The target data amount display unit 12 outputs a target value (target data amount) of the accumulated data amount that is the amount of data accumulated in the data buffer 10 to the bit rate estimation unit 13. The bit rate estimation means 13 receives the accumulated data amount and the target data amount, estimates the data transmission bit rate of the data transmission device 2 based on these data amounts, and uses the data extraction means 11 and the clock as the estimated bit rate. Output to the generation means 14. The data extraction unit 11 receives the estimated bit rate estimated and output by the bit rate estimation unit 13, extracts data from the data buffer 10 at the estimated bit rate, and outputs the data to the terminal device 5. The clock generator 14 receives the estimated bit rate estimated and output by the bit rate estimator 13 and sets the estimated bit rate to synchronize the clock for operating the data receiver 4 with the data transmitter 2. Based on this, a clock is generated.

  FIG. 3 is a block diagram showing a functional configuration of the second embodiment of the data receiving device 4 shown in FIG. The data receiving device 4 includes a data buffer 10, a data extraction unit 11, a target data amount display unit 12, a bit rate estimation unit 13, a clock generation unit 14, and an accumulated data amount display unit 15. In FIG. 3, the same reference numerals as those in FIG. 2 are assigned to portions common to FIG. 2, and detailed description thereof is omitted. The accumulated data amount display means 15 receives the data transmitted from the data transmission device 2 via the communication network 3 and inputs the extracted data amount of the data extracted from the data buffer 10 by the data extraction means 11. Then, the difference between the amount of received data and the input extracted data amount is calculated, the amount of data stored in the data buffer 10 is calculated based on the difference, and output to the bit rate estimating means 13 as the stored data amount. To do.

  In the first embodiment shown in FIG. 2, the range of the accumulated data amount is 0 or more and less than the capacity of the data buffer 10. On the other hand, in the second embodiment, the accumulated data amount display means 15 does not directly measure the amount of data accumulated in the data buffer 10, but inputs the received data amount and the data extraction means 11. The difference from the extracted data amount is calculated, and the result is set as the accumulated data amount. Therefore, when the data extracting means 11 behaves as if the data has been extracted even when no data is stored in the data buffer 10, the accumulated data amount becomes a negative value, and the accumulated data amount display means 15 is negative. The amount of stored data can be handled. Further, when the data buffer 10 overflows, the amount of stored data exceeds the capacity of the data buffer 10. In this case, the accumulated data amount display means 15 does not directly measure the amount of data accumulated in the data buffer 10 (the amount of data equivalent to the capacity of the data buffer 10 due to buffer overflow). The accumulated data amount to be performed may not indicate the actually accumulated data amount. In this way, the stored data amount display means 15 calculates the stored data amount that is actually impossible, and outputs it to the bit rate estimating means 13, so that the control output (estimated bit rate estimated by the bit rate estimating means 13) is large. Therefore, the estimated bit rate can be made closer to the bit rate of the data transmission device 2 at a higher speed.

  The accumulated data amount display means 15 can also calculate the actual accumulated data amount accumulated in the data buffer 10. For example, when data is not accumulated in the data buffer 10, the accumulated data amount calculated by the accumulated data amount display means 15 becomes a negative value by preventing the data retrieving means 11 from retrieving data. There is no. Also, for example, when the accumulated data amount display means 15 receives data when the accumulated data amount calculated by the accumulated data amount display means 15 matches the capacity of the data buffer 10, the accumulated data amount display means 15 However, since the accumulated data amount does not increase, the accumulated data amount does not exceed the capacity of the data buffer 10.

  FIG. 4 is a block diagram showing a functional configuration of the first embodiment in the bit rate estimating means 13 provided in the data receiving device 4 of FIGS. The bit rate estimating means 13 includes a difference calculating means 21, an integral calculating 1 means 22, a differential calculating 2 means 23, an adding means 24 and a multiplying 3 means 25. The integral calculation 1 means 22, the differential calculation 2 means 23, the addition means 24 and the multiplication 3 means 25 constitute a controller 28. The difference calculation means 21 inputs the accumulated data amount from the data buffer 10 or the accumulated data amount display means 15 and the target data amount from the target data amount display means 12, calculates the difference, and performs an integral operation as the target deviation amount. 1 means 22, differential operation 2 means 23 and addition means 24. The integral calculation 1 means 22 inputs the target deviation amount, performs the integral calculation on the target deviation amount, then multiplies the coefficient (A1) held by the integral calculation 1 means 22, and adds the result to the addition means 24. Output to. The differential operation 2 means 23 inputs the target deviation amount, performs the differential operation on the target deviation amount, then multiplies the coefficient (B1) held by the differential operation 2 means 23, and adds the result to the addition means 24. Output to. The adding means 24 inputs the target deviation amount from the difference calculating means 21, the output result of the integral calculation 1 means 22, and the output result of the differential calculation 2 means 23, and calculates and outputs the sum of these. The multiplication 3 means 25 receives the addition result from the addition means 24, multiplies the coefficient (C1) held by the multiplication 3 means 25, and outputs the result as an estimated bit rate.

  FIG. 5 is a block diagram showing a functional configuration of the second embodiment in the bit rate estimating means 13 provided in the data receiving device 4 of FIGS. The bit rate estimating means 13 includes a difference calculating means 21, an integral calculating 4 means 32, a differential calculating 5 means 33, an adding means 24, a multiplying 6 means 35, and a smoothing calculating means 36. Further, the integral calculation 4 means 32, the differential calculation 5 means 33, the addition means 24, the multiplication 6 means 35 and the smoothing calculation means 36 constitute a controller 38. The difference calculation means 21 inputs the accumulated data amount from the data buffer 10 or the accumulated data amount display means 15 and the target data amount from the target data amount display means 12, calculates the difference, and performs an integral operation as the target deviation amount. 4 and output to the smoothing calculation means 36. The integral calculation 4 means 32 inputs the target deviation amount, performs the integral calculation on the target deviation amount, multiplies the coefficient (A2) held by the integral calculation 4 means 32, and adds the result to the addition means 24. Output to. The smoothing calculation means 36 receives the target deviation amount, performs a smoothing calculation on the target deviation amount, and outputs the calculation result to the differential calculation 5 means 33 and the addition means 24. The differential calculation 5 means 33 receives the calculation result (smoothed target deviation amount) from the smoothing calculation means 36, performs a differential calculation on the smoothed target deviation amount, and then performs the differential calculation 5 The coefficient (B2) held by the means 33 is multiplied and the result is output to the adding means 24. The adding means 24 inputs the smoothed target deviation amount from the smoothing calculating means 36, the output result of the integral calculating 4 means 32, and the output result of the differential calculating 5 means 33, and calculates the sum thereof. Output. The multiplication 6 means 35 receives the addition result from the addition means 24, multiplies the coefficient (C2) held by the multiplication 6 means 35, and outputs the result as an estimated bit rate.

  FIG. 6 is a block diagram showing a functional configuration of the third embodiment in the bit rate estimating means 13 provided in the data receiving device 4 of FIGS. The bit rate estimation means 13 includes a difference calculation means 21, an integral calculation 7 means 42, a differentiation calculation 8 means 43, an addition means 24, a multiplication 9 means 45, a smoothing calculation means 36, and an averaging calculation means 47. Further, the integral calculation 7 means 42, the differential calculation 8 means 43, the addition means 24, the multiplication 9 means 45, the smoothing calculation means 36 and the averaging calculation means 47 constitute a controller 48. The difference calculation means 21 inputs the accumulated data amount from the data buffer 10 or the accumulated data amount display means 15 and the target data amount from the target data amount display means 12, calculates the difference, and performs an integral operation as the target deviation amount. 7 and output to the smoothing calculation means 36. The integral calculation 7 means 42 inputs the target deviation amount, performs the integral calculation on the target deviation amount, then multiplies the coefficient (A3) held by the integral calculation 7 means 42, and adds the result to the addition means 24. Output to. The smoothing calculation means 36 receives the target deviation amount, performs a smoothing calculation on the target deviation amount, and outputs the calculation result to the differential calculation 8 means 43 and the addition means 24. The differential calculation 8 means 43 receives the calculation result (smoothed target deviation amount) from the smoothing calculation means 36, performs a differential calculation on the smoothed target deviation amount, and then performs the differential calculation 8 The coefficient (B3) held by the means 43 is multiplied and the result is output to the adding means 24. The adding means 24 inputs the smoothed target deviation amount from the smoothing calculating means 36, the output result of the integral calculating 7 means 42, and the output result of the differential calculating 8 means 43, and calculates the sum of these. To the averaging calculation means 47. The averaging calculation means 47 inputs the addition result from the addition means 24, averages the addition result, and outputs the calculation result to the multiplication 9 means 45. The multiplication 9 means 45 receives the calculation result from the averaging calculation means 47, multiplies the coefficient (C3) held by the multiplication 9 means 45, and outputs the result as an estimated bit rate.

[Operation]
Next, the operation of the data receiving device 4 shown in FIGS. 2 and 3 will be described. This operation controls the estimated bit rate in order to keep the amount of data accumulated in the data buffer 10 (accumulated data amount) at a certain fixed value (target data amount). FIG. 7 is a functional block diagram showing an outline of the operation of the data receiving device 4. First, the accumulated data amount is a value obtained by performing integration processing on the difference between the bit rate of the received data (bit rate of the data transmission device 2) and the estimated bit rate. Therefore, the bit rate of the received data and the estimated bit rate obtained by feeding back the outputs of the controllers 28, 38, and 48 are input to the adder, and the adder calculates the difference and outputs it to the integrator. The integrator performs an integration process on the difference between the input calculation results and outputs the calculation result as an accumulated data amount. The target deviation amount is a difference between the accumulated data amount and the target data amount. Therefore, the second adder inputs the accumulated data amount from the integrator and the target data amount, calculates the difference between them, and outputs the calculation result to the controllers 28, 38, and 48 as the target deviation amount. The controllers 28, 38, and 48 estimate the bit rate and output the estimated bit rate. The clock generation means 14 receives the estimated bit rate, performs a constant multiplication, generates a clock, and outputs it.

係数Ａ１、Ｂ１及びＣ１は全て正数である。 Here, the controllers 28, 38, and 48 shown in FIG. 7 correspond to portions other than the difference calculation means 21 in FIGS. The processing of the controller 28 shown in FIG. With the target deviation amount g (t) and the estimated bit rate y (t), the processing of the controller 28 is the sum of the result of multiplying each of the proportional component, integral component and differential component of the target deviation amount by a coefficient. Can be represented by the following equation.

The coefficients A1, B1, and C1 are all positive numbers.

  The operation of the controller 28 will be described. When t = 0, g (t) is 0, and y (t) is 0, the calculation result in the parentheses in the expression (1) is 0 at t = 0, so the right side is 0. As time advances, g (t) becomes positive because there is no data retrieval, and both its integration and differentiation become positive. Therefore, y (t) is also positive. As time progresses further, y (t) increases and eventually exceeds the reception bit rate. Then, g (t) starts to decrease. As g (t) decreases, its derivative becomes negative. As time progresses further, g (t) further decreases and finally g (t) becomes negative. As the right side of equation (1) decreases, y (t) also decreases. When y (t) falls below the reception bit rate (bit rate of the data transmission device 2), g (t) starts to increase. By repeating this process several times, y (t) asymptotically approaches the reception bit rate and g (t) asymptotically approaches zero. In this case, the state where y (t) asymptotically approaches the reception bit rate depends on the coefficients A1, B1 and C1. When y (t) is stabilized in accordance with the reception bit rate, g (t) is stabilized at 0. The derivative of g (t) is also 0, but since the integral of g (t) is not 0, no offset remains.

平滑化演算ｈ（・）の例を次式に表す。

ここで、Ｈ（ｓ）はｈ（・）のラプラス変換であり、式（３）は伝達関数による表現である。この平滑化演算に対するステップ入力の応答、すなわちステップ応答ｚ（ｔ）を次式に表す。

また、他の平滑化演算の例を次式に表す。

この平滑化演算のステップ応答ｚ（ｔ）を次式に表す。

Next, the processing of the controller 38 shown in FIG. The basic form of the mathematical expression is the same as that of the controller 28 described above, but is different in that a smoothing operation is performed. The process of the controller 38 can be expressed by the following equation where h (·) is the smoothing operation.

An example of the smoothing operation h (•) is expressed by the following equation.

Here, H (s) is a Laplace transform of h (•), and Expression (3) is an expression by a transfer function. A step input response to the smoothing operation, that is, a step response z (t) is expressed by the following equation.

Another example of the smoothing calculation is represented by the following equation.

The step response z (t) of this smoothing calculation is expressed by the following equation.

  FIG. 8 is a graph of the smoothing calculation when a = 5 in Equation (6). The horizontal axis represents time, and the vertical axis represents the smoothing calculation step response z (t). As described above, it can be seen from the graph of FIG. 8 that the input data is smoothed by the smoothing calculation of Expression (6). The above-described formulas (3) to (6) of the smoothing calculation are examples, and other smoothing calculation formulas may be used.

この平滑化演算出力のグラフを図１０に示す。時刻０及びそれ以降において、出力は滑らかに変化することがわかる。 The basic operation of the controller 38 is the same as that of the controller 28 described above, but a smoothing operation is incorporated so that the result y (t) does not change abruptly even if g (t) changes abruptly. Is different. For example, when the communication network 3 is a packet network and the data transmission device 2 transmits data collectively at a certain interval, a certain amount of data is included in one packet. FIG. 9 shows a change in the amount of accumulated data when the data receiving device 4 receives bursty data when the estimated bit rate and the transmission bit rate (bit rate of the data transmitting device 2) match. It is a graph. From the graph of FIG. 9, it can be seen that the amount of accumulated data changes abruptly every time a packet is received, and the target deviation also changes abruptly. If this is used for control as it is, the proportional component and the differential component change abruptly, so the estimated bit rate also changes abruptly, resulting in an unstable state. Therefore, smoothing is performed in order to perform more stable control. The output when the smoothing operation is performed on the time interval [0, 1] is expressed by the following equation.

A graph of the smoothing calculation output is shown in FIG. It can be seen that the output changes smoothly at time 0 and thereafter.

平均化演算ｍ（・）の例を次式に表す。

これは、全Ｎ個のデータを単純にＮで割ったものである。また、他の平均化演算の例を次式に表す。

ここで、αは０より大きく１より小さい実数である。式（１０）による平均化演算では、過去の全てのデータの値を保持する必要がないので、式（９）に比べて簡便である。尚、平均化演算の前述の式（９）及び（１０）は一例であり、これら以外の平均化演算式を用いてもよい。 Next, the processing of the controller 48 shown in FIG. The basic form of the mathematical formula is the same as that of the controller 38 described above, but differs in that an averaging operation is performed. The process of the controller 48 can be expressed by the following equation where the averaging operation is m (•).

An example of the averaging operation m (•) is represented by the following equation.

This is simply N data divided by N. Another example of the averaging operation is represented by the following equation.

Here, α is a real number larger than 0 and smaller than 1. The averaging calculation according to the equation (10) is simpler than the equation (9) because it is not necessary to hold all past data values. The above-described equations (9) and (10) of the averaging operation are examples, and other averaging operation equations may be used.

  The basic operation of the controller 48 is similar to the operation of the controller 38 described above, but differs in that an averaging operation is incorporated. For example, when jitter occurs in the communication network 3, the data reception device 4 is affected by fluctuations due to the jitter, and an error occurs in the estimated bit rate. The error caused by the jitter fluctuation can be suppressed by the above-described averaging calculation.

  The data receiving device 4 includes a volatile storage medium such as a CPU and a RAM, a non-volatile storage medium such as a ROM, an input device such as a keyboard and a pointing device, a display device that displays images and scenes, and an external device. Each may be constituted by a computer device provided with an interface for communicating with. In this case, the data buffer 10 provided in the data receiving device 4, the data extraction means 11, the target data amount display means 12, the bit rate estimation means 13, the clock generation means 14 and the accumulated data amount display means 15, and the bit rate estimation means 13 is realized by causing the CPU to execute a program describing the function. These programs can also be stored and distributed in a storage medium such as a magnetic disk (floppy disk, hard disk, etc.), optical disk (CD-ROM, DVD, etc.), semiconductor memory, or the like.

It is a block diagram which shows the structure of one Example of the communication system containing the data receiver of this invention. It is a block diagram which shows the function structure of the 1st Example in the data receiver of this invention. It is a block diagram which shows the function structure of the 2nd Example in the data receiver of this invention. It is a block diagram which shows the function structure of the 1st Example in the bit rate estimation means with which the data receiver of this invention was equipped. It is a block diagram which shows the function structure of the 2nd Example in the bit rate estimation means with which the data receiver of this invention was equipped. It is a block diagram which shows the function structure of the 3rd Example in the bit rate estimation means with which the data receiver of this invention was equipped. It is a functional block diagram which shows the outline | summary of the bit rate estimation method. It is a graph which shows an example of smoothing calculation. It is a graph which shows an example of the mode of change of the amount of stored data when data arrives in burst form via a communication network. FIG. 10 is a graph showing an example of smoothing calculation output when the data amount changes as shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,5 Terminal device 2 Data transmission device 3 Communication network 4 Data reception device 10 Data buffer 11 Data extraction means 12 Target data amount display means 13 Bit rate estimation means 14 Clock generation means 15 Accumulated data amount display means 21 Difference calculation means 22 Integration Calculation 1 means 23 Differential calculation 2 means 24 Addition means 25 Multiplication 3 means 28, 38, 48 Controller 32 Integration calculation 4 means 33 Differentiation calculation 5 means 35 Multiplication 6 means 36 Smoothing calculation means 42 Integration calculation 7 means 43 Differential calculation 8 means 45 Multiplication 9 means 47 Averaging calculation means

Claims (17)

In a data receiving apparatus that is connected to a data transmitting apparatus that transmits data at a constant bit rate via a communication network, receives the data, and estimates a bit rate from the data.
A data buffer for storing received data; and
Accumulated data amount output means for outputting the amount of data accumulated in the data buffer (accumulated data amount);
Target data amount output means for outputting a target value (target data amount) of the accumulated data amount;
Bit rate estimator for estimating the bit rate by performing proportional, integral and differential operations based on the accumulated data amount output by the accumulated data amount output means and the target data amount output by the target data amount output means When,
A data receiving apparatus comprising: data extracting means for extracting data from the data buffer at the bit rate estimated by the bit rate estimating means. In a data receiving apparatus that is connected to a data transmitting apparatus that transmits data at a constant bit rate via a communication network, receives the data, and estimates a bit rate from the data.
A data buffer for storing received data; and
Based on the amount of received data and the amount of data extracted from the data buffer (extracted data amount), the amount of data accumulated in the data buffer (accumulated data amount) is calculated, and the accumulated data amount Stored data amount output means for outputting
Target data amount output means for outputting a target value (target data amount) of the accumulated data amount;
Bit rate estimator for estimating the bit rate by performing proportional, integral and differential operations based on the accumulated data amount output by the accumulated data amount output means and the target data amount output by the target data amount output means When,
A data receiving apparatus comprising: data fetching means for fetching data from the data buffer at the bit rate estimated by the bit rate estimating means and outputting the fetched data amount to the accumulated data amount output means. The data receiving device according to claim 1 or 2,
The bit rate estimating means includes
A difference calculating means for calculating a difference (target deviation amount) between the accumulated data amount and the target data amount and outputting the target deviation amount;
An integral operation 1 means for performing an integral operation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 1), and outputting an operation result;
Differential operation 2 means for performing differential operation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 2), and outputting the operation result;
An addition means for performing addition operation on the target deviation amount output by the difference calculation means, the calculation result output by the integral calculation 1 means, and the calculation result output by the differential calculation 2 means, and outputting the calculation result;
Multiplication 3 means for multiplying the calculation result output by the addition means by a predetermined coefficient (coefficient 3) and outputting the calculation result,
A data receiving apparatus for estimating a calculation result output by said multiplication 3 means as a bit rate. The data receiving device according to claim 1 or 2,
The bit rate estimating means includes
A difference calculating means for calculating a difference (target deviation amount) between the accumulated data amount and the target data amount and outputting the target deviation amount;
Integral calculation 4 means for performing integral calculation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 4), and outputting the calculation result;
Smoothing calculation means for performing a smoothing calculation on the target deviation amount and outputting a calculation result (smoothing target deviation amount);
Differential operation 5 means for performing differential operation on the smoothing target deviation amount, multiplying by a predetermined coefficient (coefficient 5), and outputting the operation result;
Addition means for performing addition operation on the smoothing target deviation amount output by the smoothing operation means, the operation result output by the integration operation 4 means, and the operation result output by the differentiation operation 5 means, and outputting the operation result When,
Multiplication 6 means for multiplying the calculation result output by the addition means by a predetermined coefficient (coefficient 6) and outputting the calculation result;
A data receiving apparatus characterized by estimating a calculation result output by said multiplication 6 means as a bit rate. The data receiving device according to claim 1 or 2,
The bit rate estimating means includes
A difference calculating means for calculating a difference (target deviation amount) between the accumulated data amount and the target data amount and outputting the target deviation amount;
Integral calculation 7 means for performing integral calculation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 7), and outputting the calculation result;
Smoothing calculation means for performing a smoothing calculation on the target deviation amount and outputting a calculation result (smoothing target deviation amount);
Differential operation 8 means for performing differential operation on the smoothing target deviation amount, multiplying by a predetermined coefficient (coefficient 8), and outputting the operation result;
Addition means for performing addition operation on the smoothing target deviation amount output by the smoothing operation means, the operation result output by the integration operation 7 means, and the operation result output by the differentiation operation 8 means, and outputting the operation result When,
An averaging operation unit that performs an averaging operation on the operation result output by the adding unit and outputs the operation result;
A multiplication 9 means for multiplying the calculation result output by the averaging calculation means by a predetermined coefficient (coefficient 9) and outputting the calculation result;
A data receiving apparatus characterized by estimating a calculation result output by said multiplication 9 means as a bit rate. In the data receiving device according to any one of claims 1 to 5,
The data receiving apparatus further comprises a clock generating means for generating a clock based on the bit rate estimated by the bit rate estimating means. Stored in the data buffer under a communication system in which a data transmission device that transmits data at a constant bit rate and a data reception device that receives the data via a communication network and stores the data in the data buffer are connected. In a method for estimating the bit rate so that the amount of stored data (accumulated data amount) approaches a preset target value (target data amount),
A bit rate estimating method, wherein the data receiving device estimates a bit rate by performing proportional, integral and differential operations based on an accumulated data amount and a target data amount. Under a communication system in which a data transmission device that transmits data at a constant bit rate and a data reception device that receives the data via a communication network and stores the data in a data buffer are connected, the data reception device includes: A data buffer comprising: a difference calculation means for performing a subtraction operation; an integral operation 1 means for performing an integral operation; a differential operation 2 means for performing a differentiation operation; an addition means for performing an addition operation; and a multiplication 3 means for performing a multiplication operation. In the method of estimating the bit rate so that the amount of data stored in (accumulated data amount) approaches a preset target value (target data amount),
The difference calculation means calculates the difference (target deviation amount) between the accumulated data amount and the target data amount, and outputs the target deviation amount.
The integral calculation 1 means performs an integral calculation on the target deviation amount, multiplies a predetermined coefficient (coefficient 1), outputs the calculation result,
The differential operation 2 means performs a differential operation on the target deviation amount, multiplies a predetermined coefficient (coefficient 2), and outputs the operation result,
The addition means performs an addition operation on the target deviation amount output by the difference calculation means, the calculation result output by the integral calculation 1 means, and the calculation result output by the differential calculation 2 means, and outputs the calculation result;
Multiplication 3 means multiplies the calculation result output by the addition means by a predetermined coefficient (coefficient 3) and outputs the calculation result;
A bit rate estimation method, wherein the calculation result output by the multiplication means 3 is estimated as a bit rate. Under a communication system in which a data transmission device that transmits data at a constant bit rate and a data reception device that receives the data via a communication network and stores the data in a data buffer are connected, the data reception device includes: Difference calculation means for performing subtraction operation, integration operation 4 means for performing integration operation, smoothing operation means for performing smoothing operation, differential operation 5 means for performing differentiation operation, addition means for performing addition operation, multiplication operation A method of estimating the bit rate by bringing the amount of data accumulated in the data buffer (accumulated data amount) closer to a preset target value (target data amount).
The difference calculation means calculates the difference (target deviation amount) between the accumulated data amount and the target data amount, and outputs the target deviation amount.
The integral calculation 4 means performs an integral calculation on the target deviation amount, multiplies a predetermined coefficient (coefficient 4), and outputs the calculation result,
The smoothing calculation means performs the smoothing calculation on the target deviation amount and outputs the calculation result (smoothing target deviation amount).
A differential calculation 5 means performs a differential calculation on the smoothing target deviation amount, multiplies a predetermined coefficient (coefficient 5), and outputs the calculation result.
The addition means performs an addition operation on the smoothing target deviation amount output by the smoothing calculation means, the calculation result output by the integration calculation 4 means, and the calculation result output by the differentiation calculation means 6 to obtain the calculation result. Output,
Multiplication 6 means multiplies the calculation result output by the addition means by a predetermined coefficient (coefficient 6) and outputs the calculation result;
A bit rate estimation method for estimating a calculation result output by a multiplication means as a bit rate. Under a communication system in which a data transmission device that transmits data at a constant bit rate and a data reception device that receives the data via a communication network and stores the data in a data buffer are connected, the data reception device includes: Difference calculation means for performing subtraction operation, integration operation 7 means for performing integration operation, smoothing operation means for performing smoothing operation, differential operation 8 means for performing differentiation operation, addition means for performing addition operation, averaging An averaging operation means for performing an operation and a multiplication 9 means for performing a multiplication operation are provided so that the amount of data accumulated in the data buffer (accumulated data amount) approaches a preset target value (target data amount). In the method of estimating the bit rate,
The difference calculation means calculates the difference (target deviation amount) between the accumulated data amount and the target data amount, and outputs the target deviation amount.
The integral calculation 7 means performs an integral calculation on the target deviation amount, multiplies a predetermined coefficient (coefficient 7), and outputs the calculation result,
The smoothing calculation means performs the smoothing calculation on the target deviation amount and outputs the calculation result (smoothing target deviation amount).
A differential calculation 8 means performs a differential calculation on the smoothing target deviation amount, multiplies a predetermined coefficient (coefficient 8), and outputs the calculation result.
The adding means performs an addition operation on the smoothing target deviation amount output by the smoothing calculating means, the calculation result output by the integration calculating means 7 and the calculation result output by the differentiation calculating means 8 to obtain the calculation result. Output,
The averaging calculation means performs an averaging calculation on the calculation result output by the addition means and outputs the calculation result,
Multiplication 9 means multiplies the calculation result output by the averaging calculation means by a predetermined coefficient (coefficient 9) and outputs the calculation result;
A bit rate estimation method, wherein the calculation result output by the multiplication 9 means is estimated as a bit rate. In the bit rate estimating method according to any one of claims 7 to 10,
A bit rate estimation method, wherein the estimated bit rate is multiplied by a predetermined constant, and the calculation result is used as an estimated value of a frequency of a clock synchronized with the data transmission apparatus. Stored in the data buffer under a communication system in which a data transmission device that transmits data at a constant bit rate and a data reception device that receives the data via a communication network and stores the data in the data buffer are connected. A program for estimating the bit rate so that the amount of stored data (accumulated data amount) approaches a preset target value (target data amount),
A bit rate that causes a computer constituting the data receiving apparatus to execute a process of performing proportional, integral, and differential calculations based on an accumulated data amount and a target data amount, and a process of estimating a bit rate based on the calculation result Estimation program. The data is stored in the data buffer under a communication system in which the data transmitting device that transmits data at a constant bit rate and the data receiving device that receives the data via the communication network and stores the data in the data buffer are connected. A program for estimating the bit rate so that the amount of stored data (accumulated data amount) approaches a preset target value (target data amount),
In the computer constituting the data receiving device,
A difference calculation process for calculating the difference between the accumulated data amount and the target data amount (target deviation amount) and outputting the target deviation amount;
An integral operation 1 process for performing an integral operation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 1), and outputting the operation result;
Differential operation 2 processing for performing a differential operation on the target deviation amount and multiplying by a predetermined coefficient (coefficient 2) and outputting the operation result;
A target deviation amount output by the difference calculation process, a calculation result output by the integral calculation 1 process, and an addition process for performing an addition operation on the calculation result output by the differential calculation 2 process and outputting the calculation result;
A bit rate estimation program for executing a multiplication 3 process for multiplying a calculation result output by the addition process by a predetermined coefficient (coefficient 3), outputting the calculation result, and estimating the calculation result as a bit rate. The data is stored in the data buffer under a communication system in which the data transmitting device that transmits data at a constant bit rate and the data receiving device that receives the data via the communication network and stores the data in the data buffer are connected. A program for estimating the bit rate so that the amount of stored data (accumulated data amount) approaches a preset target value (target data amount),
In the computer constituting the data receiving device,
A difference calculation process for calculating the difference between the accumulated data amount and the target data amount (target deviation amount) and outputting the target deviation amount;
Integral calculation 4 processing for performing integral calculation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 4), and outputting the calculation result;
A smoothing calculation process for performing a smoothing calculation on the target deviation amount and outputting a calculation result (smoothing target deviation amount);
A differential operation 5 process for performing a differential operation on the smoothing target deviation amount, multiplying by a predetermined coefficient (coefficient 5), and outputting an operation result;
A smoothing target deviation amount output by the smoothing calculation process, an arithmetic result output by the integral calculation 4 process, and an addition process for performing an addition operation on the calculation result output by the differential calculation 6 process and outputting the calculation result; ,
A bit rate estimation program for executing a multiplication 6 process for multiplying a calculation result output by the addition process by a predetermined coefficient (coefficient 6), outputting the calculation result, and estimating the calculation result as a bit rate. The data is stored in the data buffer under a communication system in which the data transmitting device that transmits data at a constant bit rate and the data receiving device that receives the data via the communication network and stores the data in the data buffer are connected. A program for estimating the bit rate so that the amount of stored data (accumulated data amount) approaches a preset target value (target data amount),
In a computer constituting the data receiving device,
A difference calculation process for calculating the difference between the accumulated data amount and the target data amount (target deviation amount) and outputting the target deviation amount;
An integral calculation 7 process for performing integral calculation on the target deviation amount, multiplying by a predetermined coefficient (coefficient 7), and outputting the calculation result;
A smoothing calculation process for performing a smoothing calculation on the target deviation amount and outputting a calculation result (smoothing target deviation amount);
Differential operation 8 processing for performing a differential operation on the smoothing target deviation amount, multiplying by a predetermined coefficient (coefficient 8), and outputting the operation result;
A smoothing target deviation amount output by the smoothing calculation process, an calculation result output by the integral calculation 7 process, and an addition process for performing an addition operation on the calculation result output by the differential calculation 8 process and outputting the calculation result; ,
Averaging operation processing that performs an averaging operation on the operation result output by the addition processing and outputs the operation result;
A bit rate estimation program for executing a multiplication 9 process for multiplying a calculation result output by the averaging calculation process by a predetermined coefficient (coefficient 9), outputting the calculation result, and estimating the calculation result as a bit rate. In the bit rate estimation program according to any one of claims 12 to 15,
Bit rate estimation that causes a computer that constitutes the data receiving apparatus to further execute a process of multiplying the estimated bit rate by a predetermined constant and using the calculation result as an estimated value of a frequency of a clock synchronized with the data transmitting apparatus program.   The recording medium which recorded the bit rate estimation program as described in any one of Claim 12-16.

Images