JP2006065973A - Nonvolatile semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory in which the loss of initial setting data of a specified range is prevented and rewriting of the initial setting data can be enabled. <P>SOLUTION: The nonvolatile semiconductor memory has a memory cell array 1 in which electrically rewritable nonvolatile memory cells are arrayed and which stores the first initial setting data permitted to be rewritten and the second initial setting data prohibited to be rewritten, a sense amplifier circuit which performs data read-out of the memory cell array, and an initial setting data register in which the first and second initial setting data are transferred and held and which acts to regulate a memory operating condition. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM), and more particularly to an EEPROM having an initial setting data storage area in a memory cell array.

  In a large-scale semiconductor memory, a redundant circuit system is usually used to repair a defective chip. That is, a redundant cell array is prepared as the memory cell array, and a fuse circuit for programming defective address information found by the wafer test is also prepared. When the fuse circuit is programmed, when a defective address is input, control is performed to automatically replace the defective column or defective row with the redundant column or redundant row by detecting coincidence with the defective address held by the fuse circuit.

  The fuse circuit is used for storing various initial setting data for determining the operation condition of the memory in addition to the defective address information as described above. The same applies to the EEPROM.

  However, once the fuse circuit is programmed, it cannot be undone. In view of this, as an initial setting data storage circuit that replaces the fuse circuit, a method using an electrically rewritable nonvolatile memory cell that is the same as an EEPROM memory cell is also used.

  In particular, the method of setting the initial setting data storage area in the EEPROM memory cell array has advantages that the circuit configuration is simple and that verification and correction are easy (see Patent Document 1). In Patent Document 1, it is also proposed to store initial setting data as a set of data having a complementary relationship. This is preferable for confirming and securing the validity of the initial setting data.

  Initial setting data written in the memory cell array is automatically read when the power is turned on, transferred to the initial setting data register, and held. Thereafter, the memory operates under operating conditions defined by the data held in the initial setting data register.

Furthermore, in order to make the initial setting data more reliable, a method of storing the same initial setting data in a plurality of blocks in the memory cell array has been proposed (see Patent Document 2). As a result, even if the initial setting data stored in one block is destroyed, the operation conditions of the flash memory can be set because another block has the same initial setting data.
JP 2001-176290 A Japanese Patent Application Laid-Open No. 2002-117692

  A method of storing the initial setting data in the memory cell array is preferable because the initial setting data can be easily verified or rewritten. In particular, it is convenient for the user that the initial setting data can be rewritten by the user.

  However, if all of the initial setting data can be rewritten, there is a possibility that initialization of basic memory operation conditions, and thus normal memory operation may be disabled.

  An object of the present invention is to provide a non-volatile semiconductor memory device in which initial setting data in a certain range can be prevented from being lost and the initial setting data can be rewritten.

A nonvolatile semiconductor memory device according to one aspect of the present invention is provided.
A memory cell array in which electrically rewritable nonvolatile memory cells are arranged and stores first initial setting data that is allowed to be rewritten and second initial setting data that is prohibited from being rewritten,
A sense amplifier circuit for reading data from the memory cell array;
First and second initial setting data read from the memory cell array to the sense amplifier circuit is transferred and held, and has an initial setting data register that functions to define memory operating conditions.

  According to the present invention, it is possible to provide a non-volatile semiconductor memory device that can rewrite initial setting data by preventing loss of initial setting data in a certain range.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows a functional block configuration of a NAND flash memory according to an embodiment of the present invention, and FIG. 2 shows a configuration of a memory cell array 1. The memory cell array 1 is configured by arranging NAND cell units NU. Each NAND cell unit NU is connected to a plurality (16 in the illustrated example) of electrically rewritable nonvolatile memory cells M0 to M15 and both ends thereof connected to the source line CELSRC and the bit line BL, respectively. Select gate transistors S1 and S2.

  The control gates of the memory cells in the NAND cell unit are connected to different word lines WL0 to WL15. The gates of the selection gate transistors S1 and S2 are connected to selection gate lines SGS and SGD, respectively.

  A set of NAND cell units sharing one word line constitutes a block serving as a data erasing unit. As shown in FIG. 2, a plurality of blocks BLK0, BLK1,..., BLKn are arranged in the bit line direction. A set of memory cells sharing one word line constitutes one page (or two pages) as a unit of data reading and writing.

  The row decoder 2 selectively drives a word line and a selection gate line according to a row address, and includes a word line and a selection gate line driver. The sense amplifier circuit 3 is connected to the bit line to read data and also serves as a data latch for holding write data.

  Data exchange between the sense amplifier circuit 3 and the external input / output terminal I / O is performed via the I / O buffer 5 and the data bus 12. The sense amplifier circuit 3 is provided with a column gate for performing column selection, and the column decoder 4 performs this column gate control. By this column control, data transfer (reading and writing) is performed in units of one page between the sense amplifier circuit 3 and the memory cell array 1, whereas between the sense amplifier circuit 3 and the external input / output terminals, for example, Serial data transfer is performed in units of 1 byte.

  The address “Add” supplied via the input / output terminal I / O is transferred to the row decoder 2 and the column decoder 4 via the address register 6. The command “Com” supplied via the input / output terminal I / O is decoded by the controller 8. The controller 8 performs data write / erase sequence control and read operation control based on an external control signal and a command.

  The internal voltage generation circuit 9 is controlled by the controller 8 to generate various internal voltages necessary for write, erase and read operations. A booster circuit is used to generate an internal voltage higher than the power supply voltage. It is done. The status register 14 is for outputting a status signal R / B indicating whether the chip is in a read or write ready state or a busy state to the outside of the chip. The power-on reset circuit 11 detects power-on and causes the controller 8 to perform an initialization operation.

  The memory cell array 1 is set with an initial setting data storage area 13 for storing various initial setting data for determining the operating conditions of the memory. Specifically, the initial setting data includes (1) defective address data for replacing a defective cell, (2) voltage setting data such as a write voltage generated by the internal voltage generation circuit 9, and (3) process variation. There are voltage adjustment data for adjusting the internal voltage generated by the internal voltage generation circuit 9, and (4) a control parameter for the number of control loops for writing and erasing. Further, although not determining the operating conditions of the memory, an ID code such as a manufacturer ID or a chip ID is also included.

  The initial setting data storage area 13 is programmed before shipping the memory. When the power is turned on, the power-on reset circuit 11 detects this, and the controller 8 automatically reads the initial setting data to the sense amplifier circuit 3 and transfers it to the initial setting data register 10 via the data bus 12. Perform initialization. Various initial setting data are held in the initial setting data register 10, and the operating conditions of the memory are defined by this.

  Specifically, various internal voltages output from the internal voltage generation circuit 9 are determined based on voltage setting data and voltage adjustment data held in the initial setting data register 10, and a control loop for writing and erasing based on control parameters. The number is determined. The address match detection circuit 7 detects a match between an externally input address and a defective address held in the initial setting data register 10, and performs replacement control of the defective address.

  FIG. 3 shows a control flow of the initial setting operation. When power-on is detected, a power-on reset is applied (step S1), and after waiting for a predetermined time (step S2), the status register 14 is set to a busy state of R / B = “L” (step S3). Then, the initial setting data storage area 13 is sequentially read, and operation control is performed to transfer it to the initial setting data register 10 (step S4). When the reading and transfer of all the initial setting data are completed, the ready state of R / B = “H” is set (step S5).

  In the flash memory of this embodiment, the initial setting data storage area 13 of the memory cell array 1 is an area for storing initial setting data that can be rewritten (hereinafter simply referred to as a rewritable area) A and an initial state in which rewriting is prohibited. It is characterized in that it is divided into at least two areas B for storing setting data (hereinafter simply referred to as a rewrite prohibition area) B.

  For example, the initial setting data stored in the rewritable area A includes voltage setting data such as a write voltage, voltage adjustment data for adjusting an internal voltage, control parameters such as the number of control loops, and the like. These can be easily rewritten in response to the user's desire to switch the memory operating conditions.

  On the other hand, examples of the initial setting data stored in the rewrite prohibition area B include defective address data and ID codes. The defective address data is determined based on the test result at the wafer stage. If the user arbitrarily rewrites the defective address data, the necessary defective cell replacement is not performed, which is inconvenient. Making the ID code rewritable is also inconvenient because the chip history information is erased.

  FIG. 4 specifically shows the configuration of the portion related to the rewrite control of the initial setting data storage area 13 in the flash memory of this embodiment. Assume that one of the blocks BLK0 to BLKn-1 of the memory cell array 1, for example, RF-BLK is set as the initial setting data storage area 13. The block RF-BLK as the initial setting data storage area 13 is hereinafter referred to as a “ROM fuse block” in the sense that it is a ROM area of a fuse substitution circuit that normally does not rewrite data. Of the ROM fuse block RF-BLK, for example, pages P0 to P19 are defined as a rewritable area A, and the remaining pages P20 to P31 are defined as a rewritable prohibited area B.

  There are several specific methods for prohibiting rewriting of the initial setting data in the rewrite prohibition area B. One of them is to automatically rewrite the data in the rewrite prohibition area B once when the data rewrite request of the ROM fuse block RF-BLK is made. For this purpose, it is desirable for the chip to store the address of the rewrite prohibition area B. For example, the address of the rewrite prohibition area B is stored in the ROM fuse block RF-BLK, and the address is read out and held in the initial setting data register 10 in the above-described chip initialization operation.

  FIG. 5 shows a data rewrite control flow of the ROM fuse block RF-BLK when the above-described method is adopted, and FIGS. 6A to 6E show changes in the data states of the respective parts in the rewrite operation. The sequencer 22 in the controller 8 performs the rewrite control. In the controller 8, a buffer memory (data register) 21 capable of temporarily storing data for one block of the memory cell array 1 is prepared. Of the two address registers 6 and 10a shown in FIG. 4, the address register 10a is included in the initial setting data register 10 shown in FIG.

  As shown in FIG. 5, the data rewrite operation of the ROM fuse block RF-BLK is started by command input. Following the command input, an address and initial setting data to be rewritten are sequentially input (step S11). The address is a block address assigned to the ROM fuse block RF-BLK and a page address corresponding to the first page (P0) for accessing the rewritable area A in the block. This address is held in the address register 6. The

  The initial setting data DA ′ supplied from the outside replaces the initial setting data DA in the rewritable area A, and is transferred to the buffer memory 21 in the controller 8 via the data bus 12 as shown in FIG. 6A. And held until the rewrite sequence is completed.

  Next, prior to the block erase, as shown in FIG. 6B, the initial setting data DB of the rewrite prohibition area B of the ROM fuse block RF-BLK is read and transferred to the buffer memory 21 in the controller 8 (step S12). In this data reading and transfer, the operation of reading the data to the sense amplifier circuit 3 in units of one page in order from the first page P20 of the rewrite prohibited area B held by the address register 10a and transferring it to the buffer memory 21 is repeated. .

  Next, the ROM fuse block RF-BLK is collectively erased (step S13). This block erasing is performed by applying 0 V to all the word lines in the block and applying an erase voltage Vera to the p-type well in which the cell array is formed. As a result, all the memory cells of the ROM fuse block RF-BLK are in an erased state of “1” data by releasing electrons from the floating gate. FIG. 6C shows the state of this block erase.

  However, actual data erasing is performed by repeating erasing voltage application and verify reading. Based on the verify read result by the sense amplifier circuit 3, an erasure pass or fail determination is performed.

  If block erasure fails, a fail flag is output and the data rewrite operation ends. When the block erase is passed, as shown in FIG. 6D, new initial setting data DA 'held in the buffer memory 21 is written in the rewritable area A (step S14). This data writing is performed in units of pages by transferring write data to the sense amplifier circuit 3 page by page in order from the first page P0 of the rewritable area A held by the address register 6.

  In the page write, the channel of each NAND cell unit of the selected block is precharged based on the write data held by the sense amplifier circuit 3, the write voltage Vpgm is applied to the selected word line corresponding to the selected page, and the non-selected word line and the selected gate. This is done by applying a pass voltage Vpass to the line. As a result, in the memory cell to which “0” data is applied, electrons are injected into the floating gate and the threshold voltage is in the positive “0” data state. In the memory cell to which “1” data is applied, electron injection does not occur and the “1” data state is maintained.

  The actual writing is performed by repeating the writing voltage application and the verify reading. Then, based on the verify read result of the sense amplifier circuit 3, a write pass or fail determination is made. When writing is failed, a fail flag is output and the sequence is terminated. When the writing of one page is passed, the page address is incremented, the next page data is transferred to the sense amplifier circuit 3, and the same writing is repeated.

  When writing of all pages (P0-P19) is passed, the initial setting data DB saved in the buffer memory 21 is written back to the rewrite prohibition area B as shown in FIG. 6E (step S15). As described above, this write-back is also performed in units of pages by repeating the write voltage application and verify read. When the writing of all pages (P20 to P31) is completed, the initial setting data rewriting sequence is normally completed.

  As described above, in this embodiment, control is performed such that the initial setting data in the rewrite prohibition area B is saved and rewritten in the rewrite sequence of the ROM fuse block RF-BLK by a single command input. Thereby, the initial setting data in the rewritable area A can be rewritten without destroying the data in the rewrite prohibition area B in the ROM fuse block RF-BLK.

  In the above example, the initial setting data in the rewrite prohibition area B is saved in the buffer memory. However, it can be saved in an empty block in the memory cell array.

  As described in the prior art, in order to ensure reliability, the two ROM fuse blocks store the same initial setting data. In the following embodiment, when the two ROM fuse blocks RF-BLKa and RF-BLKb each include a rewrite prohibition area, a rewrite operation of these initial setting data will be described.

  FIG. 7 is a flow of the rewrite operation, and FIGS. 8A to 8F show the data state change of the two ROM fuse blocks RF-BLKa and RF-BLKb according to the operation flow. FIG. 8A shows an initial state in which the ROM fuse blocks RF-BLKa and RF-BLKb each include the rewritable area A and the rewritable prohibited area B and store the same initial setting data. The two ROM fuse blocks RF-BLKa and RF-BLKb are arranged, for example, in separate cell array planes.

  Data rewrite operation is started by command input. Following the command input, an address (initial value) for sequentially accessing the ROM fuse blocks RF-BLKa and RF-BLKb and rewrite data (initial setting data to be written in the rewritable area A) are input (step S21). . The input address is held in the address register 6 and the rewrite data is loaded into the buffer memory as in the previous embodiment.

  Subsequently, as shown in FIG. 8B, the data in one ROM fuse block RF-BLKa indicated by the address is erased all at once (step S22). Next, as shown in FIG. 8C, the initial setting data of the rewrite prohibition area B held in the ROM fuse block RF-BLKb is transferred to the corresponding rewrite prohibition area B of the erased ROM fuse block RF-BLKa. (Step S23).

  As in the previous embodiment, this data transfer is automatically controlled by the controller 8 on the assumption that the address of the rewrite prohibited area B is held in the initial setting data register 10. More specifically, the initial setting data of the rewrite prohibition area B is read in units of pages to the sense amplifier circuit of the plane to which the ROM fuse block RF-BLKb belongs, and this is the sense of the plane to which the ROM fuse block RF-BLKa belongs. It is transferred to the amplifier circuit. This is written into the rewrite prohibition area B of the ROM fuse block RF-BLKa.

  After this data transfer, as shown in FIG. 8D, the other ROM fuse block RF-BLKb is collectively erased (step S24).

  Next, as shown in FIG. 8E, the initial setting data transferred to the ROM fuse block RF-BLKa is transferred again to the rewrite prohibition area B of the ROM fuse block RF-BLKb and written back (step S25). This data transfer and write-back are also performed in units of pages under the same control as in step S23.

  Then, as shown in FIG. 8F, new initial setting data held in the buffer memory is written into the rewritable area A of the ROM fuse blocks RF-BLKa and RF-BLKb (step S26). This data writing can be executed simultaneously if each of the planes to which the two ROM fuse blocks RF-BLKa and RF-BLKb belong has a sense amplifier circuit. That is, the page address held by the address register 6 is the operation of transferring the data held in the buffer memory to each sense amplifier circuit page by page and writing it in the rewritable area A of the ROM fuse blocks RF-BLKa and RF-BLKb. Increment and repeat.

  By the rewrite sequence as described above, the initial setting data in the rewritable area A can be rewritten without destroying the initial setting data in the rewrite prohibition area B of the two ROM fuse blocks RF-BLKa and RF-BLKb. Note that the order of the data write-back in step S25 (FIG. 8E) and the new data write in step S26 (FIG. 8F) can be reversed.

  It is also possible to set a rewritable area and a rewritable area in the same page in one initial setting data storage area (ROM fuse block). FIG. 9 shows a portion related to rewriting of the initial setting data storage area 13 of such an embodiment in correspondence with FIG. As shown in the figure, a rewritable area A and a rewritable prohibited area B are set in a specific page PX in the ROM fuse block RF-BLK.

  FIG. 10 shows a data rewrite operation flow of the page PX of the ROM fuse block RF-BLK in this embodiment. In response to an address input and a command input (step S31), the data of the page PX of the ROM fuse block RF-BLK is read to the sense amplifier circuit 3, and among the read data, the initial setting data of the column corresponding to the rewrite prohibition area B is read. Then, the data is transferred to the initial setting data register 10 (step S32). However, if the initial setting data is read and transferred to the initial setting data register 10 upon power-on, the data transfer in step S32 is not necessary.

  Next, batch erase of the ROM fuse block RF-BLK is performed (step S33). If the block erase is passed, an address input, rewrite data input and command input are received (step S34), and the initial setting data of the ROM fuse block RF-BLK is rewritten.

  At this time, for the page PX, the initial setting data of the rewritable area A supplied from the outside is first loaded into the sense amplifier circuit 3, and then the initial setting data of the rewrite prohibition area B is the initial setting data. The data is transferred from the register 10 to the sense amplifier circuit 3 and loaded (step S35). The transfer operation of the above-described external rewrite data and write-back data from the initial setting data register 10 to the sense amplifier circuit 2 is to perform column control using a column address previously assigned to the rewrite prohibition area B. Is possible. The transfer operation of the rewrite data from the outside and the write-back data from the initial setting data register 10 to the sense amplifier circuit 2 may be reversed.

  Then, the page PX is written with the write data for one page held by the sense amplifier circuit 3 (step S36).

  As described above, with respect to the specific page PX in the ROM fuse block RF-BLK, it is possible to maintain the initial setting data in the rewrite prohibition area B and rewrite other initial setting data.

  So far, the case where the rewritable area and the rewritable area are set in the same data erasure unit (block) has been described. In this case, as described above, it is necessary to save the initial setting data in the rewrite prohibition area before erasing for data rewriting. On the other hand, when the rewritable area and the rewritable area are set as different data erasure units, the initial setting data protection of the rewritable area is easier.

  For example, when the block is an erasure unit, a ROM fuse block for storing rewritable initial setting data and a ROM fuse block for storing rewritable initial setting data are provided. In this case, if the ROM fuse block storing the initial setting data for which rewriting is prohibited is prohibited from external access, specifically, if no external address is assigned, the initial setting data is arbitrarily rewritten. Can be prevented.

  Even when a rewritable area and a rewritable area are set in the same ROM fuse block, if the data erasure unit is a page unit or a plurality of pages in the block, the initial setting data protection of the rewritable area is After all it becomes easy. That is, also in this case, the initial setting data is not arbitrarily rewritten by prohibiting external access to the page range that is a rewrite-inhibited area in the block.

  The NAND flash memory has been described above. However, the present invention is not limited to this, and can be similarly applied to a NOR type, an AND type, and a DINOR type flash memory.

1 is a diagram showing a functional block configuration of a NAND flash memory according to an embodiment of the present invention. FIG. It is a figure which shows the structure of the memory cell array of the flash memory. It is a figure which shows the control flow of the pattern on reset operation | movement of the flash memory. It is a figure which shows the structure of the part relevant to ROM fuse block rewriting of the flash memory. It is a figure which shows the data rewriting sequence of the ROM fuse block of the flash memory. It is a figure which shows the data state of the ROM fuse block and buffer memory for demonstrating the same data rewriting sequence. It is a figure which shows the data state of the ROM fuse block and buffer memory for demonstrating the same data rewriting sequence. It is a figure which shows the data state of the ROM fuse block and buffer memory for demonstrating the same data rewriting sequence. It is a figure which shows the data state of the ROM fuse block and buffer memory for demonstrating the same data rewriting sequence. It is a figure which shows the data state of the ROM fuse block and buffer memory for demonstrating the same data rewriting sequence. It is a figure which shows the data rewrite sequence of the ROM fuse block by other embodiment. It is a figure which shows the data state of two ROM fuse blocks for demonstrating the same data rewriting sequence. It is a figure which shows the data state of two ROM fuse blocks for demonstrating the same data rewriting sequence. It is a figure which shows the data state of two ROM fuse blocks for demonstrating the same data rewriting sequence. It is a figure which shows the data state of two ROM fuse blocks for demonstrating the same data rewriting sequence. It is a figure which shows the data state of two ROM fuse blocks for demonstrating the same data rewriting sequence. It is a figure which shows the data state of two ROM fuse blocks for demonstrating the same data rewriting sequence. It is a figure which shows the structure of the part in connection with ROM fuse block rewriting by other embodiment. It is a figure which shows the data rewrite operation | movement flow of the ROM fuse block of the embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory cell array, 2 ... Row decoder, 3 ... Sense amplifier circuit, 4 ... Column decoder, 5 ... I / O buffer, 6 ... Address register, 7 ... Address coincidence detection circuit, 8 ... Controller, 9 ... Internal voltage generation circuit DESCRIPTION OF SYMBOLS 10 ... Initial setting data register, 11 ... Power-on reset circuit, 12 ... Data bus, 13 ... Initial setting data storage area, A ... Rewritable area, B ... Rewrite prohibition area, 14 ... Status register, 21 ... Buffer memory, 22 ... Sequencer.

Claims (5)

A memory cell array in which electrically rewritable nonvolatile memory cells are arranged and stores first initial setting data that is allowed to be rewritten and second initial setting data that is prohibited from being rewritten,
A sense amplifier circuit for reading data from the memory cell array;
Non-volatile memory comprising: an initial setting data register for transferring and holding the first and second initial setting data read from the memory cell array to the sense amplifier circuit and for defining a memory operation condition Semiconductor memory device. The first and second initial setting data are set in one data erase unit in the memory cell array,
2. The non-volatile semiconductor memory device according to claim 1, wherein the second initial setting data is temporarily saved and rewritten in the first initial setting data rewrite sequence. 3. The nonvolatile semiconductor memory device according to claim 2, further comprising a buffer memory for temporarily saving the second initial setting data. The first and second initial setting data are set in different data erasing units of the memory cell array, and
2. The nonvolatile semiconductor memory device according to claim 1, wherein the second initial setting data storage area is prohibited from external access. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the memory cell array includes a plurality of blocks configured by arranging a plurality of NAND cell units.

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