JP2006064963A - Display data input device for flat display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display data input device for a flat display apparatus which can be realized inexpensively with a simple structure, capable of reducing a high frequency noise in a signal line and a driving section. <P>SOLUTION: The display data input device comprises; a plurality of differential output circuits for outputting each of a plurality of bits which form digital data, as differential output signals of positive polarity and negative polarity; a plurality of wiring lines to which the differential signals of the positive polarity and the negative polarity of the plurality of differential output circuits are respectively transmitted; a plurality of first differential circuits in which an input terminal of the positive polarity is connected to the wiring line of the positive polarity and an input terminal of the negative polarity is connected to the wiring line of the negative polarity respectively; and a plurality of second differential circuits in which the input terminal of the negative polarity is connected to the wiring line of the positive polarity and the input terminal of the positive polarity is connected to the wiring line of the negative polarity respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display data input device for a flat display device using liquid crystal, a light emitting element, plasma, or the like.

  The flat display device, when classified into large blocks, includes a display panel unit, a drive unit that supplies signals (display data and control signals) to the display unit of the display panel unit, and a power supply unit. The display panel unit has a display area in which pixels are two-dimensionally arranged. In the display area, a plurality of signal lines and a plurality of scanning lines are arranged so as to intersect with each other, and pixels are arranged at the plurality of intersections, respectively.

  The driving unit includes a scanning line driving unit that sequentially scans a plurality of rows in which pixels are arranged, and a signal line driving unit that supplies signals to the plurality of pixels in each row through the plurality of signal lines. The drive unit is provided on the printed wiring board.

  The signal line driver receives a digital signal from the timing controller and performs analog-digital conversion processing via the buffer circuit. The analog / digital converted signal is supplied to the pixel via the corresponding signal line.

  There is a wiring group for introducing a digital signal output from the timing controller into the buffer circuit on the substrate of the signal line driver. A digital signal to be supplied to pixels for one horizontal line is output to the wiring group at a high speed. In order to obtain this high-speed digital signal, there is a circuit of a differential drive system (see, for example, Patent Document 1).

  In the differential drive method, a positive signal and a negative signal, which are differential outputs, are used to transmit one bit of a digital signal. Then, it is possible to send 1 bit in a 1/2 clock period with a positive and negative differential signal having a small amplitude as compared with the case where 1 bit is sent with a single polarity signal in 1 clock period. That is, the data transfer amount can be increased.

In the case of this differential drive system, a positive output buffer circuit that transmits a positive signal on the transmitting side, a negative output buffer circuit that transmits a negative signal, and a positive input that receives a positive signal on the receiving side A buffer circuit and a negative input buffer circuit for receiving a negative signal.
JP 2004-102259 A

However, the positive polarity output buffer circuit and the negative polarity output buffer circuit, and the positive polarity input buffer circuit and the negative polarity input buffer circuit have a corresponding relationship with each other. That means
The output line of the positive output buffer circuit is connected to the positive input buffer circuit, and the output line of the negative input buffer circuit is connected to the negative input buffer circuit. For this reason, when signals of the same polarity flow in the same direction through each switch constituting each circuit, they may interfere with each other and generate high-frequency noise. In response to this high-frequency noise, the wiring group formed on the above substrate plays the role of an antenna and may send out jamming waves to the surroundings.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a display data input device and method for a flat panel display device that can reduce high-frequency noise in the signal line and the drive unit and can be realized at low cost with a simple configuration.

  In order to achieve the above object, the present invention provides a plurality of differential output circuits that output each of a plurality of bits forming digital data as positive and negative differential output signals, and the plurality of differential output circuits A positive input terminal is connected to the plurality of wirings through which the positive and negative differential output signals are transmitted, and the wiring through which the positive signals are output, respectively. A plurality of first differential input circuits in which a negative input terminal is connected to an output wiring, and a negative input terminal is connected to each of the wirings in which the positive signal is output, and the negative signal And a plurality of second differential input circuits in which positive and negative input terminals are connected to the wiring from which is output.

  As described above, the connection state of the plurality of differential output circuits with respect to the plurality of wirings through which the positive polarity and negative polarity differential output signals are respectively transmitted is the connection state of the plurality of first differential input circuits. The connection state of the plurality of second differential input circuits. For this reason, when multiple bits of digital data, for example, have the same logic and are continuous, the operation direction of the transistors or switch elements constituting each differential input circuit is all viewed from the wiring side. It will never be the same positive or negative side. For this reason, switching noise can also be mutually canceled, and generation of high frequency noise on the output side or wiring side can be suppressed. Moreover, since it is realized only by selecting the wiring connection, it can be implemented at low cost without adding any parts.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an overall configuration example of an embodiment of a flat display device to which the present invention is applied. The flat display device includes a display panel unit 100 having a glass substrate, a drive unit (to be described later) for supplying signals (display data and control signals) to the display unit of the display panel unit 100, and a power supply unit (not shown). Have. The display panel unit 100 includes a display area 101 in which pixels are two-dimensionally arranged. In the display area 101, a plurality of signal lines and a plurality of scanning lines are arranged so as to intersect with each other, and pixels are arranged at the plurality of intersections, respectively.

  The driving unit includes a scanning line driving unit 201 that sequentially scans a plurality of rows in which pixels are arranged, a signal line driving unit 202 that supplies signals to the plurality of pixels in each row through the plurality of signal lines, and timing. A control unit 203 is included. The driving unit is provided on the printed wiring board, and the timing control unit 203 is integrated into an integrated circuit.

  An input signal (digital data) is supplied to the signal line driving unit 202 via the timing control unit 203. The signal line driver 202 buffers input data, latches it in a latch circuit, converts this latched data into a digital signal, and outputs an analog signal to a signal line to which a corresponding pixel is connected.

  The scanning line driving circuit 201 selects a pixel column to which a signal is to be supplied based on the timing signal from the timing control unit 203.

  FIG. 2 shows an example of a characteristic part of the present embodiment. The timing control unit 203 outputs digital data via the differential output circuits DF1-DFn. Each differential output circuit DF1-DFn has one input terminal and two output terminals of positive polarity and negative polarity.

  The two output terminals of the differential output circuit DF1 are connected to the positive electrode side wiring PL1 and the negative electrode side wiring NL1. The ends of the wiring PL1 and the wiring NL1 are connected via a high resistance. Two output terminals of the differential output circuit DFn are connected to the positive electrode side wiring PLn and the negative electrode side wiring NLn. The ends of the wiring PLn and the wiring NLn are connected via a high resistance.

  Buffer circuits BF1-BF4 are connected in the middle of the wiring PL1, the wiring NL1, the wiring PLn, and the wiring NLn. Although four buffer circuits are shown in the figure, in an actual product, the number of buffer circuits corresponding to the number of pixels arranged on the horizontal line is provided. Also, two differential output circuits DF1-DFn are shown, but in actuality, for example, they are configured for 4-bit output or 8-bit output.

  Further, the outputs of the buffer circuits BF1 to BF4 are supplied to the digital / analog conversion circuits DAC1 to DAC4, respectively. The outputs of the digital-analog conversion circuits DAC1-DAC4 are supplied to the corresponding pixels.

  Here, the configuration of the buffer circuit BF1 will be described. Buffer circuit BF1 includes differential input circuits A11-A1n and NAND circuits ND11-ND1n. The differential input circuit A11 has a positive input terminal connected to the positive side wiring PL1, a negative input terminal connected to the negative side wiring NL1, and the differential input circuit A1n has a positive input terminal connected to the positive side wiring PLn. A negative electrode input terminal is connected to the negative electrode side wiring NLn. The output of the differential input circuit A11 is connected to the negative input terminal of the NAND circuit ND11, and the output of the differential input circuit A1n is connected to the negative input terminal of the NAND circuit ND1n. Here, the other positive input terminal of the NAND circuits ND11 to ND1n is connected to the power supply Vdd line.

  Next, the buffer circuit BF2 adjacent to the buffer circuit BF1 will be described. Buffer circuit BF2 includes differential input circuits A21-A2n and NAND circuits ND21-ND2n. The differential input circuit A21 has a negative electrode input terminal connected to the positive electrode side wiring PL1, a positive electrode input terminal connected to the negative electrode side wire NL1, and the differential input circuit A2n has a negative electrode input terminal connected to the positive electrode side wiring PLn. A positive electrode input terminal is connected to the negative electrode side wiring NLn. The output of the differential input circuit A21 is connected to the negative input terminal of the NAND circuit ND21, and the output of the differential input circuit A2n is connected to the negative input terminal of the NAND circuit ND2n. Here, the other positive input terminal of the NAND circuits ND21 to ND2n is connected to the ground line.

  The difference between the buffer circuits BF1 and BF2 is that the connection state between the differential input circuits A11-A1n and A21-A2n with respect to the wirings PL1, NL1, PLn, and NLn is different. The power supply Vdd line is connected to the NAND circuits ND11 and ND1n, while the ground line is connected to the NAND circuits ND21 and ND2n.

  Buffer circuit BF3 includes differential input circuits A31-A3n and NAND circuits ND31-ND3n. Buffer circuit BF4 includes differential input circuits A41-A4n and NAND circuits ND41-ND4n. The connection state between each element of the buffer circuit BF3 and the wirings PL1, NL1, PLn, and NLn is the same as that of the buffer circuit BF1, but the connection state between each element of the buffer circuit BF4 and the wirings PL1, NL1, PLn, and NLn is as follows. This is the same as the buffer circuit BF2.

  As described above, in the present embodiment, when a large number of buffer circuits are connected in parallel to the data transmission line, the polarity of the differential input connected to the differential output is inverted every other buffer circuit. It is. For this reason, for example, it is assumed that the bit “1” is continuously output from the differential output circuits DF1 to DFn. Then, when “1” is output from the differential input circuit A11-A1n and the differential input circuit A31-A3n, “0” is output from the differential input circuit A21-A2n and the differential input circuit A41-A4n. The That is, the output of the differential input circuit is averaged as the data logic level. This is because the polarity is inverted every other buffer circuit when the wiring and the differential input circuit are connected as described above.

  If this relationship is not present, unnecessary high frequency noise is generated by continuously outputting “1” of the same polarity from the differential input circuits A11-A1n, A31-A3n, A21-A2n, A41-A4n all at once. May occur.

  However, according to the present embodiment, unnecessary high frequency noise can be reduced by the above connection relation. Let us look at the direction of operation of the transistors or switch elements constituting the differential input circuit. Now, even if the same bit is output to the parallel wirings, the plurality of switch elements are not operated in the same direction, but are classified into elements operating in the same direction and elements operating in the reverse direction. For this reason, potential fluctuations appearing in the wiring are also averaged, and unnecessary radiation is unlikely to occur. Therefore, high frequency noise can be reduced.

  Further, when the drive circuit is configured as a printed wiring, the effect of the present invention can be obtained only by selecting the wiring connection. In some embodiments, an inversion process using a NAND circuit and a non-inversion process circuit are provided, but the buffer circuit (source drive IC) is inverted so as to be compatible with two types of liquid crystal cells, normally black and normally white. A non-inverted output switching function may be provided. When such a buffer circuit (source drive IC) is used, it is possible to perform simple output polarity selection.

  Here, since the outputs of the differential input circuits A21-A2n and A41-A4n are those in which the original data polarity is intentionally inverted, it is necessary to restore the outputs. For this purpose, the power supply Vdd line is connected to the NAND circuits ND11 to ND1n, while the ground line is connected to the NAND circuits ND21 to ND2n.

  Data output from the buffer circuits BF1 to BF4 is converted from digital to analog and supplied to the corresponding pixels. Therefore, a gate circuit is provided at the output portion of the digital-analog conversion circuit DAC1-DAC4, and an analog signal is derived from the gate circuit only when desired pixel data is converted into an analog signal. In the operation until the data output from the timing control unit 203 is analog-converted, the buffer circuits BF1-BF4 and the digital-analog conversion circuits DAC1-DAC4 operate simultaneously and synchronously.

The present invention is not limited to the above embodiment. That is, in the previous embodiment,
When a large number of buffer circuits are connected in parallel to the wiring for transmitting data, the polarity of the differential input connected to the differential output is inverted every other buffer circuit. However, it is not limited to such a connection relationship, and a connection relationship as described below may be used.

In FIG. 3, the same parts as those in FIG. In the embodiment of FIG. 3, buffer circuits having different input polarities are classified and arranged separately on the right side and the left side of the display area. In FIG. 3, the relationship between the differential output circuits DF1-DFn, the wirings PL1, NL1, PLn, NLn, and the buffer circuits BF2, BF4 is the same as that of the embodiment of FIG. ing. Next, on the left side of the display area, differential output circuits DF1a-DFna, wirings PL1a, NL1a, PLna, NLna, and buffer circuits BF1-BF3 are arranged. The differential output circuits DF1a-DFna operate simultaneously in the same manner as the differential output circuits DF1-DFn, and output data. Alternatively, the differential output circuits DF1a to DFna may be operated when the left data is output, and the differential output circuits DF1 to DFn may be operated when the right data is output. Furthermore, the differential output circuits DF1-DFn at the same time,
Although the differential output circuits DF1a-DFna operate, each may share and output the right data and the left data.

  Here, the relationship among the differential output circuits DF1a-DFna, the wirings PL1a, NL1a, PLna, NLna, and the buffer circuits BF1, BF3 is the same as that of the embodiment of FIG. That is, the differential output circuits DF1a-DFna and the wirings PL1a, NL1a, PLna, NLna correspond to the differential output circuits DF1-DFn and the wirings PL1, NL1, PLn, NLn.

  Even with the above configuration, the probability of generating unnecessary high-frequency noise is reduced by simultaneously outputting “1” of the same polarity from the differential input circuits A11-A1n, A31-A3n, A21-A2n, A41-A4n. it can.

  The present invention is not limited to the above embodiment. In the embodiment of FIG. 1, for example, for all “1” inputs, the outputs of the differential input circuits A11-A1n, A31-A3n are “1”, the differential input circuits A21-A2n, A41-A4n. The output was “0”. Here, in order to invert the outputs of the differential input circuits A21-A2n and A41-A4n, one input of the NAND circuits ND21-ND2n and ND41-ND4n is connected to the ground line.

  In other words, adjustment is performed at the output stage of the buffer circuit in order to match the logic of the output data with the logic of the input data. However, this logic matching method is not limited to the above embodiment. That is, a method of performing connection control between the wiring and the differential input circuit and polarity control of input data may be used.

  FIG. 4 shows another embodiment of the present invention. The timing controller 203 is provided with differential output circuits DF1-DF4. The outputs of the NAND circuits n01-n04 are connected to the input terminals of the differential output circuits DF1-DF4, respectively. One input terminal of each of the NAND circuits n01 and n03 is connected to the power supply Vdd line, and one input terminal of each of the NAND circuits n02 and n04 is connected to the ground line. Each other input terminal of the NAND circuits n01 to n04 is supplied with a corresponding bit of data.

  The tips of the negative electrode side wiring NL1 and the positive electrode side wiring PL1 of the differential output circuit DF1 are connected via a high resistance. Similarly, the negative electrode side wirings and the positive electrode side wirings of the other differential output circuits DF2-DF4 are also connected at their tips via high resistances.

  The buffer circuit BF1 includes differential input circuits a11-a14 and NAND circuits n11-n14. The positive input of the differential input circuit a11 is connected to the positive polarity side wiring PL1, and the negative polarity input is connected to the negative polarity side wiring NL1. On the other hand, the positive polarity input of the adjacent differential input circuit a12 is connected to the negative polarity side wiring NL2, and the negative polarity input is connected to the positive polarity side wiring PL2. The positive input of the next differential input circuit a13 is connected to the positive polarity side wiring PL3, and the negative polarity input is connected to the negative polarity side wiring NL3. The positive input of the next differential input circuit a14 is connected to the negative polarity side wiring NL4, and the negative polarity input is connected to the positive polarity side wiring PL4. As described above, in the present embodiment, the respective inputs of the corresponding differential input circuits a11 to a14 are connected to the output wirings of the differential output circuits DF1 to DF4 with their polarities alternately inverted. .

  The buffer circuit BF2 also includes differential input circuits a21-a24 and NAND circuits n21-n24. The connection relationship between these differential input circuits a21-a24 and the wirings PL1-PL4, NL1-NL4 is the same as that of the previous buffer circuit BF1.

  According to the embodiment described above, the circuit connection state is a circuit connection state in which the polarity-inverted data is taken into the buffer circuit in units of buffer circuits. However, in the embodiment shown in FIG. 4, the circuit connection state is a circuit connection state in which data whose polarity is inverted in units of differential input circuits is taken into the differential input circuit group.

  In addition, in the embodiment shown in FIGS. 2 and 3, the process for matching the final data output logic with the input data logic is executed at the final stage of the buffer circuit. However, in the embodiment of FIG.

  The present invention is not limited to the names of the circuits described above. The timing control unit 203 may be referred to as a timing control IC. The differential output circuit may be referred to as a differential driver, and the differential input circuit may be referred to as a differential receiver. The buffer circuit may be referred to as a source drive IC.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

The figure which shows the example of a whole structure of one Embodiment of the flat display apparatus to which this invention was applied. The figure which takes out and shows the principal part of one embodiment of this invention. The figure which takes out and shows the principal part of other embodiment of this invention. The figure which takes out and shows the principal part of other embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 101 ... Display area, 202 ... Signal line drive part, 203 ... Timing control part (timing control IC), DF1, DFn ... Differential output circuit (differential driver), NL1, NLn ... Negative polarity side wiring, PL1, PLn ... Positive side wiring, A11, A1n, A21, A2n, A31, A3n, A41, A4n ... Differential input circuit (differential receiver), ND11, ND1n, ND21, ND2n, ND31, ND3n, ND41, ND4n ... NAND circuit, DAC1-DAC4: Digital-analog conversion circuit.

Claims (7)

A plurality of differential output circuits for outputting each of a plurality of bits forming the digital data as positive and negative differential output signals;
The positive polarity of the plurality of differential output circuits and a plurality of wirings through which negative differential output signals are transmitted,
A plurality of first differential input circuits each having a positive input terminal connected to the wiring from which the positive signal is output and a negative input terminal connected to the wiring from which the negative signal is output; ,
A plurality of second differential input circuits each having a negative polarity input terminal connected to the wiring for outputting the positive polarity signal and a positive polarity input terminal connected to the wiring for outputting the negative polarity signal; ,
A display data input device for a flat-panel display device. In order to match the logical state of the digital data on the input side and the output side,
A non-inverting output circuit for outputting the output of each first differential input circuit in a non-inverting state;
An inverting output circuit for outputting the output of each second differential input circuit in an inverted state;
The display data input device for a flat display device according to claim 1, further comprising: Including a plurality of first differential input circuits, a plurality of positive polarity buffer circuits to which all bits of the digital data are input, and the plurality of second differential input circuits, A plurality of negative polarity buffer circuits to which bits are input, and
3. The display data input device for a flat display device according to claim 2, wherein the positive and negative buffer circuits are alternately arranged. Including a plurality of first differential input circuits, a plurality of positive polarity buffer circuits to which all bits of the digital data are input, and the plurality of second differential input circuits, A plurality of negative polarity buffer circuits to which bits are input, and
The plurality of positive polarity buffer circuits are arranged on either the left or right side of the display area of the display device, and the plurality of negative polarity buffer circuits are arranged on the left or right side of the display area of the display device. The display data input device for a flat display device according to claim 2.   2. The flat display device according to claim 1, wherein the plurality of second differential input circuits are included in the same number in one buffer circuit, and a plurality of the buffer circuits are configured. Display data input device. Connected to the input side of each of the plurality of differential output circuits,
A plurality of non-inverting circuits that provide input bits of the plurality of differential output circuits corresponding to the plurality of first differential input circuits through the plurality of wirings in a non-inverting state;
A plurality of inverting circuits for providing input bits of the plurality of differential output circuits corresponding to the plurality of second differential input circuits in an inverted state through the plurality of wirings;
6. The display data input device for a flat display device according to claim 5, further comprising:   6. The display data input device for a flat display device according to claim 3, wherein a digital-analog conversion circuit is connected to the output side of each of the plurality of buffer circuits.

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