JP2006062132A - Image data conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform processing efficiently by switching internal circuitry depending on the data width of a memory to be connected in a circuit for converting the raster image data of an ink jet printer into column data. <P>SOLUTION: The image data conversion circuit comprises a means for inputting data of raster formant, and changes a region being stored in an image conversion buffer depending on the bit width of data being inputted by the input means. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a conversion circuit that stores data sequentially sent in a raster direction in a memory and performs data conversion.

A recording head of an ink jet printer (recording apparatus) has a plurality of recording elements arranged in the vertical direction and outputs a plurality of raster images simultaneously. In the data processing inside the recording apparatus, a plurality of raster data is extracted for each column and the data is transferred to the recording head. In this raster / column conversion circuit, an intermediate buffer consisting of a register of the product of the input data width and the number of rasters is required.
Japanese Patent Laid-Open No. 10-217584

  An image conversion circuit connected to a memory having an input raster data bus width of 64 bits and an output column data bus width of 32 bits has an image conversion buffer for storing 32 64-bit raster data, and requires a 64 × 32 = 2048 bit register. . In order to sequentially extract the column data, writing is performed until the image conversion buffer becomes full, so that column data cannot be read during that time.

  In order to increase the speed of image conversion, a method of expanding the input raster data bus width is employed. In this case, wiring is easily performed even if the bus width is expanded for the memory configured in the same circuit as the image conversion circuit, but for the external memory to which a larger capacity can be connected, the external pin It is difficult to expand the data bus width due to restrictions of the above.

  For a memory with a small data width, two internal intermediate buffers are prepared and a double buffer structure is used, so that the processing speed can be increased by simultaneously performing writing and reading. However, when a double buffer structure is used for a memory having a large data width, there arises a problem that the number of internal intermediate buffers increases.

  The present invention relates to an image conversion circuit for converting raster image data into column data, in accordance with the data bus width of the memory connected to the internal intermediate buffer, for a memory having a large bus width, the entire buffer area. Processing is performed in a single buffer structure in which reading and writing are performed alternately. For a memory having a small bus width, the buffer area is divided into two parts and switched to a double buffer structure in which writing and reading can be performed simultaneously.

  As described above, by having the function of switching the internal buffer structure in accordance with the data width of the memory to be connected, high-speed processing can be performed while effectively using the internal buffer circuit.

  High-speed processing for internal memory with a small capacity and large data width, and high-speed processing for external memory with a large capacity and small data width, both functions can be realized in the same circuit without wasting the internal intermediate buffer area is doing.

Example 1
In FIG. 1, an image data conversion circuit 101 according to the present invention includes a sequence control block 102 for instructing an internal operation of the circuit, a DMA interface unit for reading data from the memory, and two blocks 103 and 104 having a data width different from that of the target memory. The shift register unit 105 temporarily stores raster data and outputs column data, and the DMA interface block 106 writes the output column data to a memory.

  The DMA interface block 103 is connected to a memory 107 for storing raster data via a DMA control block 108. Similarly, the DMA interface block 104 is connected via a DMA controller block 110 to a memory 109 having a different bus width for storing raster data. The memory 107 is an example of a large-capacity low-speed memory connected to the outside of the IC that constitutes the image data conversion circuit. The memory 109 is a small-capacity memory that is configured inside the same IC as the image data conversion circuit. This memory is accessed at high speed.

  As shown in FIG. 2, the raster image data is transmitted in the order of raster arrangement, and when the image width is reached, the raster image data is folded back to the beginning of the next raster. As shown in FIG. 2, when 64-bit data is transmitted in the order of 1, 2, 3,..., 1 raster 3 data × 32 raster data 1 to 96 are temporarily stored in the memory.

  The temporary storage memory shown in FIG. 3 shows a state in which the image data conversion circuit of the present invention is arranged and arranged in an order that is convenient when the raster image data is read out.

  Since the column data is sequentially extracted from the most significant bit of the raster image data, it is arranged in a format in which a plurality of rasters can be read continuously with the received data width. Specifically, when 1 data of the first raster is arranged at address 0x000000 in the temporary storage memory, data 2 is arranged at address 0x000100 obtained by adding 32 bits of 64 bits = 8 bytes, and data 3 is further addressed 32. It is arranged at the address 0x000200 after adding the minutes.

  Since the 4th data of the next raster is the raster data below the 1st data, it is arranged at the address 0x000008 immediately after the 1st data, the data 5 is arranged at the address 0x000108, and the data 6 is arranged at the address 0x000208. The

  When the data arranged in this way is continuously read from address 0x000000 to address 0x0000F8, data of 1,4,7,... 91,94 is obtained, and the data width is 64 bits × 32 (32 rasters). Reading can be performed. This data is stored in a buffer in the image data conversion circuit of the present invention, and data is read out for each column.

  The aforementioned raster data is stored in the order of R0, R1,... R31 in the buffer in the image data conversion circuit shown in FIG. After the 32 pieces of raster data are stored, the 64th bit data of each of R0, R1... R31 is extracted as C63, the 63th bit data as C62. The 32nd bit of C63 data is the 64th bit data of R0, the 31st bit of the C63 data is the 64th bit data of R1, the second bit of C63 is the 64th bit of R30, and the 1st bit of C63 is the 64th bit of R31. It is converted as eye data and written to the subsequent memory.

  The shift register shown in FIG. 5 shows the structure of a buffer in the image data conversion circuit. The register for storing each raster image has a bit shift structure, and performs bit shift in the upper bit direction every time a column image is extracted. After the C63 column data is extracted, the C62 data is shifted to the C63 register. Therefore, the column data extraction is realized by repeating the C63 register reading and the bit shift.

(Example 2)
As described in the first embodiment, the image data conversion circuit extracts the column data after storing all the raster data in the buffer. Therefore, the raster data storage operation and the column data extraction operation cannot be performed simultaneously. Therefore, the reduction in processing speed is compensated by expanding the bit width of the raster data to be stored.

  However, when the bit width of the memory connected to the image data conversion circuit cannot be expanded, for example, to connect to a large-capacity external memory, the bit width is changed from the 64-bit raster data to the 32-bit raster data due to I / O pin limitations. May be reduced. In such a case, a method of effectively utilizing the capacity of 64 bits × 32 (raster) buffers of the image data conversion circuit will be described.

  FIG. 6 shows a configuration in which image data is transmitted in the order of raster arrangement and is turned back to the head portion of the next raster when the image width is reached. As shown in FIG. 6, when 32-bit width data is transmitted in the order of 1, 2, 3,..., 1 raster 6 data × 32 raster data 1 to 192 are temporarily stored in the memory.

  The temporary storage memory shown in FIG. 7 is arranged in an order convenient for the image data conversion circuit of the present invention to read out the raster image data, and the image data conversion circuit of the present invention is arranged in the column. It shows how data is extracted in units.

  Since the column data is sequentially extracted from the most significant bit of the raster image data, it is arranged in a format in which a plurality of rasters can be read continuously with the received data width. Specifically, when 1 data of the first raster is arranged at address 0x000000 in the temporary storage memory, data 2 is arranged at address 0x000080 obtained by adding 32 bits of 32 bits = 4 bytes, and data 3 is further addressed 32. It is arranged at the address 0x000100 after adding the minutes.

  Since the next 7 data of the raster is the raster data below the 1 data, it is arranged at the address 0x000004 immediately after the 1 data, and the 13 data below it is arranged at the address 0x000008.

  When data arranged in this way is continuously read from addresses 0x000000 to 0x00007C, data of 1,7,13,... 181,187 is obtained, and the data width is 32 bits × 32 (32 rasters). Reading can be performed. This data is stored in a buffer in the image data conversion circuit of the present invention, and data is read out for each column.

  The buffer in the image data conversion circuit shown in FIG. 8 is the same circuit as described above, and there are 64 bits × 32 registers. A register group obtained by dividing a 64-bit register into upper 32 bits × 32 is RxU (x = 0, 1, 2,... 31), and a register group obtained by dividing the lower 32 bits × 32 is RxD (x = 0, 1, 2,... 31). ), The aforementioned 32-bit × 32 raster data is stored in RxU.

  When the 32-bit data of RxU raster data R0, R1,... R31 is column data C31, the data is extracted in the order of C31, C30,.

  The shift register shown in FIG. 9 shows the structure of a buffer in the image data alteration circuit. A 64-bit high-order 32-bit register group RxU and a low-order 32-bit register group RxD are shifted independently by another trigger. Therefore, after the raster data is stored in the upper buffer RxU, the column data is extracted, and at the same time, the next raster data 2, 8, 14,... 182 and 188 are read from the memory 0x000080 to the address 0x0000FC in the previous stage, and the lower buffer. Processing stored in RxD can be performed simultaneously.

The block diagram which shows the outline of an image data conversion circuit. The figure which shows the transfer data order of the raster image data with respect to memory with a wide data width. The figure which shows a mode that the raster image data of FIG. 2 was stored in the memory for reading. The figure which shows a mode that column data is taken out from the raster data on the image conversion register. Schematic diagram of a shift register for image conversion. The figure which shows the transfer data order of the raster image data with respect to memory with a narrow data width. The figure which shows a mode that the raster image data of FIG. 6 was stored in the memory for reading. The figure which shows a mode that column data is taken out from the raster data of the register for image conversion. Schematic diagram of a shift register for image conversion at the time of buffer division.

Explanation of symbols

101 Image data conversion circuit for implementing this description 102 Sequence controller 103 DMA interface block for reading data 104 DMA interface block for reading data 105 Shift register for storing read data 106 DMA interface block for writing data 107 Large data bit width is small Capacity memory 108 DMA controller 109 Small capacity memory with a wide data bit width 110 DMA controller 111 DMA controller 112 Storage memory after image conversion

Claims (7)

Input means for inputting raster format data;
An image data conversion circuit, wherein an area to be stored in an image conversion buffer is changed according to a bit width of the data input by the input means.   2. The image data conversion circuit according to claim 1, wherein the image conversion buffer is used as one area, and writing and reading are alternately performed.   2. The image data conversion circuit according to claim 1, wherein the image conversion buffer is used as two areas having the same size, and a writing process for one area and a reading process for the other area are simultaneously performed.   2. The image data conversion circuit according to claim 1, wherein the most significant bit of each data stored in the image conversion buffer is extracted and output as vertical / horizontal conversion processing data.   2. The image data conversion circuit according to claim 1, wherein each data stored in the image conversion buffer is shifted in a most significant bit direction.   2. The image data according to claim 1, wherein the most significant bit of each of the upper data and the lower data obtained by dividing each data stored in the image conversion buffer is extracted and output as vertical / horizontal conversion processing data. Conversion circuit.   2. The image data conversion circuit according to claim 1, wherein each of the data stored in the image conversion buffer is shifted in the most significant bit direction of the upper data and the lower data divided into two.

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