JP2006060156A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the resistance variations of an extremely shallow junction or the variations of a junction leakage current in the formation of the extremely shallow junction. <P>SOLUTION: A bonding diffusion layer region 2 in which the S/D diffusion layer of one PMOS transistor demarcated by an element isolation region 1 is divided into a first junction diffusion block 2a of the same size, a second junction diffusion block 2b and a third junction diffusion block 2c separated from each other. An input gate electrode 3 is arranged on a plurality of the divided junction diffusion blocks. Power supply wiring 4 and output wiring 5 are formed. In this manner, the junction diffusion layer region of the MOS transistor is divided. Thereby, in the extremely shallow junction formed by the heat treatment of a low thermal basset like flash lamp annealing by dividing the bonding diffusion layer region of a MOS transistor, the resistance variations or the variations of the junction leakage current is suppressed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to an ultra-shallow junction diffusion layer formed on a semiconductor substrate surface and a method for forming the diffusion layer.

  Miniaturization of an element such as an insulated gate field effect transistor (referred to as a MOS transistor) that constitutes a semiconductor device is most effective for improving the performance of the semiconductor device. Various manufacturing techniques essential to the manufacture of these are being researched and developed, and the design standards are being vigorously advanced from the manufacturing techniques of the design standards of 130 nm to 90 nm at the current mass production level toward the manufacturing techniques of 65 nm and 45 nm.

  Under such circumstances, various studies have been made to make the source / drain diffusion layers of MOS transistors thinner. In the case of a diffusion layer doped with boron impurities which are p-conductivity type impurities, it is usually more difficult to make shallow junctions than in the case of n-conductivity type impurities, but the junction depth of the source / drain diffusion layers of the p-channel MOS transistor Therefore, an ultra-shallow junction of 20 nm or less is required, and the development of a control technique for the ultra-shallow junction is energetically advanced.

  Hereinafter, the formation of the ultra-shallow junction diffusion layer as described above will be described in detail with reference to FIGS. FIG. 3 is a CMOS inverter which is a basic circuit of a semiconductor device, and FIG. 4 is a pattern layout diagram of this CMOS inverter circuit. In the CMOS inverter circuit of FIG. 3, a PMOS transistor 101 which is a p-channel MOS transistor and an NMOS transistor 102 which is an n-channel MOS transistor are connected in series between a power supply voltage Vdd and a ground voltage Vss. Then, an input signal is applied to the input terminal 103 and an output signal is output from the output terminal 104.

  The pattern layout of the CMOS inverter circuit is as shown in FIG. As shown in FIG. 4, a junction diffusion layer region 201 which is an element active region of a PMOS transistor and forms an S / D (source / drain) diffusion layer is provided, and an input gate electrode 202, a power supply wiring 203, and an output wiring 204 are provided. Is formed. Here, the power supply wiring 203 and the output wiring 204 are electrically connected to the junction diffusion layer region 201 through the contact holes 205 and 206, respectively. Similarly, a junction diffusion layer region 207 forming an S / D diffusion layer of the NMOS transistor is provided, and the ground wiring 208 and the output wiring 204 are electrically connected to the junction diffusion layer region 207 through the contact holes 209 and 210, respectively. . The input gate electrode 202 is also commonly provided as a gate electrode of the NMOS transistor.

  A semiconductor device is an integrated body of MOS transistors or elements of various types and sizes. In particular, in order to obtain a predetermined circuit performance, it is usual to change the ratio (W / L) of the gate length (L) and the gate width (W) of the MOS transistor. For this reason, S / D diffusion layers of MOS transistors of various sizes exist on the semiconductor substrate. In the pattern layout of FIG. 4, the junction diffusion layer region 201 on the PMOS transistor side is larger than the junction diffusion layer region 207 on the NMOS transistor side. This is because the gate width (W) of the PMOS transistor needs to be larger than that of the NMOS transistor in order to obtain a predetermined circuit performance.

  In the CMOS transistor constituting the inverter circuit as described above, the S / D diffusion layer of the MOS transistor is used in order to maintain the performance (high on-current, low off-current) according to the well-known scaling law trend. Requires ultra shallow junctions. Therefore, instead of RTA (rapid heating annealing), which has been widely used so far, various extremely short-time heat treatments such as spike annealing, flash lamp annealing, laser annealing, etc. aiming at realization of ultra-shallow junction, that is, low thermal budget Heat treatment is required (see, for example, Patent Document 1). Here, the processing time of RTA is several seconds (seconds), but the processing time of the low thermal budget is as short as several milliseconds.

  However, according to the study by the inventors, it has been found that in the heat treatment of the above-described low thermal budget, the sheet resistance of the diffusion layer in the bonding region becomes dependent on the size of the bonding region. FIG. 5 shows the correlation between the width of the diffusion layer and the sheet resistance when the ultrashallow junction of the CMOS transistor constituting the inverter circuit is formed using the flash lamp annealing. Here, the horizontal axis represents the width W (corresponding to the gate width (W)) of the S / D diffusion layer of the PMOS transistor, and the vertical axis represents the sheet resistance of the S / D diffusion layer. FIG. 5 shows that the sheet resistance gradually decreases as the diffusion layer width W decreases.

  FIG. 6 shows the correlation between the diffusion layer area of the ultra-shallow junction and the junction leakage current when the ultra-shallow junction is similarly formed using flash lamp annealing. It can be seen that the smaller the diffusion layer area, the smaller the junction leakage current.

  The events described with reference to FIGS. 5 and 6 occur similarly in spike annealing and laser annealing, which are heat treatments of a low thermal budget. On the other hand, although not shown, the sheet resistance value is constant regardless of the width of the diffusion layer because sufficient heat is applied in the conventional annealing such as RTA. Similarly, the value of the junction leakage current is constant regardless of the diffusion layer area.

In the heat treatment of the low thermal budget necessary for forming the ultra-shallow junction, a minimum amount of heat is supplied. For this reason, a subtle temperature difference occurs depending on the size of the junction diffusion layer region, which appears as a difference in sheet resistance and junction leakage. This temperature difference is particularly likely to occur when the temperature is lowered than when the temperature is raised, and is related to the thermal conductivity of the insulating film or silicon material on the semiconductor substrate. On the other hand, in the conventional heat treatment by RTA, which does not require ultra-shallow junction, a sufficient amount of heat can be supplied, so the above problem does not occur.
JP 2004-063574 A

  In a conventional S / D diffusion layer of a CMOS transistor of a semiconductor device or a diffusion resistor using a PN junction for an analog element, S / Ds of various sizes (shapes, areas) are required to obtain predetermined circuit performance. A diffusion layer region or a diffusion layer region for a resistance element has been formed. Here, when an extremely short heat treatment process necessary for realizing the ultra-shallow junction required in a fine CMOS transistor after the 65 nm technology node is performed, the size of the junction region as described with reference to FIGS. There arises a problem that the sheet resistance or junction leakage current of the diffusion layer is different. Then, depending on the size of the semiconductor element constituting the semiconductor device, for example, the performance of the MOS transistor and the performance of the analog element change, which causes a big problem that the design of the semiconductor device becomes very difficult.

  The present invention has been made in view of the above-described circumstances, and solves the resistance variation of the ultra-shallow junction or the junction leakage current in the formation of the ultra-shallow junction of the S / D diffusion layer of, for example, a MOS transistor after the 65 nm technology node. An object of the present invention is to provide a diffusion layer structure and a manufacturing method thereof.

  In order to solve the above problems, an invention according to a semiconductor device has a configuration in which one PN junction of a semiconductor element formed on a semiconductor substrate is divided into a plurality of diffusion layers. The source diffusion layer or the drain diffusion layer of one insulated gate field effect transistor formed on the semiconductor substrate is divided into a plurality of diffusion layers.

  The invention relating to the method for manufacturing a semiconductor device includes a step of dividing a predetermined region on the surface of the semiconductor substrate into a plurality of blocks and introducing impurities into each block, and activating the impurities in each block by a flash lamp annealing method. Forming an impurity diffusion layer in each block, and the impurity diffusion layers of all the blocks are configured as one PN junction of a semiconductor element.

  In the above invention, the lamp irradiation time in the flash lamp annealing process is preferably 10 msec or less.

  According to the configuration of the present invention, the ultra-shallow junction of the micro-CMOS transistor having the ultra-shallow junction can be obtained even if the ultra-short heat treatment is performed in order to realize the ultra-shallow junction required in the micro-CMOS transistor after the 65 nm technology node. Variations in sheet resistance and junction leakage current can be suppressed, and the semiconductor device can be easily designed.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a pattern layout diagram of a CMOS inverter circuit constituting a semiconductor device and corresponds to FIG. 4 of the prior art. FIG. 2 is a flowchart of the manufacturing process of the semiconductor device in this embodiment.

  As shown in FIG. 1, a so-called element active region defined by an element isolation region 1 is formed on the surface of a semiconductor substrate, and a junction which is the element active region in which an S / D diffusion layer of one PMOS transistor is formed. The diffusion layer region 2 is divided into a first junction diffusion block 2a, a second junction diffusion block 2b, and a third junction diffusion block 2c of the same size separated from each other in the element isolation region 1. An input gate electrode 3 is disposed on the plurality of divided junction diffusion blocks via a gate insulating film (not shown), and a power supply wiring 4 and an output wiring 5 are formed. Here, the power supply wiring 4 is electrically connected to the source diffusion layers of the first junction diffusion block 2a, the second junction diffusion block 2b and the third junction diffusion block 2c through the contact holes 6a, 6b and 6c, respectively. The contact holes 6a, 6b and 6c constitute the contact hole 6 of the source diffusion layer in the junction diffusion layer region 2. Similarly, the output wiring 5 is electrically connected to the drain diffusion layers of the first junction diffusion block 2a, the second junction diffusion block 2b and the third junction diffusion block 2c through the contact holes 7a, 7b and 7c, respectively. 7b and 7c constitute the contact hole 7 of the drain diffusion layer in the junction diffusion layer region 2.

  Similarly, a junction diffusion layer region 8 in which the S / D diffusion layer of the NMOS transistor is formed is provided, and the ground wiring 9 and the output wiring 5 are connected to the source diffusion layer and drain of the junction diffusion layer region 8 through the contact holes 10 and 11, respectively. It is electrically connected to the diffusion layer. The input gate electrode 3 is also commonly provided as the gate electrode of the NMOS transistor.

  As described above, the junction diffusion layer region 2 where the S / D diffusion layer of the PMOS transistor of the CMOS transistor is formed is divided into blocks of the same size, and the S / D diffusion layer of the NMOS transistor is formed. The junction diffusion layer region 8 is composed of one block. Similarly, the junction diffusion layer region whose size is increased is divided into a plurality of junction diffusion blocks so that the size of the planar shape of the junction diffusion layer region in which the junction region of the elements constituting the semiconductor device is formed does not exceed a predetermined value. Is done.

  In this way, the sheet resistance of the ultra-shallow junction diffusion layer formed by using the above-described low thermal page heat treatment is obtained by dividing the diffusion layer region in which the plane area of the junction region is increased into the junction diffusion block of a predetermined size. Alternatively, the problem that the junction leakage current varies depending on the size is solved, and the design of a semiconductor device composed of a fine CMOS transistor after the 65 nm technology node becomes very simple.

  Next, the main part of the manufacturing process of the MOS transistor will be described more specifically with reference to FIGS. FIG. 2 is a flowchart of the manufacturing process of the main part of the MOS transistor. In the step S21 shown in FIG. 2, the element isolation region 1 is formed on the surface of the semiconductor substrate by shallow trench isolation (STI) by a well-known method. Then, in the step S22, impurity ions and their heat treatment are performed by a known technique to form a well layer on the surface portion of the semiconductor substrate. Then, after forming a gate insulating film on the surface of the element active region defined by the element isolation region 1, in step S23, a gate electrode composed of polycrystalline silicon or a silicide layer is formed.

Next, after forming an offset spacer on the side wall of the gate electrode, halo implantation (for example, As ion implantation angle: 30 degrees, implantation energy: 70 keV, implantation dose amount: 2 × 10 ¹³ / cm ² ) Then, in step S24, extension implantation (for example, B ion implantation angle: 0 degree, implantation energy: 0.5 keV, implantation dose amount: 1 × 10 ¹⁵ / cm ² ) is performed. Do.

Next, in step S25, a sidewall spacer is formed on the side wall of the gate electrode with a silicon oxide film or a silicon nitride film. In step S26, the gate electrode and the sidewall spacer are self-aligned with the S / S. Ion implantation of the D diffusion layer is performed. The dose amount of B ions in this ion implantation is about 5 × 10 ¹⁵ / cm ² .

  In the step S27, impurities introduced into predetermined regions of the first junction diffusion block 2a, the second junction diffusion block 2b, and the third junction diffusion block 2c by the extension implantation and the ion implantation of the S / D diffusion layer. Flash lamp annealing (for example, processing temperature: 450 ° C., processing time: 10 msec), which is a thermal treatment of a low thermal budget, is used to activate the crystal, recover crystal defects generated by the implantation, and form an ultra-shallow junction. Do. Here, SPE (Solid Phase Epitaxy) (for example, processing temperature: 600 ° C., processing time: 2 minutes) may be used in combination. In this way, a p conductivity type source / drain diffusion layer having a junction depth of about 20 nm is formed.

  Here, in flash lamp annealing, a white light xenon (Xe) flash lamp having a light emission wavelength in a wide range from the visible region to the near infrared region may be used. This Xe flash lamp is a light source capable of emitting light for a very short time of several hundred μsec to several tens of msec, and the annealing time is preferably set to 10 msec or less. In this way, for example, impurities can be activated without causing thermal diffusion of ion-implanted impurities such as boron impurities, and a PN junction having a very shallow junction and a low resistance can be formed. become.

  In the formation of the S / D diffusion layer of the MOS transistor described above, even if an ultra-shallow junction is formed by flash lamp annealing, which is a heat treatment with a low thermal paget, as described with reference to FIG. By dividing the layer region into junction diffusion blocks of a predetermined size, all the problems of diffusion layer sheet resistance or junction leakage current variations caused by the ultra-shallow junction described in FIGS. 5 and 6 can be solved. .

  In the above-described embodiment, the division of the diffusion layer of the PMOS transistor has been described. However, the same effect can be obtained by dividing the diffusion layer of the NMOS transistor, which increases the area of the junction region, into a predetermined number.

  In the above embodiment, the case where the activation of the ion implantation layer is performed by the flash lamp annealing has been described, but the same effect can be obtained even when the heat treatment is performed by other low thermal page heat treatment.

  According to the embodiment described above, the ultra-shallow junction of a micro-CMOS transistor having an ultra-shallow junction can be obtained even if an ultra-short-time heat treatment process is performed in order to realize the ultra-shallow junction required in a micro-CMOS transistor after the 65 nm technology node. Variations in sheet resistance and junction leakage current can be suppressed, and the design of a semiconductor device composed of the above-described miniaturized MOS transistors becomes very simple. And the performance improvement of the circuit comprised by the fine CMOS transistor which has an ultra-shallow junction is implement | achieved. Similarly, variations in the diffusion layer resistance for analog elements can be suppressed, and the performance of the analog circuit can be improved.

  Although the preferred embodiments of the present invention have been described above, the above-described embodiments do not limit the present invention. Those skilled in the art can make various modifications and changes in specific embodiments without departing from the technical idea and technical scope of the present invention.

  For example, the present invention can be similarly applied to the case where gallium, indium, arsenic, or phosphorus is used in addition to boron as an effective impurity for forming the impurity diffusion layer, and the amorphous surface of the semiconductor substrate forming the shallow junction is used. The present invention can also be applied to the case of ion-implanting impurities used for crystallization and the case of ion-implanting germanium to form a Si—Ge alloy layer.

  In addition to the case where the semiconductor device is formed on the silicon substrate, the present invention can be similarly applied to the case where the MISFET is formed on a compound semiconductor substrate such as a GaAs substrate or a GaN substrate.

It is a pattern layout diagram of a CMOS inverter according to an embodiment of the present invention. It is a flowchart of the main processes of MOS transistor manufacture. It is a CMOS inverter circuit diagram. It is a pattern layout figure of the CMOS inverter in a prior art. It is a figure which shows the junction size dependence of the sheet resistance of a diffused layer seen in a very shallow junction. It is a figure which shows the junction size dependence of the junction leakage current by a reverse bias seen in a very shallow junction.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Element isolation region 2,8 Junction diffusion layer area | region 2a 1st junction diffusion block 2b 2nd junction diffusion block 2c 3rd junction diffusion block 3 Input gate electrode 4 Power supply wiring 5 Output wiring 6a, 6b, 6c, 7a, 7b, 7c 10, 11 Contact hole 9 Ground wiring

Claims (4)

  A semiconductor device, wherein one PN junction of a semiconductor element formed on a semiconductor substrate is divided into a plurality of diffusion layers.   A semiconductor device, wherein a source diffusion layer or a drain diffusion layer of one insulated gate field effect transistor formed on a semiconductor substrate is divided into a plurality of diffusion layers. Dividing a predetermined region of the semiconductor substrate surface into a plurality of blocks and introducing impurities into each block;
Activating impurities in each block by a method of flash lamp annealing to form an impurity diffusion layer in each block;
Have
A method of manufacturing a semiconductor device, wherein the impurity diffusion layers of all the blocks are one PN junction of a semiconductor element. The method of manufacturing a semiconductor device according to claim 3, wherein a lamp irradiation time in the flash lamp annealing treatment is 10 msec or less.

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