JP2006040422A - Data read-out method, and semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent erroneous read-out by remarkably expanding read-out operation margin. <P>SOLUTION: A signal value corresponding to an almost non-polarization state of a capacitor is generated for individual memory cell (ferroelectric capacitor CF) selected at access, and it is used as a reference signal for sensing. More concretely, a memory signal of the selected memory cell is read out first, then the reference signal corresponding to the almost non-polarization state is generated using the memory cell, and a memory state is determined by comparing the memory signal with the reference signal. The signal value corresponding to the almost non-polarization state is generated equivalently by dividing a generated signal by polarization inversion into almost halves, or generated by making the selected capacitor almost non-polarization and accessing it. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data reading method in a semiconductor memory device such as a ferroelectric memory, and a semiconductor memory device that executes the data reading method.

U.S. Pat. No. 4,873,664 JP 2002-197857 A JP-A-9-121022

In recent years, various semiconductor memories using new memory materials have been proposed. Many of these memories are non-volatile and capable of high-speed operation similar to DRAMs, and future applications are promising as “next-generation memories”.
A typical example is a ferroelectric memory. The cell structure and operation of a ferroelectric memory which is currently mainstream are disclosed in the above-mentioned Patent Document 1.

An example of the realization method is shown in FIG.
In the structure shown in FIG. 6, a memory cell is composed of one access transistor Ta and one ferroelectric capacitor C, and a binary value, that is, one bit is stored according to the polarization direction of the ferroelectric capacitor C.
The word line WL (WL1, WL2,...) Is applied with a voltage according to the address to be accessed by the word line decoder / driver 1. Since a voltage is applied to the gate electrode of the access transistor Ta in each memory cell by a predetermined word line WL, the memory cell is selected by driving the word line WL.
Bit lines BL (BL1, BL2,...) Are arranged in a direction orthogonal to the word lines WL.
The bit lines BL1 and BL2 are a pair of bit lines whose potential is detected by the sense amplifier 3-1. The bit lines BL3 and BL4 are a pair of bit lines whose potential is detected by the sense amplifier 3-2.
In each memory cell, the access transistor Ta is turned on by the word line WL, so that each memory cell is connected to the corresponding bit line BL.
A predetermined voltage is applied to the plate lines PL (PL1, PL2,...) By the plate line decoder / driver 2.
A predetermined plate line PL is connected to one end of the capacitor C of each memory cell.

In such a configuration, for example, data reading from a memory cell by a capacitor C (*) marked with (*) and an access transistor Ta (*) in the figure is taken as an example, and a data reading operation is performed with reference to FIG. Will be explained.
When reading data from the capacitor C (*), the word line WL3 is selected and a pulse is applied to the plate line PL2. Then, since the access transistor Ta (*) of the memory cell is on, the bit line BL1 connected to the counter electrode of the ferroelectric capacitor C (*) is connected to the bit line BL1 from the ferroelectric capacitor C (*). A read signal appears.

The properties of the ferroelectric capacitor will be described with reference to the hysteresis curve of FIG. The horizontal axis represents the voltage applied to the ferroelectric capacitor, and the vertical axis represents the amount of charge induced in the capacitor.
In the case of a paraelectric capacitor, this is a straight line passing through the origin, but the ferroelectric capacitor has hysteresis as shown in the figure.
For example, although the applied voltage is 0 V at the starting point (H0), a negative charge that cancels the polarization component is induced in the electrode (FIG. 7B).
When a voltage is applied in the positive direction from there, in addition to the induced charge due to the paraelectric component, polarization inversion occurs in the middle, and a large charge accompanying it is induced to reach (H1) (FIG. 7 (c)). ).
Therefore, when the voltage application is returned to 0 V, the state changes to (H2) (FIG. 7D).
Further, when a negative voltage is applied this time, polarization inversion occurs again halfway, and a large negative charge is induced (H3) (FIG. 7 (e)). Therefore, when the voltage application is returned to 0 V, the state changes to the original (H0).

In the configuration of FIG. 6, the plate line PL2 and the bit line BL1 are equalized to 0V in the initial state of reading, and the bit line BL1 is in a floating state.
The ferroelectric capacitor C (*) is polarized in different directions according to the stored data. For example, when the data is “0”, the state is (H0) in FIG. 7, and when the data is “1”, the state is (H2). is there.
Here, by applying a pulse of voltage Vcc to the plate line PL2, approximately Vcc is applied to the capacitor C (*). Then, in any of the above cases, the polarization amount shifts to the state of (H1). Accordingly, a signal difference corresponding to the difference in polarization variation from the initial state appears as a read signal difference of “0” and “1” on the bit line BL1 which is the counter electrode of the plate line PL2.

  That is, only when the “1” data is stored and the state is (H0), the ferroelectric capacitor C (*) undergoes polarization inversion, and a signal difference corresponding to the inversion appears on the bit line BL1. Specifically, the potential of the bit line BL1 is higher when reading the “1” data with the polarization inverted than when reading “0” data without the polarization inversion.

Here, for example, an intermediate potential between the read signal for storing “1” data and the read signal for storing “0” data is supplied as a reference signal to the paired bit line BL2, and the read signal and reference corresponding to the stored data are supplied. It is possible to determine whether the read signal is “1” or “0” by comparing the signal with the differential sense amplifier 3-1.
Such polarization reversal of the ferroelectric capacitor can be performed at a high speed in about 1 nanosecond. Accordingly, the ferroelectric memory can achieve an access speed comparable to that of a DRAM while being nonvolatile.
In the above example, a so-called folded bit line configuration has been described. However, as another configuration, an open bit line configuration or a configuration in which a reference voltage is directly supplied to a sense amplifier without using a pair of bit lines is known. . In these cases, the principle of the operation and data determination is the same.

Further, in Patent Documents 2 and 3, a cross-point type ferroelectric memory is proposed as means for further improving the integration degree of the ferroelectric memory.
FIG. 8 shows a circuit example of a cross-point type memory cell.
As shown in the figure, the cell string SS (SS1, SS2,...) Includes a plurality (n) of capacitors C1 to Cn connected to the common node electrode NE (NE1, NE2,...).
Each cell string is connected to a bit line BL (BL1, BL2...) Via an access transistor Ta (Ta1, Ta2...) That is an FET controlled by a word line WL (WL1...). .
Each capacitor constituting the cell string SS stores separate data and is controlled by independent plate lines PL1 to PLn.
In the case of this circuit example, the potential detection of the bit line BL1 is performed by the sense amplifier 3-1, and the potential detection of the bit line BL2 is performed by the sense amplifier 3-2.

As an example, data reading from the capacitor C1 of the cell string SS1 will be described.
In this case, if the pulse is applied to the plate line PL1 while the word line WL1 is selected and the plate lines PL2 to PLn are fixed at 0V, the bit is set according to the polarization direction of the ferroelectric capacitor C1 according to the same principle as described above. Different signals are generated on the line BL1. The sense amplifier 3-1 determines “1” or “0” for the read memory signal by comparing the memory signal generated in this manner with the bit line BL 1 and the separately supplied reference signal.

In the case of this cross-point type cell configuration, since the plurality of capacitors C1 to Cn share one access transistor Ta, the number of elements per bit is effectively reduced, which is effective for cost reduction.
Needless to say, this cross-point type also has various configuration variations such as folded bit lines and open bit lines.

Further, Patent Document 2 proposes a memory configuration that has a mechanism for amplifying a read signal by developing the cross point type. An example is shown in FIG.
The cell string SS is composed of a plurality (n) of ferroelectric capacitors C1 to Cn connected to the common node NE, and each capacitor C1 to Cn stores separate data, and has independent plate lines PL1 to PL1. Controlled by PLn.

Further, a read access transistor Tr, a write access transistor Tw, and a sense transistor Ts, each of which is formed of an FET, are provided.
The sense transistor Ts is a depletion type N-channel MOS-FET, and its gate is connected to the common node NE. Further, one of the sources / drains is connected to, for example, the ground potential, and the other is connected to the bit line BL via the read access transistor Tr.
Read access transistor Tr has one of its source / drain connected to sense transistor Ts and the other connected to bit line BL. The gate is connected to read word line WLr, and therefore read access transistor Tr is on / off controlled by read word line WLr.
Write access transistor Tw has one of its source / drain connected to common node NE and the other connected to bit line BL. The gate is connected to write word line WLw, and therefore write access transistor Tw is on / off controlled by write word line WLw.

For example, when reading data, for example, when reading data from the capacitor C1, in this case, the read word line WLr is selected, and a pulse is applied to the plate line PL1 while the plate lines PL2 to PLn are fixed at 0V. To do.
As a result, a signal appears at the common node NE in accordance with the polarization direction of the ferroelectric capacitor C1, but at this time, the write word line WLw is closed (the write access transistor Tw is off), and the common node NE is the bit line. Disconnected from BL.
That is, the charge from the cell capacitor C1 does not directly drive the bit line BL, but drives only the gate electrode of the sense transistor Ts. For example, the sense transistor Ts, which is a depletion type NMOS, drives the bit line BL according to the voltage applied to its gate. That is, in this case, an amplified signal obtained by converting a signal appearing on the common node NE appears on the bit line BL.

  On the other hand, at the time of data writing, write word line WLw is selected and write access transistor Tw is turned on. The read access transistor Tr is turned off. Then, since the common node NE is connected to the bit line BL, the bit line BL and the plate line are transferred to the selected capacitor C (x) by driving the bit line BL and the plate line to a required state, respectively. An appropriate voltage as a potential difference of PL (x) is applied, and data is written.

  Such an amplification type memory can effectively take out a signal from a minute ferroelectric capacitor by its signal amplification effect, and is extremely advantageous for high integration. Further, the sense transistor Ts or the like as an additional circuit for amplification can be formed in an empty silicon region below the cell string SS, so that the cell area does not increase.

  As described above, although the ferroelectric memory is non-volatile, it has a potential to realize a high-speed rewrite operation and to realize a large capacity that surpasses DRAM. In particular, the cross-point type having a signal amplification function as shown in FIG. 9 is advantageous for miniaturization because even a minute capacitor can be amplified to a large signal.

However, when the ferroelectric capacitor is miniaturized, there is a problem that the error rate increases due to signal variation.
Ferroelectric films have considerable variations in crystal orientation and polarization due to their crystal imperfections. Such a variation is not a problem that is averaged with a large capacitor, but becomes more prominent with miniaturization. For example, when the capacitor area and the load capacitance are both (1/4), the average value of the signal is scaled as it is and does not change, but the statistical variation is doubled.
Such a problem cannot be solved simply by amplifying a signal because variations are similarly amplified.
Such variations are largely due to variations in the ferroelectric component, and are particularly noticeable on the high level side (here, corresponding to “1” data).

  The influence of such signal variations on data determination is shown in the conceptual diagram of FIG. In the figure, the signal levels of the respective memory cells are shown as cell signals CS1, CS2 and CS3, but both “0” and “1” vary as indicated by ● and ○. In addition, these signals change as indicated by “x” and “Δ” in the direction in which “0” data and “1” data approach each other due to data retention degradation, disturbance degradation, and the like. For example, in the case of the cell signal CS1, the state (α) changes over time from the state (α). That is, the “0” signal rises, the “1” signal falls, and the signal difference becomes smaller.

Here, in the determination of the data stored in the memory cell, one reference signal corresponding to an intermediate level between “0” and “1” is used for determining a plurality of capacitors. As one technique, for example, one dummy capacitor for generating a reference potential is provided on a bit line, and determination of all memory cells on adjacent bit lines is performed using the dummy capacitor.
However, looking at the reference signal rf in FIG. 10A, an error occurs in the cell signal CS2, even if the level is appropriate for the determination of the cell signal CS1, for example. Further, the operation margin is further deteriorated due to the deterioration of the signal over time as described above.

In order to solve such a problem, a method called self-reference has been proposed in which a reference signal is generated in the accessed capacitor itself. This is done in the following procedure.
1. First, the first signal from the initial data is acquired by the first reading, and then data corresponding to the low level signal is once written in the cell.
2. A second read is performed to obtain a second signal.
3. The second signal is added with a certain offset signal as a reference signal and compared with the first signal to determine initial data.

In such a determination method, as shown in FIG. 10B, for each memory cell, a signal obtained by adding a certain offset OF from the low level signal (corresponding to “0” data here) is referred to. It is given as signals rf1, rf2, and rf3. Therefore, the variation on the “0” side is always canceled out.
However, the most problematic variation on the “1” side is not offset. Moreover, since the value of the offset OF is constant for any memory cell, an optimal signal cannot be given to each memory cell.
Therefore, for example, as shown in the figure, even if the reference signal rf1 for the cell signal CS1 is appropriate, the reference signal rf2 for the cell signal CS2 is too close to “1”, while the reference signal rf3 for the cell signal CS3 is on the “0” side. It is a biased level.

Since the sense amplifier that performs read data determination senses and determines the difference between each cell signal and the reference signal, if there is an imbalance as described above, a sufficient difference can be obtained in a specific state of a specific cell. Therefore, the sensitivity of determination is reduced.
Further, when there is a deterioration with time such as data retention, the “0” signal written as a reference is fresh and becomes smaller than the retained “0” signal. Therefore, an offset that is too small causes an error in reading “0”, and an offset that is too large causes an error in reading “1”. Therefore, setting an appropriate offset OF value itself becomes very difficult.

  In view of such a problem, an object of the present invention is to dramatically increase an operation margin in reading in a semiconductor memory device using a ferroelectric memory and prevent erroneous reading.

According to the data reading method of the present invention, in a semiconductor memory device having a memory cell that stores binary data according to the polarization direction of the ferroelectric capacitor, the memory according to the polarization direction of the ferroelectric capacitor read from the memory cell is stored. With respect to the signal, a signal value corresponding to the substantially non-polarized state of the ferroelectric capacitor is used as a reference signal to determine the storage state of the memory cell.
In particular, after reading the storage signal from the selected memory cell, generating the reference signal corresponding to a substantially non-polarized state using the selected memory cell, and comparing the storage signal with the reference signal To determine the storage state of the selected memory cell.
The reference signal corresponding to the substantially non-polarized state is generated by halving the generated signal accompanying polarization inversion.
Alternatively, the reference signal corresponding to the substantially non-polarized state is generated by reading a signal from the memory cell in a state where the ferroelectric capacitor of the selected memory cell is substantially non-polarized.

The semiconductor memory device according to the present invention includes a memory cell that stores binary data according to a polarization direction of a ferroelectric capacitor, and a read pulse applied to the selected memory cell, so that the ferroelectric of the memory cell Memory cell reading means for generating a memory signal corresponding to the polarization direction of the capacitor and generating a reference signal corresponding to a substantially non-polarized state of the ferroelectric capacitor using the selected memory cell, and the memory cell reading means Determination means for determining the storage state of the selected memory cell by comparing the storage signal read out by the reference signal with the reference signal.
The memory cell reading means generates the reference signal corresponding to the substantially non-polarized state by making the generated signal accompanying the polarization inversion approximately one half.
Alternatively, the memory cell reading means reads the reference signal corresponding to the substantially non-polarized state from the memory cell in a state where the ferroelectric capacitor of the selected memory cell is substantially non-polarized. Generate by.

That is, according to the present invention, in the so-called ferroelectric memory as described above, a signal value corresponding to a substantially non-polarized state of a capacitor is generated for each memory cell selected at the time of access, and this is referred to at the time of sensing. It is used as a signal.
By using a signal corresponding to the non-polarized state of the selected memory cell as a reference signal, correct data can be read out even if a slight polarization deviation remains in the accessed memory cell.

The present invention generates a signal value corresponding to a substantially non-polarized state of a capacitor for each memory cell selected at the time of access and uses it as a reference signal at the time of sensing. The selected memory cell itself Since a signal corresponding to the non-polarized state is used as a reference signal, data can be correctly read out even if a slight polarization deviation remains in the accessed cell. Therefore, it is possible to perform sensing that is hardly affected by signal variations between memory cells and that is extremely resistant to deterioration over time. In addition, the operation margin in reading of the semiconductor memory device can be dramatically increased, and erroneous reading can be prevented.
Also, such a reference signal is equivalently generated from the ferroelectric capacitor of the memory cell that is actually accessed, or an unpolarized signal itself is actually generated. Therefore, there is almost no need to artificially generate a reference potential or offset from a system other than the capacitor of the accessed memory cell, so that the influence of characteristic fluctuations due to manufacturing variations can be minimized.
Therefore, it is possible to correctly sense a very small amount of signal from a very fine capacitor, contributing to the miniaturization of the memory cell and realizing a large capacity and low cost ferroelectric memory.

Embodiments of the present invention will be described below.
FIG. 1 shows the configuration of the semiconductor memory device according to the first embodiment.
In the structure shown in FIG. 1, a memory cell is composed of one access transistor Ta and one ferroelectric capacitor CF, and stores a binary value, that is, one bit according to the polarization direction of the ferroelectric capacitor CF. A folded bit line configuration is adopted.

The word line WL (WL1, WL2,...) Is applied with a voltage according to the address to be accessed by the word line decoder / driver 1. Since a voltage is applied to the gate electrode of the access transistor Ta in each memory cell by a predetermined word line WL, the memory cell is selected by driving the word line WL.
Bit lines BL (BL1, BL2,...) Are arranged in a direction orthogonal to the word lines WL. The paired bit lines BL1 and BL2 are connected to the level converter 7 via connection transistors T4 and T5, respectively.

In each memory cell, the access transistor Tr is turned on by the word line WL, so that each memory cell is connected to the corresponding bit line BL.
A predetermined voltage is applied by the plate line decoder / driver 2 to the plate lines PL (PL1, PL2, PL3... Not shown).
A predetermined plate line PL is connected to one end of the capacitor CF of each memory cell.

Control lines SL1, SL2, SL3, SL4, and SL5 are provided, and each control line SL is driven at a predetermined timing.
For example, the control line SL1 is connected to the gate of the transistor Tp1 formed of a P-channel MOSFET. One end of the source / drain of the transistor Tp1 is connected to the fixed voltage Vcc, and the other end is connected to the bit line BL1, and when the transistor Tp1 is turned on by the control line SL1, the voltage Vcc is applied to the bit line BL1.
For example, the control line SL2 is connected to the gate of the transistor Tp2 formed of a P-channel MOSFET. One end of the source / drain of the transistor Tp2 is connected to the fixed voltage Vcc, and the other end is connected to the bit line BL2. When the transistor Tp2 is turned on by the control line SL2, the voltage Vcc is applied to the bit line BL2.
For example, the control line SL3 is connected to the gates of transistors Tp3a and Tp3b formed of N-channel MOSFETs. One ends of the sources / drains of the transistors Tp3a and Tp3b are connected to the ground node. The other end of the transistor Tp3a is connected to the bit line BL1, and the other end of the transistor Tp3b is connected to the bit line BL2. Since the transistors Tp3a and Tp3b are turned on by the control line SL3, the bit lines BL1 and BL2 are grounded.

For example, the control line SL4 is connected to the gate of the connection transistor T4 formed of an N-channel MOSFET. The source / drain of the connection transistor T4 is connected to the bit line BL1 and a node on the level converter 7 side, and the connection transistor T4 is turned on by the control line SL4, so that the potential of the bit line BL1 is changed to the level converter 7. Is input.
A control line SL5 is connected to the gate of the connection transistor T5 formed of an N-channel MOSFET. The source / drain of the connection transistor T5 is connected to the node on the bit line BL2 and the level converter 7 side, and the connection transistor T5 is turned on by the control line SL5, so that the potential of the bit line BL2 is changed to the level converter 7. Is input.

The global bit line GBL from the level converter 7 is connected to a coupling capacitor Ccp, and the other end side of the coupling capacitor Ccp is a determination circuit unit in which inverters 5 and 6, a switch 4, and transistors T 1, T 2 and T 3 are arranged. It is said that.
The storage circuit read from the ferroelectric capacitor CF is determined to be “0” or “1” by this determination circuit unit, and is output to the data bus DB.

In the configuration of FIG. 1, for example, a case where data is read by selecting the capacitor CF (*) will be described.
First, the control line SL3 for equalization is turned on to fix the bit line BL1 to the ground potential, and further the control line SL3 is turned off to place the bit line BL1 in a floating state. Thereafter, a pulse is applied to the plate line PL1 to generate a signal potential on the bit line BL1.
Conventionally, the data value is determined by comparing the potential appearing on the bit line BL1 with an externally generated reference potential. However, in this example, the signal generated on the bit line BL1 is stored by an appropriate means, and a signal corresponding to the non-polarized state is generated from the same selected capacitor CF (*), which is used as a reference potential. Compare Specifically, it is as follows.

First, by turning on the gate of the connection transistor T4 by the control line SL4, the signal potential generated in the bit line BL1 is transmitted to the global bit line GBL via the level converter 7, and there is a read signal (corresponding to the polarization direction). A memory signal VS1 is generated.
Here, when the transistor T1 is turned on by the control line S1, the input / output of the inverter 6 is short-circuited, and the potential of the node N1 is fixed to the threshold value VT.
Further, when the transistor T1 is turned off and the node N1 is brought into a floating state, the storage signal VS1 transmitted to the global bit line GBL is stored as the charge of the node N1 via the coupling capacitor Ccp.

That is, in this system, when the potential of the global bit line GBL becomes smaller than the storage signal VS1, the potential of the node N1 also becomes smaller than the threshold value VT, so that the output (N2) of the inverter 6 becomes high. Conversely, when the potential of the global bit line GBL becomes higher than the storage signal VS1, the potential of the node N1 also becomes higher than the threshold value VT, and therefore the output (N2) of the inverter 6 becomes low.
Here, a read signal corresponding to the non-polarized state is generated on the bit line BL1 by using the selected capacitor CF (*) (the method will be described later). This signal is intermediate between the “1” signal and the “0” signal, and is transmitted from the connection transistor T4 to the global bit line GBL via the level converter 7, thereby generating the reference signal VREF.
As a result, the comparison determination between the storage signal VS1 stored as the charge in the node N1 and the reference signal VREF is performed. That is, if the previously read storage signal is high, since VREF <VS1, the output (N2) of the inverter 6 becomes high. Similarly, if the previously read storage signal is low, since VREF> VS1, the output (N2) of the inverter 6 becomes low. If the switch 4 is turned on to activate the latch, the data is determined.
The determined data is output to the data bus DB when the transistors T2 and T3 are turned on by the control line S2, and transmitted to the bit line BL1 through a path (not shown), and rewritten to the capacitor CF (*). The

  In this circuit configuration, the level converter 7 and the bit line pair BL1 and BL2 may constitute a memory unit, and a plurality of memory units may be connected to the global bit line GBL. In that case, a selection transistor is provided between the level converter 7 and the global bit line GBL, and only a desired memory unit is selected and connected to the global bit line GBL. If such a hierarchical structure is adopted, the coupling capacitor Ccp, the latch circuit (determination circuit unit), etc. can be shared by a plurality of memory units, and the circuit scale can be reduced.

  By the way, as a specific method for generating a signal corresponding to the non-polarized state from the capacitor CF, there are a method for generating an equivalent signal and a method for actually accessing the capacitor CF in the non-polarized state.

First, a method for generating an equivalent signal will be described.
An equivalent non-polarized signal can be generated by applying a pulse to the plate line PL, reading the signal after returning it to the original, and dividing the high level signal into approximately two parts. is there.
FIG. 2 shows the state transition on the hysteresis curve and the behavior of the corresponding signal node when a pulse is applied to the plate line PL and returned to its original state in the actual memory configuration.
As shown in FIG. 2B, the ferroelectric capacitor CF is connected to the load capacitor CB by the bit line BL, and the potential applied to the plate line PL is distributed to the ferroelectric capacitor CF and the load capacitor CB. Is done. When attention is paid to the node NB where the signal appears, the charge induced on the node NB side in the ferroelectric capacitor CF is the inversion charge of the induced charge toward the plate line PL shown by the hysteresis curve in FIG. It is.

In the initial state, the potential applied to the plate line PL is 0, and the node NB is also equalized to the ground state. At that time, if the state of the capacitor CF is (H0) in FIG. 2A, a positive charge which is an inversion of the negative charge induced toward the plate line PL is induced at the node NB. Further, if the state of the capacitor CF is (H2), a negative charge that is an inverted charge of the positive charge induced toward the plate line PL is induced at the node NB.
After that, since the node NB is in a floating state, the charge amount is stored during the read operation. As the pulse is applied to the plate line PL, the stored charge is redistributed between the capacitors CF and CB to become a residual signal ΔV.

Assume that a positive pulse is applied to the plate line PL and the state returns to the 0 V state again. At that time, if the starting point is (H2), the polarization state does not change. Therefore, the capacitor CF returns to the (H2) state, and the remaining signal is also zero.
On the other hand, when the starting point is (H0), the ferroelectric capacitor CF reverses its polarization and tries to return to the (H2) side via (H1). At this time, since a residual signal corresponding to the state change is generated and the potential of the node NB rises, a negative bias (−ΔV) is applied to the capacitor CF, and the state reaches (H4).
Here, when a straight line L1 having a slope of the negative value of the load capacity value of the capacitive load CB is subtracted from (H0), (H4) is located at the intersection of the straight line L1 and the hysteresis curve.
That is, as the state of the ferroelectric capacitor CF changes from (H0) to (H4), ΔV is applied to the capacitive load CB, and a charge corresponding to the difference between (H4) and (H0) is induced. The On the other hand, the charge induced on the node NB side of the capacitor CF is an inverted charge of (H4). That is, the sum of the charges induced in the load capacitor CB is equal to the initial charge, that is, the inversion charge of (H0).

Similarly, in the initial stage, when the capacitor CF is in a non-polarized state, the state transition and the remaining signal upon application of the pulse are as follows.
In the initial state, the node NB is 0 V, and the unpolarized state corresponds to the origin (H5). When a positive pulse is applied to the plate line PL, the state changes from (H5) to (H1), and when the pulse is returned to its original state, it passes through (H2) and goes to (H6). (H6) is located at the intersection with the hysteresis curve when a straight line L2 having a slope of a negative value of the load capacity value of the capacitive load CB is subtracted from (H5).

  Here, since the ferroelectric capacitor CF ideally has no polarization change below the coercive electric field, the hysteresis curve can be approximated as a straight line when the applied voltage is around 0V. That is, the transition from (H2) to (H4) can be regarded as a substantially straight line. In this case, the potential of (H6) is approximately (−1/2) ΔV. Therefore, the remaining signal to the node NB is equivalent to (1/2) ΔV, that is, a signal obtained by dividing the remaining signal on the high level side into ½.

An equivalent procedure for creating a non-polarized signal according to the above method is shown on the circuit of FIG.
In a state where the word line WL2 of the selected memory cell (capacitor CF (*)) is ON, first, the gate of the transistor Tp1 (control line SL1) by the pull-up PMOS is turned ON to 0V, and the bit line BL1 is set to Vcc. To charge.
Further, if the plate line PL1 is set to 0V, a high level signal is written to the selection capacitor CF (*).
Next, when the transistor Tp1 is turned off and the gates (control lines SL3) of the transistors Tp3a and Tp3b by the pull-down NMOS are turned on, the bit lines BL1 and BL2 are equalized to 0V.
Further, the transistors Tp3a and Tp3b are turned off to make the bit lines BL1 and BL2 floating, and then a read pulse is applied to the plate line PL1.
Thereafter, even if the plate line PL1 is returned to 0V, the residual signal ΔV corresponding to the high level remains on the bit line BL1. On the other hand, the paired bit line BL2 remains at 0V.
Here, when the gates (control lines SL4 and SL5) of the connection transistors T4 and T5 corresponding to the respective bit lines BL1 and BL2 are turned on, the residual signal generated on the bit line BL1 is divided between the bit lines BL2 and (1/2) ΔV is input to the level converter 7. The reference signal VREF generated in this way is substantially equivalent to a read signal generated when the capacitor CF (*) is in a non-polarized state.

FIG. 3 shows a conceptual diagram of signal determination by such a method in the same format as the conventional example of FIG.
As described above, when the remaining signal is read in a state where the pulse returns from high to low, a low level signal without polarization inversion returns to the state before the pulse application if it is fresh. On the other hand, on the high level side where polarization inversion is performed, a signal corresponding to the inversion is generated.
The remaining signal states of the different memory cells at that time are shown as cell signals CS11, CS12, and CS13 in FIG.
Similar to FIG. 10 described above, the signal levels of the memory cells shown as the cell signals CS11, CS12, and CS13 vary as shown by ● and ○. These signals change as indicated by “x” and “Δ” in the direction in which “0” data and “1” data approach each other due to data retention degradation, disturbance degradation, and the like. Deterioration with time due to standing at high temperature during data retention, which is a particular problem in the nonvolatile memory, finally reaches a non-polarized state.

Here, reference levels obtained by performing high-level writing again and converting it to approximately ½ are shown as broken lines VREF11, VREF12, and VREF13 in FIG.
The reference level generated in this way is substantially equal to the signal from the unpolarized state in each capacitor, as described above. Therefore, the optimum reference potential is set for each capacitor.

Next, a method for generating a signal corresponding to the non-polarized state from the capacitor CF by actually accessing the capacitor CF in the non-polarized state will be described.
For example, in FIG. 1, the pass line Tp3a is turned on and the bit line BL1 is equalized to 0V, the word line WL2 is opened, and the bit line side of the selection capacitor CF (*) is fixed to 0V.
Here, the non-polarized state can be generated by alternately applying positive and negative pulses to the plate line PL1 while attenuating them.

This is shown in the hysteresis curve of FIG.
By alternately applying positive and negative pulses to the plate line PL1 while attenuating as shown in FIG. 4B, the state of the ferroelectric capacitor CF (*) is changed to (HP0) in FIG. ) (HP1) (HP2) (HP3)... In order and converge to the non-polarized state at the origin.
When the non-polarized state is generated in this way, the signal is read from the capacitor CF (*) as usual, and this is used as the reference signal VREF, and the data value of the storage signal VS1 read before that is determined. Just do it.

The sensing method as described above can be applied to other memories using ferroelectric capacitors for data storage.
FIG. 5 shows an example of a semiconductor memory device having a cross-point type ferroelectric memory configuration as a second embodiment. In this example, in order to generate an unpolarized signal equivalently, a mechanism for distributing the signal between adjacent units is incorporated.

FIG. 5 shows a certain memory unit and a portion of the memory unit adjacent thereto. The cell string SS1 in one memory unit (the same applies to the cell strings SS2... In other memory units) includes a plurality (n) of capacitors CF1 to CFn connected to the common node NE1.
Each capacitor CF constituting the cell string SS1 stores separate data, and is controlled by independent plate lines PL1 to PLn.

Further, a read access transistor Tr, a write access transistor Tw, and a sense transistor Ts, each of which is formed of an FET, are provided.
The sense transistor Ts is a depletion type N-channel MOS-FET, and its gate is connected to the common node NE1. Further, one of the sources / drains is connected to, for example, the ground potential, and the other is connected to the bit line BL via the read access transistor Tr.
Read access transistor Tr has one of its source / drain connected to sense transistor Ts and the other connected to bit line BL. The gate is connected to read word line WLr, and therefore read access transistor Tr is on / off controlled by read word line WLr.
In the write access transistor Tw, one of the source / drain is connected to the common node NE1, and the other is connected to the bit line BL. The gate is connected to write word line WLw, and therefore write access transistor Tw is on / off controlled by write word line WLw.

Further, in the memory unit, a reset transistor Trst and a signal distribution transistor Td are provided.
In the reset transistor Trst, one of the source / drain is connected to the common node NE1, and the other is grounded. The gate is connected to the reset control line SLrst, and therefore the reset transistor Trst is on / off controlled by the reset control line SLrst.
This resetting transistor Trst makes it possible to ground the common node NE1, which is a node that receives a signal from the capacitor CF, without going through the bit line BL.

In the signal distribution transistor Td, one of the source / drain is connected to the common node NE1, and the other is connected to the common node NE2 of the adjacent memory unit. The gate is connected to the signal distribution control line SLd. Therefore, the signal distribution transistor Td is controlled to be turned on / off by the signal distribution control line SLd.
This signal distribution transistor Td makes it possible to short-circuit the common node NE1 with the common node NE2 of the adjacent memory unit.

Note that all these circuits can be arranged in the lower layer of the cell string SS1, so that no extra occupied area is required.
A plurality of memory units having such a configuration are connected to the bit line BL, and the bit line BL is further connected to a coupling capacitor Ccp.
A PMOS transistor T4 is connected to the bit line BL.
The other end side of the coupling capacitor Ccp is a determination circuit unit in which inverters 5 and 6, a switch 4, and transistors T 1, T 2, and T 3 are arranged as in the example of FIG.
The storage circuit read from the ferroelectric capacitor CF is determined to be “0” or “1” by this determination circuit unit, and is output to the data bus DB.

In the configuration of FIG. 5, a case where data is read from the capacitor CF1 is taken as an example.
The sense transistor Ts in the memory unit receives the potential of the common node NE1 carrying the read signal from the cell capacitor CF1 at the gate, and drives the bit line BL toward the ground potential.
On the other hand, the PMOS transistor T4 connected to the bit line BL operates as a pull-up resistor, and the potential of the bit line BL is fixed where both are balanced. That is, the sense transistor Ts and the PMOS transistor T4 convert the potential of the node NE1 into a bit line potential.
After the signal (memory signal) read in this way is converted into the potential of the bit line BL, when the transistor T1 is turned on, the input / output of the inverter 6 is short-circuited, and the potential of the node N1 is fixed to the threshold value VT.
Further, by turning off the transistor T1 and bringing the node N1 into a floating state, the storage signal VS1 (bit line potential) appearing on the bit line BL is stored as the charge of the node N1 via the coupling capacitor Ccp. Become.
That is, in this system, when the bit line potential becomes smaller than the storage signal VS1, the potential of the node N1 becomes smaller than the threshold value VT, and therefore the output (N2) of the inverter 6 becomes high.
Conversely, when the bit line potential becomes higher than the storage signal VS1, the potential of the node N1 also becomes higher than the threshold value VT, and therefore the output (N2) of the inverter 6 becomes low.
Here, a read signal corresponding to the non-polarized state is generated at the common node NE1 using the selected capacitor CF1. This signal is in the middle between the “1” signal and the “0” signal, and the sense transistor Ts is driven, and a conversion signal appears on the bit line BL. That is, the reference signal VREF.
As a result, the comparison determination between the storage signal VS1 stored as the charge in the node N1 and the reference signal VREF is performed.
That is, if the previously read storage signal VS1 is high, the output (N2) of the inverter 6 becomes high because VREF <VS1. Similarly, if the previously read storage signal VS1 is low, since VREF> VS1, the output (N2) of the inverter 6 becomes low. If the switch 4 is turned on to activate the latch, the data is determined.
The determined data is output to the data bus DB when the transistors T2 and T3 are turned on, and is transmitted to the bit line BL via a path (not shown), and further, the write transistor Tw of the selection unit SS1 is transmitted. Via the common node NE1. According to this value, data is rewritten in the capacitor CFC1.

  In the configuration of FIG. 5 as well, the generation method of the signal corresponding to the non-polarized state (reference signal VREF) generates an equivalent non-polarized signal as in the case of the first embodiment described above. Alternatively, a non-polarized state may be actually generated in the memory cell, and this may be read and used as a reference potential.

In order to generate an equivalent non-polarized signal, for example, a pulse is applied to the plate line PL, a sensing method is used to read the signal after returning it to the original, and a high level signal is generated by substantially dividing it into two. It is possible.
Hereinafter, an equivalent generation procedure of a non-polarized signal in the configuration of FIG. 5 will be specifically described.
First, after all the common node NE1 and the plate lines PL1 to PLn of the selected memory unit are grounded, all the transistors Tw, Tr, Trst, and Td are turned off, and the common node NE1 is brought into a floating state.
Next, the remaining plate lines PL2 to PLn are driven to Vcc while the plate line PL1 connected to the selected cell capacitor CF1 is kept at 0V. As a result, the common node NE1 rises to near Vcc in response to coupling from each non-selected capacitor (CF2 to CFn). Therefore, high level data is selectively written into the selection capacitor CF1.
In such a writing method, the coupling ratio increases as the number of unselected capacitors connected to the common node NE1 increases, and a voltage closer to Vcc can be applied to the selected capacitor CF1. Therefore, the signal distribution transistor Td is turned on, the common node NE1 is connected to the common node NE2 of the adjacent unit, and the same writing may be performed using the non-selected capacitor of the adjacent unit.
By using the method as described above, it is possible to easily write high-level data to a capacitor group connected to a desired plate line without driving a heavily loaded bit line BL.

Next, the common node NE1 and the plate lines PL1 to PLn of the selected unit are all grounded again, all the transistors Tw, Tr, Trst, and Td are turned off, and the common node NE1 is brought into a floating state.
Here, a read pulse is applied to the plate line PL1. Thereafter, even if the plate line PL1 is returned to 0V, the residual signal ΔV corresponding to the high level remains at the common node NE1.
On the other hand, the common node NE2 and the plate line of the adjacent unit that is paired are also grounded, and the node NE2 is left floating.
Here, when the signal distribution transistor Td is turned on, the residual signal ΔV generated at the common node NE1 is divided between the common node NE2 and becomes (½) ΔV.
Further, the sense transistor Ts is driven by this signal potential, and the conversion signal, that is, the reference signal VREF appears on the bit line BL. The reference signal VREF generated in this way is substantially equivalent to a read signal generated when the capacitor CF1 is in a non-polarized state.

Further, in order to actually generate a non-polarized state in the memory cell and read it as a reference potential, the following may be performed.
For example, in FIG. 5, the reset transistor Trst is turned on to ground the common node NE1 to 0V.
Here, as described with reference to FIG. 4, positive and negative pulses are alternately applied to the plate line PL1 while being attenuated. As a result, a non-polarized state can be generated in the selection capacitor CF1.
When the non-polarized state is generated, signal reading from the capacitor CF1 is performed as usual, which is used as the reference signal VREF, and the data value of the storage signal VS1 read before that is determined.

As described above, in the first and second embodiments, a signal value corresponding to a substantially non-polarized state of a capacitor is generated for each memory cell (ferroelectric capacitor) selected at the time of access. It is used as a reference signal for sensing.
More specifically, first, a memory signal of a selected memory cell is read, and then a reference signal corresponding to a substantially non-polarized state is generated using the memory cell, and the memory signal is compared with the reference signal. The memory state is determined.
The signal value corresponding to the substantially non-polarized state is generated equivalently by making the generated signal accompanying the polarization inversion approximately one half, or the selected capacitor is made substantially non-polarized and accessed. Generate by.
Thus, by using a signal corresponding to the non-polarized state of the selected capacitor itself as a reference signal, data can be read correctly as long as a slight polarization deviation remains in the accessed capacitor. Therefore, it is possible to perform sensing that is hardly affected by signal variations between cells and that is extremely resistant to deterioration over time. Therefore, it is possible to increase the margin during reading and prevent erroneous reading.
In addition, the reference signal in this case is generated equivalently from the cell capacitor that is actually accessed, or the non-polarized signal itself is actually generated, so that the reference potential is artificially generated from a system other than the accessed cell capacitor. Since there is almost no need to generate an offset, it is possible to minimize the influence of characteristic fluctuations due to manufacturing variations and the like.
Therefore, it is possible to correctly sense a very small amount of signal from a very fine capacitor, contributing to the miniaturization of the memory cell and realizing a large capacity and low cost ferroelectric memory.

  The present invention is not limited to the configuration and operation of the above embodiment. For example, the second embodiment is an example based on a configuration called an amplification type cross-point memory, but it goes without saying that the present invention can be applied to a cross-point memory that is not an amplification type.

It is explanatory drawing of the structure of the 1st Embodiment of this invention. It is explanatory drawing of the behavior of the ferroelectric capacitor of embodiment. It is explanatory drawing of the reference signal by embodiment. It is explanatory drawing of the production | generation method of the non-polarization state of the capacitor of embodiment. It is explanatory drawing of the structure of the 2nd Embodiment of this invention. It is explanatory drawing of the structure of the semiconductor memory by a ferroelectric capacitor. It is explanatory drawing of the behavior of a ferroelectric capacitor. It is explanatory drawing of a cross point type ferroelectric memory. It is explanatory drawing of an amplification type cross point type ferroelectric memory. It is explanatory drawing of the signal variation of a ferroelectric capacitor.

Explanation of symbols

  1 Word line decoder / driver, 2 plate line decoder / driver, 4 switches, 5, 6 inverter, 7 level converter, WL word line, BL bit line, GBL global bit line, PL plate line, CF capacitor, Ccp coupling capacitor

Claims (7)

In a semiconductor memory device having a memory cell for storing binary data according to the polarization direction of a ferroelectric capacitor,
A memory signal read from the memory cell according to the polarization direction of the ferroelectric capacitor is used as a reference signal using a signal value corresponding to a substantially non-polarized state of the ferroelectric capacitor as a reference signal. A data reading method characterized by determining a storage state of the data.   After reading the storage signal from the selected memory cell, the reference signal corresponding to a substantially non-polarized state is generated using the selected memory cell, and the selection is performed by comparing the storage signal with the reference signal. 2. The data reading method according to claim 1, wherein the storage state of the memory cell is determined.   2. The data reading method according to claim 1, wherein the reference signal corresponding to the substantially non-polarized state is generated by halving a generated signal accompanying polarization inversion.   The reference signal corresponding to the substantially non-polarized state is generated by reading a signal from the memory cell in a state where the ferroelectric capacitor of the selected memory cell is substantially non-polarized. The data reading method according to claim 1. A memory cell for storing binary data according to the polarization direction of the ferroelectric capacitor;
A read pulse is applied to the selected memory cell to generate a memory signal corresponding to the polarization direction of the ferroelectric capacitor of the memory cell, and the ferroelectric capacitor is used using the selected memory cell. Memory cell reading means for generating a reference signal corresponding to the substantially non-polarized state of
Determining means for determining the storage state of the selected memory cell by comparing the reference signal with the storage signal read by the memory cell reading means;
A semiconductor memory device comprising:   6. The semiconductor memory according to claim 5, wherein said memory cell reading means generates said reference signal corresponding to said substantially non-polarized state by halving a generated signal accompanying polarization inversion. apparatus. The memory cell reading means reads the signal from the memory cell in a state in which the ferroelectric capacitor of the selected memory cell is in a substantially non-polarized state, thereby obtaining the reference signal corresponding to the substantially non-polarized state. The semiconductor memory device according to claim 5, wherein the semiconductor memory device is generated.

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