JP2006039582A - Method and device for error diffusion processing of display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an error diffusion processing method for a display device which can reduce picture quality disturbance such as periodic pattern noise appearing when error diffusion processing is performed in spite of higher luminance of a panel. <P>SOLUTION: A readout start position of a line memory 36 holding error data to be diffused to a plurality of pixels disposed one line behind a pixel of interest is shifted to make the relative diffusion place of at least one signal among R, G, and B signals to the pixel of interest of error data of a line, which is at least one line behind, be different from other signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an error diffusion processing method and an error diffusion processing apparatus used in a display device, and more particularly, to a plasma display panel display device (PDP), a field emission display device (FED), a digital micromirror device (DMD), and electroluminescence. In a display device that expresses digitally limited intermediate gradations, such as a display (EL), a display device that can reduce image quality interference caused by multi-gradation processing by error diffusion processing. The present invention relates to an error diffusion processing method and an error diffusion processing apparatus.

  Among display devices that display video signals, for example, a PDP that displays gradation by dividing one field into a plurality of subfields, an FED that displays gradation by pulse width modulation (PWM), and a matrix type such as DMD In a display device, an image can be expressed only with a digitally limited number of gradations depending on the driving method.

  Normally, in television broadcasting and the like where the receiver is assumed to be a cathode ray tube (CRT), a gamma characteristic is given in advance on the transmitter side, and a linear scale is combined with the inverse gamma characteristic of the CRT on the receiver side. It is designed to have a tonal characteristic. However, in the display device as described above that displays an image with a digitally limited number of gradations, unlike the CRT, the display device itself has linear gradation characteristics. Therefore, in order to display an image with the same gradation characteristics as a display device using CRT that is usually used, the input image signal of the display device is subjected to a 2.2 power inverse gamma correction process to return to the linear gradation characteristics. It is necessary to display an image.

  On the other hand, in these display devices, the number of gradations (bit number) of the input signal may be larger than the number of gradations (bit number) that can be expressed by the display device. In some cases, the number of gradations (number of bits) expressed by the display device is intentionally reduced from the number of gradations (bits) of the input signal.

  Further, when the inverse gamma correction circuit performs the inverse gamma correction processing to return to the linear gradation, the number of bits may be temporarily increased from the number of bits that can be expressed by the display device. This is due to the following reason. When the inverse gamma correction process is performed to return to a linear gradation, the number of gradations at a low luminance level is impaired, and image quality interference often resulting from the loss of gradation continuity may occur. In particular, in the case of PDP, one field is composed of a plurality of subfields having different light emission weights, and gradation is expressed by selecting a plurality of subfields. Therefore, depending on the selection condition of the subfield, the visual luminance difference with respect to the adjacent gradation becomes large, and as a result, the pseudo-contour image quality interference may occur. Therefore, in order to prevent the gradation from being lost as much as possible, the inverse gamma correction processing is performed with the number of bits higher than the number of bits of the original signal, and the number of bits is increased and output.

  As described above, the number of bits of the input video signal or the number of gradations (first bit number) of the video signal output from the inverse gamma correction circuit is the number of gradations (second bit number) expressed by the display device. If it is greater than (), it is necessary to reduce the number of gradations (number of bits). If the number of gradations (number of bits) is reduced, gradations are impaired, and therefore, multi-gradation processing is performed using an error diffusion method.

  The multi-gradation processing by the error diffusion method is performed as follows as an example in order to obtain an image corresponding to the first number of bits exceeding the digitally limited second number of bits. In FIG. 8, P is one of the three dots constituting the target pixel, and is a dot having the number of gradations that cannot be expressed as it is with the second number of bits. A is a dot on the right, B is a lower left dot, C is a lower dot, and D is a lower right dot. As shown in FIG. 8, the first bit number that cannot be expressed in the target dot P−the second bit number is diffused with a certain weight applied to the plurality of peripheral dots A to D, and apparently, It is a common method to perform multi-gradation processing so that an image corresponding to the first number of bits is obtained.

For example, when the display device has only 8-bit gradation capability and gradation display is performed with the upper 8 bits of the 12-bit dot data, the dot data for the remaining lower 4 bits is given a certain weight, and the peripheral dots By diffusing to A to D, a gradation display equivalent to 12 bits is performed using a visual integration effect. In FIG. 8, 7/16, 3/16, 5/16, and 1/16 attached to the peripheral dots A to D are examples of error diffusion coefficients representing the degree of weighting. A common error diffusion coefficient is used for the three primary color signals of R, G, and B.
JP-A-10-51638 Japanese Patent Application Laid-Open No. 8-116459

  In the case of a display device as described above, particularly in the case of a PDP, by performing the multi-gradation processing by the error diffusion method as described above, the number of apparent gradations is increased and the image quality of the pseudo contour shape is increased. I try to reduce interference. However, in the past, the number of bits used for error diffusion for the three primary color signals of R, G, and B is set to a common bit number and a common error diffusion coefficient is used. When displaying a fixed pattern or the like, there is a problem that image quality interference such as periodic pattern noise peculiar to error diffusion may occur.

  On the other hand, display devices such as PDPs continue to improve in performance due to improvements in the structure of the panel and the materials constituting the inside of the panel, and the increase in the brightness of the panel is progressing. For this reason, image quality interference such as periodic pattern noise peculiar to the above error diffusion tends to become more conspicuous. In particular, it has been clarified that an image having many low gradation portions has a problem that the image quality is further deteriorated as the brightness of the panel is increased.

  The present invention has been made in view of such problems, and extremely effectively reduces image quality interference such as periodic pattern noise that appears when error diffusion processing is performed even if the brightness of the panel is increased. It is an object of the present invention to provide an error diffusion processing method and an error diffusion processing device for a display device that can perform the above-described process.

The present invention reduces the R, G, and B signals having the first number of bits to a second number of bits that is smaller than the first number of bits in order to solve the above-described problems of the prior art. At this time, at least a part of the lower bits of the first bit number, which is the difference between the first bit number and the second bit number in each pixel of interest composed of dots of R, G, B signals In the error diffusion processing method of a display device, in which error data obtained by multiplying a predetermined error diffusion coefficient by a predetermined error diffusion coefficient is diffused to a plurality of pixels located at least one line behind the target pixel, the error diffused to the plurality of pixels By shifting the reading start position of the memory holding the data, the error data in the line behind the at least one line in at least one of the R, G, and B signals. Providing an error diffusion processing method for a display device, wherein said varying the relative diffusion locations for other signal for the target pixel of.
In addition, in order to solve the above-described problems of the prior art, the present invention provides an error diffusion processing apparatus that performs error diffusion processing on each of R, G, and B signals. When the number of bits is reduced to a second number of bits smaller than the first number of bits, the first number of bits and the second number of bits in each pixel of interest composed of dots of R, G, and B signals An R signal that is diffused to a plurality of pixels located in a line at least one line behind the target pixel by multiplying at least a part of the lower bits of the first bit number, which is a difference from the number, by a predetermined error diffusion coefficient A first error diffusion processing circuit (3R) comprising a first error detection circuit (33R) for generating the error data of the first signal and a first memory (36) for holding the error data of the R signal, First bit Is reduced to the second number of bits, at least one of the lower bits of the first number of bits, which is the difference between the first number of bits and the second number of bits in the pixel of interest. A second error detection circuit (33G) that multiplies the unit by a predetermined error diffusion coefficient to generate error data of a G signal that is diffused to a plurality of pixels located at least one line behind the target pixel; A second error diffusion processing circuit (3G) including a second memory for storing error data of the G signal, and reducing the B signal having the first bit number to the second bit number; Multiplying at least part of the lower bits of the first bit number, which is the difference between the first bit number and the second bit number in the target pixel, by a predetermined error diffusion coefficient, A third error detection circuit (33B) that generates error data of the B signal that is diffused to a plurality of pixels located on the line behind the line; and a third memory that holds the error data of the B signal. 3 error diffusion processing circuits (3B), and by shifting the reading start position of at least one error data in the first to third memories, at least one of the R, G, B signals There is provided an error diffusion processing device configured such that a relative diffusion location of the error data with respect to the target pixel in the line behind the at least one line is different from other signals.

  According to the error diffusion processing method and the error diffusion processing device of the display device of the present invention, it is possible to drastically reduce the occurrence probability of image quality interference such as periodic pattern noise that appears when error diffusion processing is performed, and to achieve high image quality. Display can be realized. Even if the brightness of the panel increases and the brightness step difference in the low gradation part increases, the light emission probability (number of times of light emission) of each dot by a certain area is averaged, so that an image with many low gradations can be obtained. Even if it appears, it does not feel the noise due to error diffusion, and the deterioration of image quality due to the high brightness of the panel can be suppressed.

  Hereinafter, an error diffusion processing method and an error diffusion processing apparatus for a display device according to the present invention will be described with reference to the accompanying drawings. 1 is a block diagram showing an embodiment of a display device using the error diffusion processing method of the present invention, FIG. 2 is a block diagram showing a specific configuration example of the error diffusion processing circuit 3 in FIG. 1, and FIG. FIG. 4 is a diagram for explaining an example of the error diffusion processing method of the present invention, FIG. 4 is a diagram for explaining another example of the error diffusion processing method of the present invention, and FIG. 5 is still another example of the error diffusion processing method of the present invention. FIG. 6 is a diagram for explaining an example, FIG. 6 is a diagram for explaining the gist of the first embodiment of the error diffusion processing method of the present invention, and FIG. 7 is the gist of the second embodiment of the error diffusion processing method of the present invention. It is a figure for demonstrating.

  In this embodiment shown in FIG. 1, a case is shown in which a PDP is used as a matrix type display device that can express an image only with a digitally limited number of gradations. Of course, the display device of the present invention is not limited to the PDP. In FIG. 1, three systems of video signals composed of R, G, and B signals are input to the video signal processing circuit 1. The video signal processing circuit 1 performs various types of video signal processing on these video signals and inputs them to the inverse gamma correction circuit 2. For example, the R, G, and B signals are 8-bit digital signals, that is, signals having 256 gradations.

  The inverse gamma correction circuit 2 performs reverse gamma correction processing with the same characteristics on the input R, G, and B signals, and outputs a 12-bit digital signal, that is, a signal of 4096 gradations as an example. The reason why the 8-bit digital signal is output as the 12-bit digital signal is to prevent the number of gradations from being damaged by the inverse gamma correction processing as described above.

  The R, G and B signals output from the inverse gamma correction circuit 2 are input to the error diffusion processing circuit 3. The error diffusion processing circuit 3 includes an R error diffusion processing circuit 3R, a G error diffusion processing circuit 3G, and a B error diffusion processing circuit 3B, and the R, G, and B signals are respectively error diffusion processing circuits 3R, 3G. , 3B. The error diffusion processing circuits 3R, 3G, and 3B perform error diffusion processing on the input R, G, and B signals and output the signals. That is, for example, the lower 4 bits of the 12-bit digital signal are given a certain weight and then spread to the upper 8 bits to be output as an 8-bit digital signal.

  At this time, the error diffusion processing circuits 3R, 3G, and 3B do not use a common error diffusion coefficient, but have different error diffusion coefficients used in at least one circuit, or the number of bits used for error diffusion in at least one circuit. Make them different. For example, only for the B signal, the error diffusion coefficient is made different, or a total of 3 bits from the lower 4 bits to the lower 2 bits of the 12-bit digital signal are diffused into the upper 8 bits, and the 8-bit digital Output as a signal.

  Further, the error data to be diffused to the pixels located one line or more behind the target pixel, that is, the pixels B, C, and D in FIG. Different diffusion locations are used to diffuse the dots. At this time, this diffusion location is changed for at least one of the R, G and B signals or for each line. The diffusion location to pixels located behind one or more lines of the target pixel may be made different for all of the R, G, and B signals.

  As described above, according to the present invention, the diffusion location to the dot of the pixel located one or more lines behind the target pixel is changed with respect to at least one of the R, G, and B signals or for each line. There is a special feature. The detailed contents of these error diffusion processes will be described later. In this embodiment, as a more preferred embodiment, in addition to changing the diffusion location, a common error diffusion coefficient is not used for the R, G, B signals, but the error diffusion coefficient for at least one signal is changed to another. It is different from the error diffusion coefficient for the signal, or the number of bits used for error diffusion for at least one signal, that is, the number of bits diffused to the upper 8 bits is different from the number of bits used for error diffusion for other signals.

  The R, G, and B signals subjected to the error diffusion processing by the error diffusion processing circuits 3R, 3G, and 3B are input to the PDP 4. The PDP 4 displays various R, G, and B signals on the screen after performing various drive processes such as a subfield process.

  Here, a specific configuration of the error diffusion processing circuit 3 will be described with reference to FIG. The error diffusion processing circuit 3R for R, the error diffusion processing circuit 3G for G, and the error diffusion processing circuit 3B for B all have the same configuration, but the set error diffusion coefficient, the number of bits used for error diffusion, and the diffusion location are different. ing. Therefore, the configuration of the G error diffusion processing circuit 3G and the B error diffusion processing circuit 3B is the same as that of the R error diffusion processing circuit 3R, so that the illustration is simplified and the description of the operation is omitted. .

  In FIG. 2, the 12-bit R signal input from the inverse gamma correction circuit 2 is output through adders 31 and 32, which will be described later. Of the 12-bit data output from the adder 32, the lower 4 bits are This is input to the R error detection circuit 33R. The lower 4 bits correspond to the gradation difference lost by reducing the 12-bit digital signal (4096 gradations) to the 8-bit digital signal (256 gradations). The R error detection circuit 33R multiplies the input lower 4 bits of data by error diffusion coefficients corresponding to the peripheral dots A ′ to D ′ shown in FIG. 3A or FIG. Is generated.

  From the terminals a to d shown in the R error detection circuit 33R, error data obtained by multiplying the lower 4 bits of data by an error diffusion coefficient corresponding to the peripheral dots A 'to D' is output. In the case of FIG. 3A or FIG. 4A, the lower 4 bits of data are multiplied by 7/16, 3/16, 5/16, 1/16 from the terminals a to d, respectively. Error data is output. The relationship between the peripheral dots A ′ to D ′ and the peripheral dots A to D will be described later.

  The error data output from the terminal a is input to the adder 32, the error data output from the terminal b is input to the adder 35, and the error data output from the terminals c and d is input to the adder 34. . The adder 34 adds the error data from the input terminals c and d and inputs the added error data to the adder 35. The adder 35 adds the error data output from the terminal b and the output of the adder 34 and inputs the result to the line memory 36. The line memory 36 delays the output of the adder 35 by a time slightly shorter than one line and inputs it to the adder 31.

  The adder 31 adds the input R signal and the output of the line memory 36 and inputs the sum to the adder 32. Assuming that the input R signal is the noticed dot P ′ shown in FIG. 3A or FIG. 4A, the adder 31 is error data generated in the past for approximately one line with respect to the noticed dot P ′. The operation of adding the output of the line memory 36, that is, B ′ × 3/16 + C ′ × 5/16 + D ′ × 1/16 is performed.

  The adder 32 adds the output of the adder 31 and the error data output from the terminal a of the R error detection circuit 33R. That is, the adder 32 adds error data generated in the past of one dot to the output of the adder 31 obtained by adding error data generated in the past of approximately one line to the target dot P ′. The operation of adding 7/16 is performed. As described above, error data obtained by multiplying the peripheral dots A ′ to D ′ by the respective error diffusion coefficients is added to the target dot P ′ shown in FIG. 3A or 4A. Of the 12-bit data output from the adder 32, the lower 4 bits are input to the R error detection circuit 33R, and the above operation is repeated.

  The upper 8 bits of the 12-bit data output from the adder 32 are input to the limiter 37. The limiter 37 limits and outputs the amount of data obtained by adding error data to the target dot P ′ exceeding 8 bits (overflow).

  As described above, the error data addition process for the target dot P ′ is sequentially performed for each dot. As a result, as shown in FIG. 3A or FIG. This means that the minute data is multiplied by an error diffusion coefficient of 7/16, 3/16, 5/16, 1/16 and diffused to the peripheral dots A to D.

  In the example shown in FIG. 2, the error diffusion coefficient set in the G error detection circuit 33G in the G error diffusion processing circuit 3G is the same as the error diffusion coefficient set in the R error detection circuit 33R, and the B error diffusion processing is performed. The error diffusion coefficient set in the B error detection circuit 33B in the circuit 3B and the number of bits used for error diffusion are the error diffusion coefficient set in the R error detection circuit 33R and the G error detection circuit 33G and the number of bits used for error diffusion. It is different from.

  FIG. 3 shows a case where the error diffusion coefficients are made different. As shown in FIG. 3B, for the B signal, the data for the lower 4 bits in the target dot P is 9/16, 2 The error diffusion coefficients of / 16, 4/16, and 1/16 are multiplied to diffuse to the peripheral dots A to D.

  In this manner, the error diffusion processing circuits 3R, 3G, and 3B perform error diffusion on one signal or all signals in the R, G, and B signals in the target pixel that is configured by three dots of the R, G, and B signals. By varying the coefficients and performing error diffusion processing on the R, G, and B signals, 12-bit data is output as 8-bit data. Note that all of the error diffusion coefficients for the peripheral dots A to D may be made different, or only some of them may be made different. In the example of FIG. 3, the error diffusion coefficient for the peripheral dot D is 1/16, and the error diffusion coefficients for the other peripheral dots A to C are different. Note that it is better to make the error diffusion coefficient slightly different than to make it significantly different.

  As described above, even in the PDP 4 having only 8-bit display capability, it is possible to display an image that can be apparently recognized as a display image equivalent to 12 bits by using the visual integration effect. Since a common error diffusion coefficient is not used as an error diffusion coefficient for R, G, and B signals, even when a fixed pattern or the like is displayed, image quality disturbances such as periodic pattern noise peculiar to error diffusion are visually recognized. Hard to do. Therefore, a high-quality display device can be provided.

  FIG. 4 shows a case where the number of bits used for error diffusion is varied. As shown in FIG. 4B, for the B signal, the lower 4th bit to the lower 2nd bit in the target dot P are shown. The three bits of data up to the above are multiplied by error diffusion coefficients of 4/8, 1/8, 2/8, and 1/8, and are diffused to the peripheral dots A to D.

  In this embodiment, error diffusion is performed using 3 bits from the lower 4th bit to the lower 2nd bit in the 12-bit B signal, but the inverse gamma correction in the inverse gamma correction circuit 2 is applied to the B signal. At the processing stage, it is configured to output an 11-bit digital signal, that is, a 2048 gradation signal with the same inverse gamma correction characteristics as the R and G signals, and the lower 3 bits of data are multiplied by the above error diffusion coefficient. Then, it may be diffused to the peripheral dots A to D.

  In this case, if the inverse gamma correction processing of the B signal is realized by a look-up table (LUT) using a read only memory (ROM), the ROM capacity can be saved accordingly. There is an effect of becoming. Further, when the inverse gamma correction processing is 11 bits, all the processing performed by the B error diffusion processing circuit 3B is a processing circuit for 3 bits, so that circuit capacity is saved. There is also an effect that the delay of about one line in the line memory 36 can be reduced by one bit.

  In this manner, the error diffusion processing circuits 3R, 3G, and 3B perform error diffusion on one signal or all signals in the R, G, and B signals in the target pixel that is configured by three dots of the R, G, and B signals. The R, G, and B signals are subjected to error diffusion processing by changing the number of bits used for, thereby outputting 12-bit data (B signal is 11 bits) as 8-bit data. It should be noted that the number of bits used for error diffusion is better to be slightly different than to be significantly different.

  As described above, even in the PDP 4 having only 8-bit display capability, an image that can be recognized as a display image equivalent to 12 bits (B signal is equivalent to 11 bits) by using the visual integration effect. Can be displayed. Since the number of bits used for error diffusion for R, G, and B signals is not common, even when a fixed pattern or the like is displayed, image quality interference such as periodic pattern noise peculiar to error diffusion is not easily recognized visually. . Therefore, a high-quality display device can be provided.

  In this embodiment, the number of bits used for error diffusion of the B signal is 3 bits, and the number of bits used for error diffusion of the R and G signals is 4 bits. However, the number of bits used for error diffusion is 3 bits or 4 bits. It is not limited to. It is preferable that not all of the lower bits of the first number of bits, which are the difference between the first number of bits and the second number of bits, be used for error diffusion, but a part thereof is used for error diffusion. As described above, the higher-order bits consecutive from the most significant bit (the lower-order fourth bit in the above example) of the lower-order bits are used.

  In this embodiment, the number of bits used for error diffusion of the R and G signals is 4 bits, and the error diffusion coefficient of each peripheral dot is the same. However, the error diffusion coefficients of the peripheral dots may be different. As an example, for the R signal, as shown in FIG. 5 (A), the error diffusion coefficients of 7/16, 3/16, 5/16, 1/16 are added to the data of the lower 4 bits in the target dot P. To the surrounding dots A to D, and for the G signal, as shown in FIG. 5B, the lower 4 bits of the data of the target dot P are 9/16, 2/16, The error diffusion coefficients of 4/16 and 1/16 are multiplied and diffused to the peripheral dots A to D. For the B signal, as shown in FIG. 4/8, 1/8, 2/8, 1/8 error diffusion for 3 bits of data from the first to the lower 2 bits (or data for the lower 3 bits if the inverse gamma correction is 11 bits) You may make it spread to surrounding dots AD by multiplying with a coefficient.

  In this manner, the error diffusion processing circuits 3R, 3G, and 3B perform error diffusion on one signal or all signals in the R, G, and B signals in the target pixel that is configured by three dots of the R, G, and B signals. By performing error diffusion processing on the R, G, and B signals by varying the coefficients, or by varying the number of bits used for error diffusion for one signal or all signals in the R, G, and B signals , 12-bit or 11-bit data is output as 8-bit data.

  Next, in addition to the error diffusion processing method shown in FIGS. 3 to 5, the diffusion location to the dot of the pixel located one or more lines behind the target pixel is determined for at least one of the R, G, and B signals. Alternatively, a method of changing for each line will be described. In this example, as a more preferred embodiment, a case where the diffusion location is made different for each of the R, G, and B signals will be described. FIG. 6 shows an example of changing the diffusion location of dots of pixels located one or more lines behind the target pixel for each R, G, B signal, and FIG. 7 exists one line or more behind the target pixel. An example of changing the diffusion location of the pixel to the dot for each line is shown.

  First, FIG. 6 will be described. The attention dots P shown in FIGS. 6A, 6B, and 6C are pixels located at the same place, and are three dots that constitute the attention pixel. Each error diffusion coefficient diffused to the dots A, B, C, and D shown in FIG. 6 is the same as each error diffusion coefficient diffused to the dots A, B, C, and D shown in FIGS. It's okay. In FIG. 6, description of the value of each error diffusion coefficient diffusing to dots A, B, C, and D is omitted.

  For the R signal of FIG. 6A, the target dot P is diffused to the right adjacent dot A, the directly lower dot B, the lower right dot C, and the lower right pixel D. For the G signal in FIG. 6B, the target dot P is diffused to the right adjacent dot A, the lower left dot B, the direct lower dot C, and the lower right dot D. With respect to the B signal in FIG. 6C, the target dot P is diffused to the right adjacent dot A, the lower left dot B, the lower left dot C, and the lower right dot D. In this way, the diffusion locations of the pixels located behind one or more lines of the pixel of interest (here, the pixels located behind one line) to the dots are made different for each of the R, G, and B signals.

  The R error diffusion processing circuit 3R, the G error diffusion processing circuit 3G, and the B error diffusion processing circuit 3B shown in FIG. 2 have the same circuit configuration, but R, G, and B signals as shown in FIG. The change of the diffusion location for each line can be easily realized, for example, by shifting the read start position of each line memory 36 for each R, G, B signal. If the change of the diffusion location is realized by shifting the reading start position of the line memory 36, as shown in FIG. 6, the relative positional relationship between the dots B, C, and D (the order and the distance between the dots). Is not changed.

  The present invention is not limited to this, and the relative positional relationship between the dots B, C, and D may be shifted within the same line, or the dots B, C, and D may be positioned on different lines. Good. For example, the R signal may be diffused one line below the target dot P, the G signal may be diffused two lines below the target dot P, and the B signal may be diffused three lines below the target dot P. Furthermore, the relative positions of the dots B, C, and D including the dot A with respect to the target pixel P may be changed.

  Next, FIG. 7 will be described. In FIG. 7, the first line to the fifth line... Represent the display lines of the PDP 4. It is assumed that the attention dot P is at the position shown in FIG. The target dot P is one of R, G, and B signals, and the dots B to N shown in the second and subsequent lines are signals of the same color as the target dot P.

  The error data is diffused from the attention dot P on the first line to the dot A on the right, the dot B immediately below, the dot C on the lower right, and the dot D on the lower right of the pixel. The error data is diffused to the surrounding pixels in the first line in the same manner except for the target dot P shown in the figure. The right adjacent dot is A, the immediately lower dot is B, the lower right dot is C, and the lower right pixel is 2 pixels. Are diffused as D. Each error diffusion coefficient diffusing to the dots A, B, C, and D shown in FIG. 7 is the same as each error diffusion coefficient diffusing to the dots A, B, C, and D shown in FIGS. It's okay. In FIG. 7, the description of the value of each error diffusion coefficient that diffuses to dots A, B, C, and D is omitted.

  Next, in the second line, the dot B is the attention dot, in the third line, the dot F is the attention dot, and in the fourth line, the dot J is the attention dot. From the noticed dot B on the second line, it diffuses to the dot C on the right side, the dot E on the lower left, the dot F just below, and the dot G on the lower right. The value of the error diffusion coefficient that diffuses to the right adjacent dot C, the lower left dot E, the directly lower dot F, and the lower right dot G is the dot A, B, C, and D that diffuses from the target dot P on the first line. The value of each error diffusion coefficient is the same.

  From the noticed dot F on the third line, it diffuses to the right adjacent dot G, the lower left dot H, the lower left dot I, and the lower right dot J. The value of the error diffusion coefficient that diffuses to the right adjacent dot G, the lower left dot H, the lower left dot I, and the direct lower dot J is the dot A, B, C, D that diffuses from the target dot P on the first line. It is the same as each error diffusion coefficient in. From the noticed dot J on the fourth line, it diffuses to the dot K on the right, the dot L directly below, the dot M on the lower right, and the dot N on the lower right of the pixel. The value of the error diffusion coefficient that diffuses to the right adjacent dot K, the right lower dot L, the lower right dot M, and the second lower right dot N is the dot A, B, C diffused from the target dot P of the first line. , D are the same as the values of the respective error diffusion coefficients.

  The R error diffusion processing circuit 3R, the G error diffusion processing circuit 3G, and the B error diffusion processing circuit 3B shown in FIG. 2 have the same circuit configuration, but the diffusion location for each line as shown in FIG. The change can be easily realized by, for example, shifting the read start position of each line memory 36 for each line. If the change of the diffusion location is realized by shifting the reading start position of the line memory 36, as shown in FIG. 7, the relative positions of the dots positioned one line behind the target dot P, B, F, J. The positional relationship (order and distance between each dot) is not changed.

  The present invention is not limited to this, and within the same line, the relative positional relationship of each of the three dots positioned behind one line is shifted, or the position of the rear line that diffuses for each line is switched. Two dots may be positioned on different lines. For example, the target dot P on the first line diffuses down one line, the target dot B on the second line diffuses down two lines, the target dot F on the third line diffuses down three lines, etc. Then, the diffusion distance in the line direction may be varied. Furthermore, the relative position with respect to the pixel of interest may be changed, including the dot located on the same line as the pixel of interest (dot A in the first line).

  As described above, when performing error diffusion processing, the error data diffusion location is changed for at least one of the R, G, and B signals or for each line. The occurrence probability of image quality interference such as periodic pattern noise appearing at the time can be drastically reduced, and a high-quality display can be realized. In addition, you may combine the change of the spreading | diffusion location with respect to R, G, B signal, and the change of the spreading | diffusion location for every line.

  According to the present invention, even if the brightness of the panel increases and the brightness step difference in the low gradation part increases, the light emission probability (number of times of light emission) of each dot in a certain area is averaged, so the vicinity of the low gradation Even if an image with a large amount of images appears, the noise caused by error diffusion is not felt, and deterioration of the image quality due to an increase in the brightness of the panel can be suppressed.

It is a block diagram which shows one Example of the display apparatus using this invention. FIG. 2 is a block diagram illustrating a specific configuration example of an error diffusion processing circuit 3 in FIG. 1. It is a figure for demonstrating an example of this invention. It is a figure for demonstrating another example of this invention. It is a figure for demonstrating another example of this invention. It is a figure for demonstrating the summary of 1st Example of this invention. It is a figure for demonstrating the summary of 2nd Example of this invention. It is a figure for demonstrating a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Video signal processing circuit 2 Inverse gamma correction circuit 3 Error diffusion processing circuit 3R Error diffusion processing circuit for 3G G Error diffusion processing circuit 3B Error diffusion processing circuit for B 4 Plasma display panel display device (PDP)

Claims (10)

When the R, G, B signal having the first number of bits is reduced to the second number of bits, which is smaller than the first number of bits, each of the R, G, B signal configured by dots Error data obtained by multiplying at least a part of the lower bits of the first bit number, which is the difference between the first bit number and the second bit number in the target pixel, by a predetermined error diffusion coefficient is used as the target pixel. In an error diffusion processing method of a display device that diffuses to a plurality of pixels located in a line that is at least one line behind,
By shifting the read start position of the memory that holds the error data diffused to the plurality of pixels, the error data in the line behind the at least one line in at least one of the R, G, and B signals. An error diffusion processing method for a display device, characterized in that a relative diffusion location with respect to a pixel of interest is different from that of another signal.   By shifting the read start position of the memory that holds the error data diffused to the plurality of pixels, the error data in the line at least one line behind the target pixel of the R, G, and B signals with respect to the target pixel. 2. The error diffusion processing method for a display device according to claim 1, wherein the relative diffusion locations are different from each other.   3. The error diffusion processing method for a display device according to claim 1, wherein a horizontal diffusion place is made different within one line without changing a relative positional relationship among the plurality of pixels. 4. .   4. The display according to claim 1, wherein an error diffusion coefficient for at least one of R, G, and B signals in the target pixel is made different from an error diffusion coefficient for other signals. An error diffusion processing method of the apparatus.   The number of bits used for an error diffusion coefficient for at least one of R, G, and B signals in the pixel of interest is different from the number of bits used for an error diffusion coefficient for other signals. 4. An error diffusion processing method for a display device according to any one of 3 above. In an error diffusion processing apparatus that performs error diffusion processing on each of the R, G, and B signals,
When the R signal having the first bit number is reduced to the second bit number having a bit number smaller than the first bit number, the R pixel in each pixel of interest formed by dots of the R, G, and B signals is used. A line that is at least one line behind the pixel of interest by multiplying at least a part of the lower bits of the first bit number, which is the difference between the first bit number and the second bit number, by a predetermined error diffusion coefficient A first error diffusion processing circuit comprising: a first error detection circuit that generates error data of an R signal that is diffused to a plurality of pixels located at a position; and a first memory that holds error data of the R signal. ,
When the G signal having the first bit number is reduced to the second bit number, the first bit number that is a difference between the first bit number and the second bit number in the target pixel. A second error detection circuit that multiplies at least some of the lower-order bits by a predetermined error diffusion coefficient to generate error data of a G signal that is diffused to a plurality of pixels located at least one line behind the pixel of interest. A second error diffusion processing circuit comprising: a second memory for holding error data of the G signal;
When the B signal having the first bit number is reduced to the second bit number, the first bit number that is a difference between the first bit number and the second bit number in the target pixel. A third error detection circuit for multiplying at least a part of the lower-order bits by a predetermined error diffusion coefficient to generate error data of a B signal that is diffused to a plurality of pixels located at least one line behind the pixel of interest And a third error diffusion processing circuit comprising a third memory for holding the error data of the B signal,
By shifting the read start position of at least one error data in the first to third memories, the error data in the line behind the at least one line in at least one of the R, G, and B signals. An error diffusion processing apparatus, characterized in that a relative diffusion place with respect to a pixel of interest is different from that of another signal.   By shifting the error data read start position in the first to third memories, relative to the target pixel of the error data in the line behind the at least one line in all signals of the R, G, B signals. 7. The error diffusion processing device according to claim 6, wherein the diffusion locations are made different from each other.   The error diffusion processing device according to claim 6 or 7, wherein a horizontal diffusion place is made different within one line without changing a relative positional relationship among the plurality of pixels. .   9. The error diffusion coefficient for at least one of R, G, and B signals in the target pixel is configured to be different from the error diffusion coefficient for other signals. The error diffusion processing apparatus described. The number of bits used for an error diffusion coefficient for at least one of R, G, and B signals in the target pixel is configured to be different from the number of bits used for an error diffusion coefficient for other signals. Item 9. The error diffusion processing device according to any one of Items 6 to 8.

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