JP2006033448A - MULTI-SAMPLING-RATE SigmaDeltaDAC SYSTEM, AND ACOUSTIC APPARATUS - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-sampling-rate ΣΔDAC system that improves the S/N when a plurality of digital input signals sampled at different sampling rates are converted by using a common ΣΔDAC device. <P>SOLUTION: A 1st digital input signal which is sampled at a sampling frequency twice or less as high as a nearly upper-limit frequency of the audio frequency range is processed by sampling rate conversion to generate a 1st up digital input signal. This 1st up digital input signal and a 2nd digital input signal of high sampling frequency are selected and supplied to the ΣΔDAC device to output analog signals. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a DAC (digital / analog converter) system, in particular, a multi-sampling rate ΣΔ DAC system for converting a plurality of digital input signals sampled at different sampling rates into an analog output signal, and a cellular phone using the same. It relates to audio equipment.

  Conventionally, as disclosed in Patent Document 1, there is a ΣΔ (sigma delta) or ΔΣ (delta sigma) DAC device that converts a digital input signal obtained by sampling an audio signal or the like at a predetermined sampling rate into an analog signal and outputs the analog signal. Known (hereinafter referred to as ΣΔDAC system).

  FIG. 4 is a diagram showing the configuration of the conventional ΣΔ DAC device 20. In FIG. 4, a digital input signal Sin is input to the ΣΔ DAC device 20. Here, the input signal Sin is a digital signal obtained by sampling an audio signal having a frequency of, for example, about 1 to several kHz at a predetermined sampling rate (sampling frequency).

  The predetermined sampling rate is 48 kHz as standard for mini-discs (hereinafter referred to as MD) and digital audio tape (hereinafter referred to as DAT), and 44.1 kHz as standard for compact discs (hereinafter referred to as CD).

  Here, it is assumed that an audio signal sampled at a standard sampling frequency of 48 kHz in MD or DAT is input to the ΣΔ DAC device 20 as the input signal Sin. This input signal Sin is upsampled to a predetermined multiple (for example, 8 times) by interpolating data in the upsampling circuit 21. The cutoff frequency of the digital LPF 22 is determined so as to attenuate an alias component (folding component) included in the upsampled data. The ΣΔ DAC 23 converts the digital data that has passed through the digital LPF 22 into analog data and inputs the analog data to the analog LPF 24, and an analog output signal Sout is output from the analog LPF 24. The same operation is performed when an audio signal sampled at a standard sampling frequency of 44.1 kHz in a CD is input.

  When an audio signal sampled at the standard sampling frequencies of 48 kHz and 44.1 kHz is input to the ΣΔ DAC device 20, the alias component is at a higher frequency than the audible frequency region (usually about 20 kHz or less). Therefore, noise due to the alias component, that is, deterioration of the S / N ratio is not a problem, and a highly accurate analog output signal Sout is output (that is, the S / N ratio is high).

  As described above, the ΣΔ DAC device 20 is designed for the input signal Sin sampled at the standard sampling frequencies of 48 kHz and 44.1 kHz, including the components such as the digital LPF 22 and the ΣΔ DAC 23.

  However, in an audio device such as a mobile phone, audio signals sampled at various sampling frequencies lower than that including the standard sampling frequencies 48 kHz and 44.1 kHz are often input to the ΣΔ DAC device 20. The sampling frequency is 8 kHz, 16 kHz, 24 kHz, 48 kHz, etc. for the first series F1 for MD and DAT, and 11.0325 kHz, 22.05 kHz, 44.1 kHz, etc. for the second series F2 for CD. is there.

  The case where the digital input signal Sin is sampled at 8 kHz of the first series F1 is taken as an example. Also in this case, the 8 kHz sampling input signal is upsampled to 64 kHz (= 8 kHz × 8 times) by the digital LPF 22 and low-pass filtered by the digital LPF 22. Since the ΣΔ DAC device 20 is designed for an input signal Sin sampled at 48 kHz, its D / A conversion operation is not suitable for an 8 kHz sampling input signal as it is.

  In this case, the cut-off frequency is changed so that the digital LPF 22 attenuates alias components (folding components) included in the up-sampled data so that the ΣΔ DAC device 20 is adapted to an input signal having a sampling frequency of 8 kHz. Is done.

  However, in the filtered output of the digital LPF 22, alias components (around 8 kHz, around 16 kHz, etc.) related to the input sampling frequency of 8 kHz may remain and be included in the audible frequency region. As a result, the noise floor NF rises from a frequency of about 4 kHz (input sampling frequency / 2) as shown in FIG. 5 showing the relationship between the level of the signal and noise floor and the frequency, and increases as the frequency increases. Therefore, the S / N ratio of the output signal Sout is lowered.

  In order to reduce the noise floor level and improve the S / N ratio, conventionally, the filter order of the digital LPF 22 is made variable and the order is increased in accordance with the sampling frequency of the input signal. It was.

  However, even if the filter order of the digital LPF 22 is increased, the rise of the noise floor NF is still within the audible frequency region (about 4 kHz), so the noise floor level is reduced, but it is difficult to improve significantly. there were.

Further, in this method of increasing the filter order of the digital LPF 22, it is necessary to change the configuration of the digital LPF 22 so that the order can be varied, and the burden of characteristic verification accompanying the configuration change is large.
JP 2004-72507 A

  Therefore, the present invention is a DAC system for converting a plurality of digital input signals sampled at different sampling rates including a digital input signal sampled at a sampling frequency in the audible frequency region into an analog signal, and comprising a common DAC device. It is an object of the present invention to provide a DAC system that improves the S / N ratio when converting each digital input signal without changing the cut-off frequency, filter order, or the like.

  It is another object of the present invention to provide an audio device such as a mobile phone that outputs a digital signal of a multi-sampling rate from a voice band to an audio band with good sound quality using a DAC system, particularly a multi-sampling rate ΣΔ DAC system. .

  The DAC system according to claim 1, wherein a plurality of digital input signals up-sampled at different sampling frequencies are input, and a signal selection circuit that selects and outputs one of the plurality of digital input signals is selected. A converter circuit for up-sampling at a constant sampling frequency regardless of a digital input signal; a filter circuit for filtering the output of the converter circuit with a constant filter order regardless of a selected digital input signal; And a DAC for converting the output into an analog signal.

The DAC system according to claim 2 is a converter circuit for up-sampling one selected digital input signal selected from a plurality of digital input signals each representing data in an audible frequency region at a predetermined sampling frequency, and A DAC system having a filter circuit to which an output is input and a DAC that converts the output of the filter circuit into an analog signal,
The converter circuit performs up-sampling at a frequency at which the noise floor of the DAC system rises past an audible frequency range.

The multi-sampling rate ΣΔ DAC system according to claim 3 is characterized in that a first digital input signal obtained by sampling an acoustic signal at a sampling frequency less than or equal to twice the upper limit frequency in the audible frequency region is a sampling frequency that is twice or more the upper limit frequency. The first sampling rate converter 11 up-converts, and outputs the first up-digital input signal up-converted by low-pass filtering the output of the first sampling rate converter 11 with the first digital LPF 12. Sampling rate conversion means;
The up-converted first up-digital input signal output from the sampling rate converting means and the second digital signal having a high sampling frequency obtained by sampling the acoustic signal at a sampling frequency that is approximately twice or more the upper limit frequency in the audible frequency range. An input signal, a multiplexer 13 for selecting and outputting either the first up digital input signal or the second digital input signal;
The first up digital input signal or the second digital input signal output from the multiplexer 13 is input as a digital signal, converted to an analog signal, and output.

  The multi-sampling rate ΣΔ DAC system according to claim 4 is the multi-sampling rate ΣΔ DAC system according to claim 3, wherein the ΣΔ DAC device is a noise whose level of the noise floor increases from about half the sampling frequency of the input digital input signal. It has a frequency characteristic.

  The multi-sampling rate ΣΔ DAC system according to claim 5 is the multi-sampling rate ΣΔ DAC system according to claim 4, wherein the ΣΔ DAC device up-samples the sampling frequency of the input digital input signal to a predetermined multiple. A second digital LPF 22A for low-pass filtering the output of the second sampling rate converter 21, a ΣΔ DAC 23 for converting the output of the second digital LPF 22A into an analog signal, and the output of the ΣΔ DAC 23 at a predetermined cutoff frequency. And an analog LPF for low-pass filtering.

  The multi-sampling rate ΣΔ DAC system according to claim 6 is the multi-sampling rate ΣΔ DAC system according to any one of claims 3 to 5, wherein the sampling frequency of the first up digital input signal and the sampling frequency of the second digital input signal are Are characterized by the same frequency.

  The multi-sampling rate ΣΔ DAC system according to claim 7 is the multi-sampling rate ΣΔ DAC system according to claim 6, wherein the sampling frequency of the second digital input signal is 48 kHz, and the sampling frequency of the first digital input signal is 8 kHz, It is one or more of 16 kHz and 24 kHz.

  The multi-sampling rate ΣΔ DAC system according to claim 8 is the multi-sampling rate ΣΔ DAC system according to claim 6, wherein the sampling frequency of the second digital input signal is 44.1 kHz, and the sampling frequency of the first digital input signal is It is characterized by being 11.25 kHz or 22.05 kHz.

  An audio device according to a ninth aspect includes the multi-sampling rate ΣΔ DAC system according to any one of the third to sixth aspects, and the multi-sampling rate ΣΔ DAC system at a sampling frequency that is approximately twice or less the upper limit frequency in the audible frequency region. A digital signal processing circuit for inputting a sampled first digital input signal and a second digital input signal sampled at a sampling frequency that is approximately twice the upper limit frequency in the audible frequency range; and the multi-sampling rate ΣΔDAC system. And an acoustic generation means to which an analog signal is supplied.

  According to the DAC system of the present invention, the first digital input signal is upsampled to a high sampling rate (oversampling), and the first up digital input signal is formed by reducing the alias component accompanying the upsampling by the first digital LPF. To do. The first up digital input signal and the second digital input signal sampled at a high sampling frequency are selectively input to a common DAC device. As a result, the S / N characteristic is improved because the DAC device operates as if high sampling rate data is input to the DAC system regardless of whether the first or second digital input signal is input. .

  In addition, since a complicated frequency characteristic changing process such as changing the cut-off frequency or filter order of the digital LPF of the ΣΔ DAC device is not required, the circuit of the ΣΔ DAC device can be easily configured. Further, since a ΣΔ DAC device having a fixed sampling rate can be used, a multi-sampling rate ΣΔ DAC system can be easily configured.

  In addition, since data of a plurality of types of sampling rates used in audio equipment such as a mobile phone can be integrated and processed, the development burden on those equipment can be reduced.

  Embodiments of a DAC system according to the present invention and an audio device such as a mobile phone using the DAC system will be described below with reference to the drawings. In the following embodiments, a mobile phone will be described as an example, but the present invention can be similarly applied to other acoustic devices.

  FIG. 1 is a diagram showing a configuration of a multi-sampling rate ΣΔ DAC system 10 according to the present invention.

  In FIG. 1, for example, a digital input signal Sin obtained by sampling an audio signal having a frequency of 1 to several kHz at a predetermined sampling frequency is input to the multi-sampling rate ΣΔ DAC system 10 as the first sequence F1 for MD and DAT. .

  As the sampling frequency, in addition to the high sampling frequency f4 = 48 kHz, which is a standard sampling frequency, low sampling frequencies f1 = 8 kHz, f2 = 16 kHz, and f3 = 24 kHz according to the required sound quality. Similarly, in the second series F2 for CD, in addition to the high sampling frequency f7 = 44.1 kHz, which is a standard sampling frequency, low sampling frequencies f5 = 11.025 kHz and f6 = 22.05 kHz according to the required sound quality. is there. Of course, other sampling frequencies may be used.

  In the present invention, regardless of which sampling frequency f1 to f7 is supplied to the multi-sampling rate ΣΔDAC system 10, the digital sampling signal input to the ΣΔDAC device 20A is a high sampling frequency 48 kHz or 44 which is a standard sampling frequency. Operates so that any of 1 kHz is input.

  The sampling frequency f4 = 48 kHz (second digital input signal Sin) of the first series F1 for MD or DAT, which is a high sampling frequency, and the sampling frequency f7 = 44.1 kHz (second digital input) of the second series F2 for CD. For sampling frequencies f1, f2, f3, f5, and f6 other than the input signal Sin), sampling rate conversion means comprising first sampling converters 11-1 to 11-6 and first digital LPFs 12-1 to 12-6 are provided. Each is provided.

  As for the sampling frequency f1 = 8 kHz, the first digital input signal Sin sampled at 8 kHz, which is a sampling frequency less than twice the upper limit frequency (about 20 kHz) in the audible frequency region, is input. The first digital input signal Sin sampled at 8 kHz is up-converted by the first sampling rate converter 11-1 to 6 times so that the sampling frequency is twice or more the upper limit side frequency (about 20 kHz) of the audible frequency. (8 kHz × 6 times = 48 kHz). This up-conversion processing may be performed by, for example, zero insertion processing so that the sampling frequency is 6 times.

  The first digital LPF 12-1 performs low-pass filtering so as to reduce the alias component from the output of the first sampling rate converter 11-1, and inputs the first up digital input signal up-converted to 48 kHz to the multiplexer 13. .

  The first digital LPF 12-1 functions as an interpolator and converts the signal up-converted by the zero insertion by the sampling rate converter 11-1 into a first up digital input signal having a sampling frequency of only 48 kHz. To do.

The first digital LPF 12-1 preferably has a performance as high as possible in order to sufficiently reduce the alias component. The first digital LPF 12-1 may have a fixed cutoff frequency and a fixed order.
The sampling rate converter 11-1 and the digital LPF 12-1 constitute sampling rate conversion means for an 8 kHz sampling input.

  The other sampling frequencies f2 = 16 kHz and f3 = 24 kHz of the first series F1 are the same as those for the sampling frequency f1 = 8 kHz, and the first sampling rate converters 11-2, 11-3 and the first digital LPF 12- 2 and 12-3 constitute sampling rate conversion means, and the first up-digital input signal converted to 48 kHz is input to the multiplexer 13.

  The other sampling frequencies f5 = 11.025 kHz and f6 = 22.05 kHz of the second series F2 are the same as those for the sampling frequency f1 = 8 kHz, and the first sampling rate converters 11-5, 11-6 and The 1 digital LPFs 12-5 and 12-6 constitute sampling rate conversion means, respectively, and the first up digital input signal converted to 44.1 kHz is input to the multiplexer 13.

  The multiplexer 13 receives a sampling frequency f4 of the first sequence F1 for MD or DAT, which is a second digital input signal having a high sampling frequency sampled at a sampling frequency that is approximately twice or more the upper limit frequency in the audible frequency range. The sampling frequency f7 = 44.1 kHz of 48 kHz and the second series F2 for CD is also input.

  In the multiplexer 13, each of the first up digital input signals based on the sampling frequencies f1, f2, f3, f5, and f6 and one of the second digital input signals of the sampling frequencies f4 and f7 are indicated by the selection signal SEL. To select and output to the ΣΔ DAC device 20A.

  Even when a digital input signal from any of the sampling frequencies f1 to f7 is input to the ΣΔ DAC device 20A, the ΣΔ DAC device 20A receives a digital input signal that is substantially sampled at a high sampling frequency of 48 kHz or 44.1 kHz. Will be.

  The ΣΔ DAC device 20A has substantially the same configuration as the conventional ΣΔ DAC device 20 of FIG. That is, the digital input signal 48 / 44.1 kHz is up-sampled to a predetermined multiple (for example, 8 times) by interpolating data by the second sampling rate converter (up-sampling circuit) 21.

  The cut-off frequency of the low-pass filtering is determined so that the second digital LPF 22A attenuates alias components (folding components) included in the data up-sampled by the second sampling rate converter 21.

  The ΣΔ DAC 23 converts the digital data that has passed through the second digital LPF 22A into analog data and inputs the analog data to the analog LPF 24, and an analog output signal Sout is output from the analog LPF 24.

  However, unlike the conventional digital LPF 22, the second digital LPF 22A may have a constant cutoff frequency, and the filter order may be a constant order. This is because the sampling frequency of the digital input signal input to the ΣΔ DAC device 20A is only 48 kHz or 44.1 kHz, and the frequency (48 / 44.1 kHz) is also approaching.

  This eliminates the need for complicated processing such as changing the order and cut-off frequency of the second digital LPF 22A of the ΣΔ DAC device 20A, so that the circuit of the ΣΔ DAC device can be easily configured. A ΣΔ DAC device having a fixed sampling rate can be used.

  FIG. 2 is a diagram showing the relationship between the signal and noise floor level and the frequency according to the multi-sampling rate ΣΔ DAC system 10 of the present invention. In the present invention, the sampling frequencies f1 = 8 kHz, f2 = 16 kHz, f3 = 24 kHz, and f4 = 48 kHz for the first series F1, and the sampling frequencies f5 = 11.025 kHz, f6 = 22.05 kHz, and f7 = for the second series F2. For any 44.1 kHz, the ΣΔ DAC device 20A receives a digital input signal with a sampling frequency of substantially 48 kHz or only 44.1 kHz.

  Therefore, as shown in FIG. 2, the noise floor NF rises from about 24 kHz (when the sampling frequency is 48 kHz) that is equal to or higher than the upper limit side frequency (about 20 kHz) of the audible frequency region. Or, when the sampling frequency is 44.1 kHz, the frequency rises from about 22 kHz. As a result, the noise floor NF falls outside the audible frequency region at all the sampling frequencies f1 to f7 input to the multi-sampling rate ΣΔDAC system 10. Since only the audio signal SIG exists in the audible frequency region, the S / N ratio is improved.

  FIG. 3 is a diagram illustrating a configuration example of the mobile phone 100 using the multi-sampling rate ΣΔ DAC system 10 of the present invention.

  3, in addition to the multi-sampling rate ΣΔ DAC system 10, the mobile phone 100 includes a digital baseband (hereinafter referred to as DBB) circuit 30, a sound source device 40, a microphone 50, a speaker 60, a headphone 70, an antenna 80, and other requirements. It has the composition part.

  The DBB circuit 30 generates a digital signal having sampling frequencies f1 to f4 of the first series F1, such as MD and DAT, based on an audio signal from the microphone 50, a received signal from the antenna 80, and the like, and a multi-sampling rate ΣΔ DAC system Enter 10.

  The tone generator 40 generates a digital signal of sampling signals f5 to f7 of the second series F2, such as a CD, and inputs it to the multi-sampling rate ΣΔDAC system 10. Of course, the DBB circuit 30 and the tone generator 40 are only examples, and may be other digital signal input means or may be input via an external input terminal.

  The multi-sampling rate ΣΔ DAC system 10 supplies an analog output signal Sout to, for example, a speaker 60 or a headphone 70 as sound generation means.

  As described above, since digital input data of a plurality of types of sampling rates f1 to f7 used in an acoustic device such as the mobile phone 100 can be integrated and processed by the multi-sampling rate ΣΔDAC system 10, a large number of filter circuits are required. This makes it possible to reduce the size of the apparatus and reduce the development burden of these acoustic devices.

The figure which shows the structure of the multi-sampling rate ΣΔ DAC system according to the present invention. The figure which shows the relationship between the level of the signal and noise floor by this invention, and a frequency The figure which shows the structural example of the mobile telephone using the (SIGMA) (DELTA) DAC system of this invention. The figure which shows the structure of the conventional ΣΔDAC device The figure which shows the relationship between the level of a signal and noise floor by a conventional ΣΔ DAC device, and frequency

Explanation of symbols

100 mobile phone 10 multi-sampling rate ΣΔ DAC system 11-1 to 11-6 first sampling rate converter 12-1 to 12-6 first digital LPF
13 Multiplexer 20A ΣΔ DAC device 21 Second sampling rate converter 22A Second digital LPF
23 ΣΔDAC
24 Analog LPF
Sin Digital input signal Sout Analog output signals f1 to f7 Sampling frequency 30 Digital baseband circuit 40 Sound source device 50 Microphone 60 Speaker 70 Headphone 80 Antenna

Claims (9)

  A plurality of digital input signals up-sampled at different sampling frequencies are input, a signal selection circuit that selects and outputs one of the plurality of digital input signals, and a constant regardless of the selected digital input signal A converter circuit that up-samples at a sampling frequency, a filter circuit that filters the output of the converter circuit with a constant filter order regardless of the selected digital input signal, and a DAC that converts the output of the filter circuit into an analog signal A DAC system comprising: A converter circuit for up-sampling one selected digital input signal selected from a plurality of digital input signals each representing data in the audible frequency region at a predetermined sampling frequency, and a filter circuit to which an output of the converter circuit is input A DAC system having a DAC for converting the output of the filter circuit into an analog signal,
The DAC system according to claim 1, wherein the converter circuit performs upsampling at a frequency at which a noise floor of the DAC system rises past an audible frequency range. Up-converting a first digital input signal obtained by sampling an acoustic signal at a sampling frequency less than or equal to twice the upper limit frequency in the audible frequency region to a sampling frequency more than twice the upper limit frequency by the first sampling rate converter; At least one sampling rate conversion means for outputting a first up-digital input signal that has been low-pass filtered and up-converted by a first digital LPF from the output of the first sampling rate converter;
The up-converted first up-digital input signal output from the sampling rate converting means and the second digital signal having a high sampling frequency obtained by sampling the acoustic signal at a sampling frequency that is approximately twice or more the upper limit frequency in the audible frequency range. An input signal, a multiplexer that selects and outputs either the first up digital input signal or the second digital input signal;
A multi-sampling rate ΣΔ DAC system comprising: a ΣΔ DAC device that receives the first up digital input signal or the second digital input signal output from the multiplexer as a digital signal, converts the digital signal into an analog signal, and outputs the analog signal. .   4. The multi-sampling rate ΣΔ DAC system according to claim 3, wherein the ΣΔ DAC device has a noise-frequency characteristic in which a level of a noise floor increases from a frequency about half of a sampling frequency of an input digital input signal.   The ΣΔ DAC device includes a second sampling rate converter 21 that upsamples a sampling frequency of an input digital input signal to a predetermined multiple, and a second digital LPF 22A that performs low-pass filtering on the output of the second sampling rate converter 21. The ΣΔDAC23 for converting the output of the second digital LPF 22A into an analog signal, and the analog LPF for low-pass filtering the output of the ΣΔDAC23 at a predetermined cut-off frequency, Multi-sampling rate ΣΔ DAC system.   6. The multi-sampling rate ΣΔ DAC system according to claim 3, wherein a sampling frequency of the first up-digital input signal and a sampling frequency of the second digital input signal are the same frequency.   The sampling frequency of the second digital input signal is 48 kHz, and the sampling frequency of the first digital input signal is any one or more of 8 kHz, 16 kHz, and 24 kHz. Rate ΣΔ DAC system.   The sampling frequency of the second digital input signal is 44.1 kHz, and the sampling frequency of the first digital input signal is 11.005 kHz or 22.05 kHz. Rate ΣΔ DAC system.   The multi-sampling rate ΣΔ DAC system according to any one of claims 3 to 6, and a first digital input signal sampled by the multi-sampling rate ΣΔ DAC system at a sampling frequency approximately equal to or less than twice the upper limit frequency in the audible frequency region. And a digital signal processing circuit for inputting a second digital input signal sampled at a sampling frequency that is approximately twice the upper limit side frequency in the audible frequency region, and an acoustic signal supplied with an analog signal from the multi-sampling rate ΣΔDAC system An acoustic device comprising a generating means.