JP2006033322A - Variable gain amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a variable gain amplifier in which a set gain will not change by the input voltage. <P>SOLUTION: A V-I converter C1 generates a current according to the input voltage ΔVIN (=VIN-VREF). Current distribution units C2, C3 respectively multiply the current generated in the V-I converter C1 by a constant by a current mirror circuit, duplicate the current, distribute and output from the outputs PP, PN and the outputs NP, NN, in response to a set value N. The output currents IPP, IPN from the current distribution unit C2 and the output currents INP, INN from the current distributing unit C3 are synthesized and become output currents IOUTP, IOUTN, respectively. The output currents IOUTP, IOUTN are converted into voltages by resistors R1, R2, respectively. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a variable gain amplifier capable of changing a gain according to a desired set value.

  The gain of the amplifier is given by the ratio of the feedback impedance and the input impedance. Therefore, the magnitude of the gain can be changed by changing the magnitude of the input side impedance.

  A conventional variable gain amplifier has a plurality of resistors and switch elements connected in series, and the input side impedance is configured by connecting them in parallel. With this configuration, the input-side impedance is given by the combined resistance of the resistors connected to the switch elements in the on state in parallel.

  As a result, the gain of the variable gain amplifier can be changed by controlling the on / off state of the switch element to change the magnitude of the combined resistance (for example, Patent Document 1 (FIG. 6B)).

  The inventions related to the present invention are disclosed in Patent Documents 2 and 3.

JP-A-9-36676 JP 2003-46352 A JP-A-9-326653

  However, when a MOS transistor is selected as the switch element, the internal resistance of the MOS transistor is added to the resistance constituting the input impedance. The internal resistance of the MOS transistor changes depending on the magnitude of the input voltage due to a channel length modulation effect or the like.

  As a result, there is a problem that the magnitude of the gain varies depending on the input voltage even if the gain setting is constant.

  Therefore, an object of the present invention is to provide a variable gain amplifier in which a set gain does not vary depending on an input voltage.

  The variable gain amplifier according to claim 1 is a variable gain amplifier that amplifies and outputs an input voltage with a gain according to a desired set value, and converts the input voltage into a current according to the input voltage. A current conversion unit, a current amplification unit that amplifies and outputs the output current of the voltage-current conversion unit to a current according to the desired set value, and a resistor that converts the output current of the current amplification unit into a voltage. It is characterized by providing.

  The variable gain amplifier according to claim 1 converts an input voltage into a current corresponding to the input voltage, and amplifies the current with a gain corresponding to a desired set value. Then, the input voltage is amplified by converting the amplified current into a voltage. Therefore, it is possible to obtain a variable gain amplifier in which the set gain does not vary depending on the input voltage.

<Embodiment 1>
FIG. 1 is a diagram showing a configuration of a variable gain amplifier according to the present embodiment. The differential input signal VIN is input to the positive phase input terminal of the V-I converter (voltage / current converter) C1. The differential input signal VREF is input to the negative phase input terminal of the V-I converter C1. The output P of the VI conversion unit C1 is connected to the input of the current distribution unit C2. Further, the output N of the VI conversion unit C1 is connected to the input of the current distribution unit C3.

  The output PP of the current distribution unit (first current distribution unit) C2 is connected to the output terminal OUTP and one end of the resistor R1. The other end of the resistor R1 is grounded. The output PN of the current distribution unit C2 is further connected to the output NP of the current distribution unit C3.

  An output NP of the current distribution unit (second current distribution unit) C3 is connected to the output terminal OUTN and one end of the resistor R2. The other end of the resistor R2 is grounded. The output NN of the current distribution unit C3 is connected to the output PP of the current distribution unit C2.

  The VI conversion unit C1 converts an input voltage ΔVIN that is a difference voltage between the differential input signals VIN and VREF into a current. That is, the input voltage ΔVIN is converted into an output current corresponding to the input voltage ΔVIN. And the output according to the converted electric current is output to electric current conversion part C2, C3.

  The current distribution units C2 and C3 receive the output of the VI conversion unit C1, duplicate the current generated by the current conversion unit C1 by a constant, and distribute the current to the two outputs according to the setting. Here, the current distribution unit C2 and the current distribution unit C3 constitute a current amplification unit. The current amplifying unit amplifies and outputs the output current of the VI conversion unit C1 to a current corresponding to a desired set value N described later.

  Resistors R1 (first resistor) and R2 (second resistor) convert the output current from the current amplifying unit into a voltage.

  Next, the configuration of the VI conversion unit C1 will be described in detail. FIG. 2 is a circuit diagram showing a configuration of the VI conversion unit C1. One end of the constant current source IS1 is connected to the power supply voltage VDD. The other end is connected to the output P and the drain of the NMOS transistor M1.

  The source of the NMOS transistor M1 is connected to one end of the constant current source IS2, and the other end of the constant current source IS2 is grounded. The gate of the NMOS transistor M1 serves as a positive phase input terminal, and the differential input signal VIN is input thereto.

  The source of the NMOS transistor M1 is connected at point D to one end of the resistor RSS and the drain of the PMOS transistor M2. The source of the PMOS transistor M2 is connected to the power supply voltage VDD, and the gate is connected to the output P.

  The other end of the resistor RSS is connected at point E to the drain of the PMOS transistor M3 and the source of the NMOS transistor M4. The source of the PMOS transistor M3 is connected to the power supply voltage VDD. The gate of the PMOS transistor M3 is connected to the output N.

  The source of the PMOS transistor M4 is connected to one end of the constant current source IS4. The other end of the constant current source IS4 is grounded. The drain of the PMOS transistor M4 is connected to the output N and one end of the constant current source IS3. The other end of the constant current source IS3 is connected to the power supply voltage VDD. The gate of the PMOS transistor M4 is a reverse phase input terminal, and the differential input signal VREF is input thereto.

  Here, the constant current sources IS1 to IS4 are configured by transistors, resistors, and the like, and the configuration method is not particularly limited. However, the constant current source IS1 and the constant current source IS3 are configured so that the same current flows. The constant current source IS2 and the constant current source IS4 are also configured so that the same current flows.

  Further, the NMOS transistor M1 and the NMOS transistor M4 are configured to have the same gate length, gate width, and the like. The PMOS transistor M2 and the PMOS transistor M3 are also configured to have the same gate length, gate width, and the like.

Next, the operation of the VI conversion unit C1 configured as described above will be described. First, all the current flowing through the constant current source IS1 flows through the NMOS transistor M1. A current flowing through the NMOS transistor M1 is defined as a current IM1. When the threshold voltage Vth and β value of the NMOS transistor M1 are VtM1 and βM1, respectively, the potential VD at the point D is
VD = VIN-SQRT (2 ・ IM1 / βM1) -VtM1… (1)
Given in.

Similarly, if the threshold voltage Vth and β value of the NMOS transistor M4 are VtM4 and βM4, respectively, and the current flowing through the NMOS transistor M4 is IM4, the potential VE at the point E is
VE = VREF-SQRT (2 ・ IM4 / βM4) -VtM4… (2)
Given in.

  As described above, the NMOS transistors M1 and M4 have the same gate length and gate width, and therefore have the same threshold voltage (VtM1 = VtM4) and the same β value (βM1 = βM4). Since the currents flowing through the constant current sources IS1 and IS3 are the same, IM1 = IM4.

Therefore, from equations (1) and (2),
VD-VE = VIN-VREF… (3)
It becomes.

The potential difference VD−VE applied to both ends of the resistor RSS is VIN−VREF from the equation (3). The current IRSS flowing through the resistor RSS has the resistance value of the resistor RSS as RRSS.
IRSS = (VIN-VREF) / RRSS… (4)
Given in.

Since the current flowing through the constant current sources IS1 to IS4 is always constant, the current IRSS is supplied by the current flowing through the PMOS transistors M2 and M3. That is, when the differential input signals VIN and VREF are equal (VIN = VREF), if the current flowing through the PMOS transistors M2 and M3 is the current I0, the current IM2 flowing through the PMOS transistors M2 and M3 when VIN−VREF = ΔVIN. (First output current) and IM3 (second output current) are
IM2 = I0 + (ΔVIN / RRSS)… (5)
IM3 = I0- (ΔVIN / RRSS)… (6)
Given in. Here, as can be seen from the equations (5) and (6), the current IM2 and the current IM3 are complementary to the current I0 (first reference current).

  From the above, when the differential input signals VIN and VREF are input, the VI conversion unit C1 generates currents IM2 and IM3 according to the input voltage ΔVIN (= VIN−VRE). That is, it operates so as to convert the input voltage ΔVIN into currents IM2 and IM3.

  Next, the configuration of the current distribution unit C2 will be described. FIG. 3 is a circuit diagram showing a configuration of the current distribution unit C2. The source of the PMOS transistor M5 is connected to the power supply voltage VDD. The drain of the PMOS transistor M5 is connected to one ends of the switch S1 and the switch S1B. The other end of the switch S1 is connected to the output PN. The other end of the switch S1B is connected to the output PP.

  The source of the PMOS transistor M6 is connected to the power supply voltage VDD. The drain of the PMOS transistor M6 is connected to one ends of the switch S2 and the switch S2B. The other end of the switch S2 is connected to the output PN. The other end of the switch S2B is connected to the output PP.

  The source of the PMOS transistor M7 is connected to the power supply voltage VDD. The drain of the PMOS transistor M7 is connected to one ends of the switch S3 and the switch S3B. The other end of the switch S3 is connected to the output PN. The other end of the switch S3B is connected to the output PP. The source of the PMOS transistor M8 is connected to the power supply voltage VDD. The drain of the PMOS transistor M8 is connected to the output PP. The gates of the PMOS transistors M5 to M8 are connected to the output P of the VI conversion unit C1.

  The switches S1 to S3 and the switches S1B to S3B are switches composed of transistors, and the switches S1 and S1B, the switches S2 and S2B, and the switches S3 and S3B operate so that ON / OFF contradicts. For example, when the switch S1 is ON, the switch S1B is OFF, and when the switch S1 is OFF, the switch S1B is ON. Moreover, ON / OFF of these switches is controlled by a control device (not shown).

  Next, the operation of the current distribution unit C2 will be described. The gates of the PMOS transistors M5 to M8 are connected to the gate of the PMOS transistor M2 of the VI conversion unit C1, and the applied gate voltage is the same as the gate voltage of the PMOS transistor M2. Further, the sources of the PMOS transistors M5 to M8 are connected to the power supply voltage VDD similarly to the PMOS transistor M2. That is, the PMOS transistors M5 to M8 have the same applied gate voltage, source voltage, and gate length as the PMOS transistor M2 (FIG. 2) of the VI conversion unit C1.

  Further, assuming that the gate widths of the PMOS transistors M5 to M8 are WM5, WM6, WM7, and WM8, respectively, the gate width WM2 of the PMOS transistor M2 is α times, 2α times, 4α times, and 7α times.

  From the above, the PMOS transistors M5 to M8 constituting the current distribution unit C2 constitute a current mirror circuit with the PMOS transistor M2 of the VI conversion unit C1.

  Therefore, for example, the current flowing through the PMOS transistor M5 is given by αIM2 considering that the gate width WM5 is α times the gate width WM2 of the PMOS transistor M2. Similarly, currents flowing through the PMOS transistors M6, M7, and M8 are given by 2αIM2, 4αIM2, and 7αIM2, respectively.

As a result, the current IPP (first distribution current) flowing through the output PP and the current IPN (second distribution current) flowing through the output PN are determined by the combination of ON / OFF of the switch.
IPP = (7 + N) × αIM2 ... (7)
IPN = (7-N) × αIM2 ... (8)
Given in. Here, the setting value N is an integer of 0 to 7 determined by the combination of ON / OFF of the switch. For example, N = 1 when the switch S1B is ON and the switches S2B and S3B are OFF, and N = 2 when the switch S2B is ON and the switches S1B and S3B are OFF. When the switches S1B to S3B are OFF, N = 0. In the example of FIG. 3, since all the switches S1B to S1B are ON, this corresponds to the state of N = 7.

  As described above, the PMOS transistors M5 to M8 of the current distribution unit C2 constitute a current mirror circuit with the PMOS transistor M2 of the VI conversion unit C1. Therefore, a current obtained by multiplying the current IM2 generated by the VI conversion unit C1 by a constant according to the gate width flows through the PMOS transistors M5 to M8.

  Then, these currents are distributed and output to the currents IPP and IPN by the combination of ON / OFF of the switches. That is, the current distribution unit C2 includes a current mirror circuit that uses the current IM2 of the VI conversion unit C1 as a reference current, distributes the output current of the current mirror circuit according to the set value N, and outputs the currents IPP and IPN. is doing.

  Next, the configuration of the current distribution unit C3 will be described. FIG. 3 is a circuit diagram showing a configuration of the current distribution unit C3. The source of the PMOS transistor M9 is connected to the power supply voltage VDD. The drain of the PMOS transistor M9 is connected to one ends of the switch S4 and the switch S4B. The other end of the switch S4 is connected to the output NN. The other end of the switch S4B is connected to the output NP.

  The source of the PMOS transistor M10 is connected to the power supply voltage VDD. The drain of the PMOS transistor M10 is connected to one ends of the switch S5 and the switch S5B. The other end of the switch S5 is connected to the output NN. The other end of the switch S5B is connected to the output NP.

  The source of the PMOS transistor M11 is connected to the power supply voltage VDD. The drain of the PMOS transistor M11 is connected to one ends of the switch S6 and the switch S6B. The other end of the switch S6 is connected to the output NN. The other end of the switch S6B is connected to the output NP.

  The source of the PMOS transistor M12 is connected to the power supply voltage VDD. The drain of the PMOS transistor M12 is connected to the output NP. The gates of the PMOS transistors M9 to M12 are connected to the output N of the VI conversion unit C1.

  The current distribution unit C3 operates to replicate the current IM3 generated by the current-voltage conversion unit C1, and distribute and output the current IMP and INN determined by the ON / OFF combination of the switches.

  That is, the current distribution unit 3 includes a current mirror circuit that uses the current IM3 of the VI conversion unit C1 as a reference current, distributes the output current of the current mirror circuit according to the set value N, and outputs currents INP and INN. is doing.

The current INP (third distribution current) and the current INN (fourth distribution current) are
INP = (7 + N) × αIM3… (9)
INN = (7-N) × αIM3… (10)
Given in.

  Since the operation of the current distribution unit C3 is the same as that of the current distribution unit C2, detailed description thereof is omitted.

  The operation of the variable gain amplifier configured as described above will be described. When the differential input signals VIN and VREF are input to the V-I converter C1, the V-I converter C1 generates currents IM2 and IM3 according to the input voltage ΔVIN = VIN-VREF (Equation (5), (See (6)). Then, an output P corresponding to the current IM2 is output to the current distributor C2. In addition, an output N corresponding to the current IM3 is output to the current distributor C3.

  When the current IM2 is generated by the VI conversion unit C1, the current distribution unit C2 receives the output P and outputs currents IPP and IPN (expressions (7) and (8)) corresponding to the state of the switch element. Similarly, when the current IM3 is generated by the VI conversion unit C1, the current distribution unit C3 receives the output N and generates currents INP and INN (expressions (9) and (10)) according to the state of the switch element. Output.

The output PP and the output NN are joined and connected to the output terminal OUTP, and the output PN and the output NP are joined and connected to the output terminal OUTN. Therefore, if the currents flowing in the direction of the output terminals OUTP and OUTN are IOUTP (first amplified current) and IOUTN (second amplified current),
IOUTP = IPP + INN… (11)
IOUTN = IPN + INP… (12)
And given by equations (5)-(10)
IOUTP = 14αI0 + (2αN / RRSS) ΔVIN… (13)
IOUTN = 14αI0- (2αN / RRSS) ΔVIN… (14)
It becomes.

  Here, as shown in the equations (13) and (14), the current IOUTP and the current IOUTN have a complementary relationship with the second reference current (14α · I0), which is a portion that does not depend on the set value N. It has become.

When the resistance values of the resistors R1 and R2 are R0, the output voltages VOUTP and VOUTN of the output terminals OUTP and OUTN are
VOUTP = 14αI0 ・ R0 + (2αN ・ R0 / RRSS) ΔVIN… (15)
VOUTN = 14αI0 ・ R0- (2αN ・ R0 / RRSS) ΔVIN… (16)
It becomes.

  Here, among the currents IPP, IPN, INP, and INN, the currents IPP and IPN, the currents INP and the currents INN are combined to form the currents IOUTP and IOUTN so that the portion including the current I0 does not depend on the set value N. ing. As a result, the output voltages VOUTP and VOUTN include a common portion (14αR0 · I0) that does not depend on the set value N, and this portion can be used as a reference potential.

  Since it is configured as described above, the variable gain amplifier according to the present embodiment amplifies and outputs the input voltage ΔVIN with a gain (αNR0 / RRSS). This gain (2αN · R0 / RRSS) is determined by the current mirror ratio α (= WM5 / WM2), the switch setting value N, the resistance value R0 of the linear resistance, and RRSS, and therefore does not depend on the input voltage ΔVIN.

  Therefore, it is possible to obtain a variable gain amplifier whose gain does not vary with the input voltage ΔVIN.

  Further, by combining the current IPP and the current IPN, and the current INP and the current INN, it is possible to set an output common potential (the center value of the output: 14αR0 · I0) that does not depend on the set value N. An output of (2αN · R0 / RRSS) ΔVIN can be obtained in the positive and negative directions around the potential.

1 is a circuit diagram showing a configuration of a variable gain amplifier according to a first embodiment. FIG. 3 is a circuit diagram showing a configuration of a VI conversion unit according to the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a current distribution unit according to the first embodiment. FIG. 3 is a circuit diagram illustrating a configuration of a current distribution unit according to the first embodiment.

Explanation of symbols

C1 V-I converter, C2, C3 Current distribution unit.

Claims (3)

A variable gain amplifier that amplifies and outputs an input voltage with a gain according to a desired set value,
A voltage-current converter that converts the input voltage into an output current corresponding to the input voltage;
A current amplifying unit that amplifies and outputs the output current of the voltage-current converter to a current according to the desired set value;
A resistor for converting the output current of the current amplification unit into a voltage;
A variable gain amplifier comprising:   The current amplification unit includes a current mirror circuit using the output current of the voltage-current conversion unit as a reference current, and generates an output current by distributing the output current of the current mirror circuit according to the desired set value The variable gain amplifier according to claim 1. The output current of the voltage-current converter includes a first output current complementary to a predetermined first reference current, and a second output current,
The current amplifying unit distributes an output current of the current mirror circuit using the first output current as a reference current to a first distribution current and a second distribution current according to the desired set value, and outputs the first distribution current and the second distribution current. A current distribution unit;
A third distribution current according to the desired set value, and a second current distribution unit for distributing and outputting the output current of the current mirror circuit using the second output current as a reference current according to the desired set value. ,
A first amplification current and a second amplification complementary to a predetermined second reference current by adding the first distribution current and the fourth distribution current and adding the second distribution current and the third distribution current. Output current,
3. The variable gain amplifier according to claim 2, wherein the resistor includes a first resistor and a second resistor that convert the first amplified current and the second amplified current into voltages, respectively.

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