JP2006032562A - Capacitive element, its forming method, semiconductor memory device, and its manufacture - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitive element comprising a capacitance insulating film of ferroelectric material in which polarizing characteristics of the capacitance insulating film is suppressed from degrading even if the capacitance insulating film is reduced in thickness. <P>SOLUTION: A capacitive element 25a has a lower electrode 18a, a capacitance insulating film 19a of ferroelectric substance, and an upper electrode 20a formed in this order. The part of at least one of the upper electrode 20a and the lower electrode 18a that contacts the capacitance insulating film 19a is a conductor of noble metal oxide. The noble metal oxide has such composition as that of less oxygen than stoichiometry composition. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a capacitive element provided with a capacitive insulating film made of a ferroelectric material, a method for forming the same, a semiconductor memory device including the capacitive element provided with a capacitive insulating film made of a ferroelectric material, and a method for manufacturing the same.

  Development of a ferroelectric memory composed of a capacitive element having a capacitive insulating film made of a ferroelectric material, which constitutes a semiconductor memory device, has started to be mass-produced with a small capacity of 1 to 64 kbit using a planar structure, Recently, a large capacity of 256 kbit to 4 Mbit using a stack type structure has become the center of development. In order to realize a ferroelectric memory having a stacked structure, it is indispensable to increase the degree of integration, that is, miniaturization, and a process of forming a ferroelectric film constituting a capacitive insulating film and a process of forming a transistor It is important to match with the process of forming the wiring. In the conventional technique, in order to compensate for the deviation of the composition of the ferroelectric film from the stoichiometric composition due to the diffusion of the metal elements constituting the ferroelectric film from the ferroelectric film into the electrode. It has been proposed that a metal element constituting a ferroelectric film is contained in an electrode. By doing so, the diffusion of elements from the ferroelectric film prevents deterioration of the polarization characteristics of the ferroelectric film, and a highly integrated ferroelectric memory is realized (for example, Patent Document 1). .

  Hereinafter, an example in which the configuration disclosed in Patent Document 1 is applied to the structure of the capacitive element in the ferroelectric memory will be described with reference to FIG.

  FIG. 17 is a cross-sectional view of the main part showing the structure of the capacitive element when the configuration disclosed in Patent Document 1 is applied to the structure of the capacitive element in the ferroelectric memory.

  As shown in FIG. 17, a memory cell transistor (not shown) is formed on a semiconductor substrate 101, and a first interlayer insulating film 102 is formed so as to cover the memory cell transistor. A first contact plug 103 is formed in the first interlayer insulating film 102 so as to be connected to the memory cell transistor. A lower electrode 104 whose lower surface is connected to the upper end of the first interlayer insulating film 102 is formed on the first interlayer insulating film 102. A capacitive insulating film 105 made of a ferroelectric film is formed on the lower electrode 104, and an upper electrode 106 is formed on the capacitive insulating film 105. Thus, the capacitor element 107 including the lower electrode 104, the capacitor insulating film 105, and the upper electrode 106 is formed. Further, a second interlayer insulating film 108 is formed on the first interlayer insulating film 102 so as to cover the capacitor element 107, and the lower end of the second interlayer insulating film 108 has the upper electrode 106. A second contact plug 109 connected to the upper surface of the first contact plug 109 is formed. A wiring 110 whose lower surface is electrically connected to the upper end of the second contact plug 109 is formed on the second interlayer insulating film 108.

In the capacitive element 107 having such a structure, the lower electrode 104 or the upper electrode 106 contains at least one of the elements constituting the capacitive insulating film 105, whereby the stronger constituting the capacitive insulating film 105 is formed. Even when a heat treatment for crystallizing the dielectric film is performed, the constituent elements of the ferroelectric film are prevented from diffusing into the lower electrode 104 or the upper electrode 106. In this way, deterioration of the polarization characteristics of the ferroelectric film is prevented.
JP 11-330357 A

  However, in the case of the above-described conventional example, it is necessary to contain the constituent elements of the ferroelectric film in the lower electrode or the upper electrode, so that there is a problem that the process of forming these electrodes becomes complicated. Specifically, in order to form the lower electrode or the upper electrode by sputtering, a new sputtering target must be prepared. Further, even when the lower electrode or the upper electrode is formed by the CVD method, precise composition control is required to add a raw material and obtain a desired composition. It is difficult to ensure the stability of the composition control, and even if it can be expected to have a uniform effect on the deterioration of the polarization characteristics of the ferroelectric film, it completely suppresses the deterioration of the polarization characteristics of the ferroelectric film. We have not yet reached the stage where we can do it.

  In view of the above, an object of the present invention is to suppress the deterioration of the polarization characteristics of the capacitive insulating film even when the capacitive insulating film is thinned in the capacitive element having the capacitive insulating film made of a ferroelectric material. And a method of manufacturing the same, and a semiconductor memory device including the capacitor and a method of manufacturing the same.

  In order to solve the above-described problem, a first capacitive element according to the present invention is a capacitive element in which a lower electrode, a capacitive insulating film made of a ferroelectric, and an upper electrode are formed in this order. And the portion in contact with the capacitive insulating film in at least one of the lower electrodes is a conductor made of a noble metal oxide, and the noble metal oxide has a composition with less oxygen than the stoichiometric composition. It is characterized by being.

  According to the first capacitive element of the present invention, the portion in contact with the capacitive insulating film in at least one of the upper electrode and the lower electrode is a conductor made of a noble metal oxide, and the composition of the noble metal oxide is The composition has less oxygen than the stoichiometric composition, and oxygen is easily released from the oxide of the noble metal. For this reason, it is possible to prevent oxygen from diffusing from the capacitive insulating film made of the ferroelectric material to the lower electrode or the upper electrode in the heat treatment step after forming the capacitive insulating film. Therefore, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film.

  In the first capacitor element according to the present invention, the noble metal oxide preferably has oxygen as a constituent element desorbed from the noble metal oxide at 600 ° C. or higher.

  In this case, oxygen is easily released from the noble metal oxide in a heat treatment step of 600 ° C. or higher performed after the capacitor insulating film is formed.

  In the first capacitive element according to the present invention, the noble metal is preferably made of one or more kinds of metals selected from Ir, Ru, Rh, Pd and Os.

  In this case, oxygen is easily released from the oxide of the noble metal in a heat treatment step at 600 ° C. or higher.

  In order to solve the above-described problem, a second capacitive element according to the present invention is a capacitive element in which a lower electrode, a capacitive insulating film made of a ferroelectric, and an upper electrode are formed in this order. The film is characterized by comprising a bismuth layered perovskite having a composition having more bismuth than the stoichiometric composition.

  According to the second capacitive element of the present invention, the capacitive insulating film is made of a bismuth layered perovskite having a composition with more bismuth than the stoichiometric composition. In the heat treatment process after forming the ferroelectric film, even if the volatile bismuth constituting the ferroelectric film diffuses to the lower electrode or the upper electrode, the bismuth constituting the ferroelectric film decreases. Since the ferroelectric film contains more bismuth than the stoichiometric composition, the amount of bismuth in the capacitive insulating film after the heat treatment step is maintained at an appropriate value. Therefore, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film.

  In order to solve the above problems, a third capacitive element according to the present invention is a capacitive element in which a lower electrode, a capacitive insulating film made of a ferroelectric, and an upper electrode are formed in this order, and the capacitive insulating The dielectric constant of a region in the vicinity of at least one surface in contact with the lower electrode or the upper electrode in the film is higher than the dielectric constant in the region in the vicinity of the center of the capacitor insulating film in the film thickness direction.

  According to the third capacitive element of the present invention, the dielectric constant of the region in the vicinity of at least one of the surfaces in contact with the lower electrode or the upper electrode in the capacitor insulating film is the region in the center in the film thickness direction of the capacitor insulating film. In the heat treatment process after forming the ferroelectric film that becomes the capacitive insulating film in the process of forming the capacitor element, a highly volatile element such as oxygen or bismuth is present in the lower part from the ferroelectric film. Even if an interface layer is formed in the vicinity of these electrodes by diffusing to the electrode or the upper electrode, the voltage drop is suppressed. Accordingly, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric constituting the capacitive insulating film.

  In the third capacitive element according to the present invention, if at least the region in the vicinity of one surface has a film thickness of 20 nm or less, the deterioration of the polarization characteristics of the ferroelectric constituting the capacitive insulating film is effectively reduced. Can be prevented.

  In order to solve the above problems, a semiconductor memory device according to the present invention includes a transistor having a source region and a drain region formed on a substrate, and an interlayer insulating film formed on the substrate so as to cover the transistor. Any one of the first to third plug contacts formed in the interlayer insulating film so that the lower end thereof is electrically connected to the source region or the drain region and the lower surface is connected to the upper end of the plug contact. And a capacitor element.

  According to the semiconductor memory device of the present invention, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric that constitutes the capacitor element in the semiconductor memory device.

  In order to solve the above-described problems, a first method for forming a capacitive element according to the present invention includes a step of forming a lower electrode on a substrate, a step of forming a capacitive insulating film on the lower electrode, and capacitive insulation. A step of forming an upper electrode on the film, and a portion in contact with the capacitive insulating film in at least one of the lower electrode and the upper electrode is a conductor made of a noble metal oxide, and the noble metal oxidation The object is formed by heat-treating a deposited metal material film mainly composed of noble metal in an atmosphere containing oxygen.

  According to the first method for manufacturing a capacitive element according to the present invention, a portion in contact with the capacitive insulating film in at least one of the upper electrode and the lower electrode is made of a noble metal oxide having a composition with less oxygen than the stoichiometric composition. It becomes the conductor which becomes. For this reason, oxygen is easily released from the oxide of the noble metal, so that oxygen diffuses from the capacitive insulating film made of the ferroelectric material to the lower electrode or the upper electrode in the heat treatment step after forming the capacitive insulating film. Can be prevented. Therefore, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film.

  In order to solve the above-described problem, a second capacitor element forming method according to the present invention includes a step of forming a lower electrode on a substrate, a step of forming a capacitive insulating film on the lower electrode, and capacitive insulation. A step of forming an upper electrode on the film and a step of crystallizing the capacitive insulating film by performing a heat treatment. The step of forming the capacitive insulating film includes the step of The method includes a step of forming a capacitive insulating film by applying a dielectric solution containing bismuth on the lower electrode so as to have a composition having more bismuth than a metric composition.

  According to the second method for forming a capacitive element according to the present invention, in order to form a capacitive insulating film made of a bismuth layered perovskite having a composition containing more bismuth than the stoichiometric composition, In the heat treatment step after forming the ferroelectric film serving as the capacitive insulating film, the highly volatile bismuth constituting the ferroelectric film diffuses into the lower electrode or the upper electrode, and the bismuth constituting the ferroelectric film becomes Even if the amount is reduced, the ferroelectric film contains more bismuth than the stoichiometric composition, so that the amount of bismuth in the capacitive insulating film after the heat treatment step is maintained at an appropriate value. Therefore, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film.

  In order to solve the above problems, a third method for forming a capacitive element according to the present invention includes a step of forming a lower electrode on a substrate, a step of forming a capacitive insulating film on the lower electrode, and capacitive insulation. Of the step of forming the upper electrode on the film, between the step of forming the lower electrode and the step of forming the capacitive insulating film, and between the step of forming the capacitive insulating film and the step of forming the upper electrode And forming a layer having a dielectric constant higher than that of the capacitor insulating film on at least one of the above.

  According to the third method for manufacturing a capacitive element according to the present invention, the dielectric constant of the region in the vicinity of at least one of the surfaces in contact with the lower electrode or the upper electrode in the capacitive insulating film is the film thickness direction in the capacitive insulating film. Higher volatility such as oxygen or bismuth from the ferroelectric film in the heat treatment process after forming the ferroelectric film that becomes the capacitive insulating film in the process of forming the capacitive element because it is higher than the dielectric constant of the central region Even if the element diffuses into the lower electrode or the upper electrode and an interface layer in the vicinity of these electrodes is formed, the voltage drop is suppressed. Accordingly, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric constituting the capacitive insulating film.

  In the third method for forming a capacitive element according to the present invention, the capacitive insulating film is formed by applying the first dielectric solution, and the layer having a high dielectric constant is the second dielectric. The second dielectric solution is formed by applying a body solution, and the second dielectric solution is a solution composition adjusted to have a dielectric constant higher than that of the capacitive insulating film after crystallization treatment. It is preferable to have.

  In this way, a capacitor insulating film and a layer having a high dielectric constant can be easily formed.

  In the third method for forming a capacitive element according to the present invention, the capacitive insulating film and the layer having a high dielectric constant are preferably formed by vapor phase growth.

  In this way, a capacitor insulating film and a layer having a high dielectric constant can be easily formed.

  In order to solve the above problems, a method of manufacturing a semiconductor memory device according to the present invention includes a step of forming a transistor having a source region and a drain region on a substrate, and an interlayer insulation so as to cover the transistor on the substrate. A step of forming a film, a step of forming a plug contact in the interlayer insulating film so that the lower end thereof is electrically connected to the source region or the drain region, and a first surface so that the lower surface is connected to the upper end of the plug contact. A step of forming a capacitor element in which a lower electrode, a capacitor insulating film, and a lower electrode are formed in this order using the third capacitor element forming method is provided.

  According to the method for manufacturing a semiconductor memory device according to the present invention, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric that constitutes the capacitor element in the semiconductor memory device.

  According to the first capacitive element and the method of manufacturing the same according to the present invention, the portion in contact with the capacitive insulating film in at least one of the upper electrode and the lower electrode is a conductor made of a noble metal oxide, and the noble metal is oxidized. The composition of the product has a composition with less oxygen than the stoichiometric composition, and oxygen is easily released from the noble metal oxide. For this reason, it is possible to prevent oxygen from diffusing from the capacitive insulating film made of the ferroelectric material to the lower electrode or the upper electrode in the heat treatment step after forming the capacitive insulating film. Therefore, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film.

  According to the second capacitive element and the method of manufacturing the same according to the present invention, the capacitive insulating film is made of bismuth layered perovskite having a composition containing more bismuth than the stoichiometric composition. In the heat treatment step after forming the ferroelectric film serving as the capacitive insulating film, the highly volatile bismuth constituting the ferroelectric film diffuses into the lower electrode or the upper electrode, and the bismuth constituting the ferroelectric film becomes Even if the amount is reduced, the ferroelectric film contains more bismuth than the stoichiometric composition, so that the amount of bismuth in the capacitive insulating film after the heat treatment step is maintained at an appropriate value. Therefore, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric material constituting the capacitive insulating film.

  According to the third capacitive element and the method of manufacturing the same according to the present invention, the dielectric constant of the region in the vicinity of at least one of the surfaces in contact with the lower electrode or the upper electrode in the capacitive insulating film is the film thickness in the capacitive insulating film. Since the dielectric constant of the region in the center of the direction is higher, in the heat treatment step after the formation of the ferroelectric film serving as the capacitive insulating film in the step of forming the capacitive element, a volatile substance such as oxygen or bismuth is formed from the ferroelectric film. Even if a high element diffuses into the lower electrode or the upper electrode and an interface layer in the vicinity of these electrodes is formed, the voltage drop is suppressed. Accordingly, it is possible to prevent the deterioration of the polarization characteristics of the ferroelectric constituting the capacitive insulating film.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
Hereinafter, a capacitor element and a method for forming the capacitor according to the first embodiment of the present invention, a semiconductor memory device including the capacitor element, and a method for manufacturing the same will be described with reference to FIGS. This will be described with reference to 3 (a) and (b).

  FIG. 1 is a cross-sectional view of a main part showing the structure of a capacitive element and a semiconductor memory device including the capacitive element according to the first embodiment of the present invention.

  As shown in FIG. 1, an impurity diffusion layer serving as a source region or a drain region formed in a surface layer portion of the silicon substrate 11 is formed in an element formation region partitioned by an element isolation layer 12 made of a silicon oxide film in the silicon substrate 11. 13 and a gate insulating film 14a and a gate electrode 14 formed on the silicon substrate 11 are formed. A first interlayer insulating film (for example, a silicon oxide film (BPSG film) doped with phosphorus (P) or boron (B)) 15 is formed on the silicon substrate 11 so as to cover the memory cell transistors. A first hydrogen barrier film 16 made of SiN is formed on the first interlayer insulating film 15. The first interlayer insulating film 15 and the first hydrogen barrier film 16 are formed with a first contact plug 17 made of tungsten having a lower end connected to the impurity diffusion layer 13 through the first interlayer insulating film 15 and the first hydrogen barrier film 16.

  As shown in FIG. 1, a lower electrode 18 a made of iridium oxide is formed on the first hydrogen barrier film 16 with its lower surface electrically connected to the upper end of the first contact plug 17. . A capacitive insulating film 19a made of a ferroelectric (SBT (SrBiTaO) or BLT (BiLaTiO)) film is formed on the lower electrode 18a. The capacitive insulating film 19a is made of iridium oxide. An upper electrode 20a is formed. Thus, the capacitive element 21a composed of the lower electrode 18a, the capacitive insulating film 19a, and the upper electrode 20a is formed.

Further, as shown in FIG. 1, a second hydrogen barrier film 22 made of SiN is formed on the first hydrogen barrier film 16 so as to cover the capacitive element 21a, and the second hydrogen barrier film is formed. A second interlayer insulating film (for example, a silicon oxide film (O ₃ -TEOS film) 23 formed of O ₃ and TEOS) is formed so as to cover the film 22. The second interlayer insulating film 23 includes A second contact plug 24 made of tungsten that penetrates through the second interlayer insulating film 23 and the second hydrogen barrier film 22 and whose lower end is electrically connected to the upper surface of the upper electrode 20a is formed. On the interlayer insulating film 23, the lower surface is electrically connected to the upper end of the second contact plug 24, and a wiring 24 made of a laminated film of TiN / Al / TiN / Ti is formed from the upper layer.

  Here, the features of the capacitive element according to the first embodiment of the present invention having the above-described structure and the semiconductor memory device including the capacitive element will be described.

A portion of at least one of the upper electrode 20a and the lower electrode 18a that is in contact with the capacitive insulating film 19a made of a ferroelectric film has an oxygen-less (deficient) composition than the stoichiometric composition. (IrO _x : 0 <x <2).

Therefore, the capacitive element according to the first embodiment of the present invention and the semiconductor memory device including the capacitive element have the following effects. That is, the portion of the upper electrode 20a or the lower electrode 18a that is in contact with the capacitive insulating film 19a is made of iridium oxide (IrO _x : 0 <x <2) having a composition with less oxygen than the stoichiometric composition. Compared with iridium oxide (IrO ₂ ) having a stoichiometric composition, iridium (IrO _x : 0 <x <2) has a tendency to desorb oxygen, and desorption of oxygen occurs at 600 ° C. or higher. Therefore, when using a ferroelectric film made of SBT, the crystallization temperature is about 800 ° C., and when using a ferroelectric film made of BLT, the crystallization temperature is about 700 ° C. During the heat treatment for crystallization of the ferroelectric film made of BLT, oxygen from the ferroelectric film constituting the capacitive insulating film 19a is prevented from diffusing into the upper electrode 20a or the lower electrode 18a. Can do. Thereby, deterioration of the polarization characteristics of the ferroelectric film can be prevented.

  Next, FIGS. 2A to 2C and FIGS. 3A and 3B illustrate a method of forming a capacitor according to the first embodiment of the present invention and manufacture of a semiconductor memory device including the capacitor. It is principal part process sectional drawing which shows a method.

  First, as shown in FIG. 2A, in the element formation region partitioned by the element isolation layer 12 made of the silicon oxide film on the silicon substrate 11, the impurity which becomes the source region or drain region of the surface layer portion of the silicon substrate 11 A memory cell transistor composed of the diffusion layer 13, the gate insulating film 14 a on the silicon substrate 11 and the gate electrode 14 is formed. Subsequently, a first interlayer insulating film (for example, a silicon oxide film (BPSG film) doped with phosphorus (P) or boron (B)) 15 is formed on the silicon substrate 11 so as to cover the memory cell transistors. After that, a first hydrogen barrier film 16 made of SiN is formed on the first interlayer insulating film 15. Subsequently, a first contact plug 17 made of tungsten that penetrates the first interlayer insulating film 15 and the first hydrogen barrier film 16 and has a lower end connected to the impurity diffusion layer 13 is formed.

Next, as shown in FIG. 2B, the lower electrode 18 a made of iridium oxide is formed on the first hydrogen barrier film 16 so that the lower surface is electrically connected to the upper end of the first contact plug 17. Form. At this time, iridium oxide (IrO _x (0 <x <2)) is formed on the surface portion of the lower electrode 18a by sputtering in an atmosphere containing oxygen.

Next, as shown in FIG. 2 (c), after applying a ferroelectric solution made of SBT on the lower electrode 18a by a spin coating method, at a temperature at which the solvent volatilizes (150 to 300 ° C.). by performing the heat treatment, the ferroelectric a capacitor insulating film 19a after the film 19 to form the _a-1. Subsequently, pre-sintering is performed by a RTP (Rapid Thermal Processing) method to form a nucleus serving as a base point for crystal growth. Although the temperature or atmosphere for forming nuclei varies depending on the type of ferroelectric material, when the ferroelectric film 19 _a-1 is made of SBT material, temporary sintering is performed in an oxygen atmosphere at about 650 ° C. Do. The ferroelectric film 19 _a-1 may be formed by sputtering, MOCVD, laser ablation, or the like.

Next, as shown in FIG. 3A, an upper electrode 20a made of Ir is formed on the ferroelectric film _19a-1 . Subsequently, after patterning the lower electrode 18a, the ferroelectric film _19a-1 and the upper electrode 20a, the ferroelectric film _19a-1 is crystallized by heat treatment at a high temperature. A capacitive insulating film 19a made of the ferroelectric film is formed. The crystallization temperature is about 650 ° C. to 800 ° C. when the ferroelectric film 19 _a-1 is made of an SBT material. Further, in the present embodiment, the case where the heat treatment is performed immediately after the ferroelectric film 19 _a-1 is applied and after the patterning is described, but after the ferroelectric film 19 _a-1 is formed, The order of performing the heat treatment is not limited to the order of the present embodiment, and the number of heat treatments may be performed once or more. In this way, the capacitive element 21a composed of the lower electrode 18a, the capacitive insulating film 19a, and the upper electrode 20a is formed.

Next, as shown in FIG. 3B, a second hydrogen barrier film 22 made of SiN is deposited on the first hydrogen barrier film 17 so as to cover the capacitive element 25a, and then the second hydrogen barrier film 22 is deposited. The hydrogen barrier film 22 is patterned. Subsequently, a second interlayer insulating film (O ₃ -TEOS film) 23 is formed on the first hydrogen barrier film 17 so as to cover the second hydrogen barrier film 21a. Subsequently, a contact hole that reaches the upper surface of the upper electrode 20a is formed by etching in the second interlayer insulating film 23 and the second hydrogen barrier film 22, and then tungsten is buried in the contact hole so that the lower end is the upper part. A second contact plug 24 in contact with the upper surface of the electrode 20a is formed. Subsequently, on the second interlayer insulating film 23 and the second contact plug 24, TiN / Al / TiN / Al is formed from the upper layer so that the lower surface is electrically connected to the upper end of the second contact plug 24. A wiring 25 made of a laminated film is formed. In this manner, a capacitor having the structure shown in FIG. 3B and a semiconductor memory device including the capacitor are formed.

As described above, according to the method for forming a capacitor element and the method for manufacturing a semiconductor memory device including the capacitor element according to the first embodiment of the present invention, the lower electrode 18a is formed by sputtering in an atmosphere containing oxygen. The portion in contact with the capacitor insulating film 19a is iridium oxide (IrO _x (0 <x <2)). Since this iridium oxide (IrO _x (0 <x <2)) has a composition with less oxygen than the stoichiometric composition, compared with the iridium oxide (IrO ₂ ) having the stoichiometric composition, resulting in oxygen from the iridium oxide _{(IrO x (0 <x <} 2)) has become a easily eliminated state, iridium oxide _{(IrO x (0 <x <} 2)) desorption of oxygen from the 600 ° C. or higher . Therefore, in the step of crystallizing the ferroelectric film 19a _-1 by heat treatment at a high temperature, oxygen from the ferroelectric film 19a _-1 constituting the capacitive insulating film 19a diffuses into the lower electrode 18a. Can be prevented. Thereby, it is possible to prevent deterioration of the polarization characteristics of the capacitive insulating film 19a.

In this embodiment, IrO _x (0 <x <2) has been described as iridium oxide having a composition with less oxygen than the stoichiometric composition. However, more effective oxygen desorption occurs. Therefore, it is desirable to set IrO _x (1 <x <2) as iridium oxide.

  Further, in the capacitor according to the present embodiment and the method for forming the same, and the semiconductor memory device including the capacitor and the method for manufacturing the same, when the upper electrode 20a serves as a capacity defining port, that is, the upper electrode 20a is lower than the lower electrode 18a. Although the case of a small structure has been described, as shown in FIG. 4 to be described later, a structure in which the lower electrode 18a serves as a capacity defining port may be used.

  In the capacitive element and the method for forming the same according to the present embodiment, and the semiconductor memory device including the capacitive element and the method for manufacturing the same, the capacitive insulating film in the second and third embodiments described later is used as the capacitive insulating film 19a. 19b and the capacitor insulating film 19c may be applied.

(Second Embodiment)
Hereinafter, a capacitive element and a method for forming the same, a semiconductor memory device including the capacitive element, and a method for manufacturing the same according to the second embodiment of the present invention will be described with reference to FIGS. This will be described with reference to FIGS. 6 (a) and (b) and FIGS. 7 (a) and (b).

  FIG. 4 is a cross-sectional view of the main part showing the structure of the capacitor according to the second embodiment of the present invention and the semiconductor memory device including the capacitor. 4 that are the same as those shown in FIG. 1 are the same as those shown in FIG. 1, and therefore, description thereof will not be repeated. Therefore, the following description will focus on differences from the capacitive element according to the first embodiment of the present invention and the semiconductor memory device including the capacitive element.

As shown in FIG. 4, on the first hydrogen barrier film 16 and the first plug contact 17, an oxygen barrier layer (IrO ₂ / Ir / TiAlN formed in order from the upper layer) and Pt are sequentially arranged from the bottom. A lower electrode 18b having a stacked structure is formed, and a buried insulating film 26 is formed on the first hydrogen barrier film 16 so as to cover the side surface of the lower electrode 18b. Further, on the lower electrode 18b and the buried insulating film 26, a capacitive insulating film 19b made of a bismuth layered perovskite having a composition containing more bismuth than the stoichiometric composition, here, a composition containing excessive bismuth is formed. Yes. An upper electrode 20b made of Pt is formed on the capacitive insulating film 19b. In this manner, the capacitive element 21b composed of the lower electrode 18b, the capacitive insulating film 19b, and the upper electrode 20b is formed. The other structure shown in FIG. 4 is the same as the structure shown in FIG. Further, here, unlike the structure shown in FIG. 1 in the first embodiment, the structure is such that the upper electrode 20b serves as a capacity defining port, that is, the lower electrode 18b is smaller than the upper electrode 20b. However, also in this embodiment, as shown in FIG. 1, a structure in which the lower electrode 18b serves as a capacity defining port may be used.

As described above, according to the capacitive element and the semiconductor memory device including the capacitive element according to the first embodiment of the present invention, the bismuth layered perovskite constituting the capacitive insulating film 19b has a stoichiometric composition SrBi ₂ Ta. _In the heat treatment step after the formation of the ferroelectric film serving as the capacitor insulating film 19b in the step of forming the capacitor element 21b by having a composition containing bismuth (Bi) excessively with respect to ₂ O ₉ , Even if bismuth having high volatility diffuses from the ferroelectric film to the lower electrode 18b or the upper electrode 20b and the bismuth constituting the ferroelectric film decreases, the ferroelectric film contains excessive bismuth. Therefore, the amount of bismuth in the capacitive insulating film 19b after the heat treatment process is maintained at an appropriate value, and deterioration of the polarization characteristics of the ferroelectric constituting the capacitive insulating film 19b can be prevented.

  Next, FIGS. 5A to 5C, FIGS. 6A and 6B, and FIGS. 7A and 7B illustrate a method for forming a capacitive element according to the second embodiment of the present invention. FIG. 10 is a fragmentary process cross-sectional view illustrating the method of manufacturing the semiconductor memory device including the capacitor element. Of the components in FIGS. 5A to 5C, FIGS. 6A and 6B, and FIGS. 7A and 7B, FIGS. Since the parts common to the constituent parts shown in (a) and (b) are the same, the description thereof will not be repeated. Therefore, the following description will focus on differences from the method for forming a capacitive element according to the first embodiment of the present invention and the method for manufacturing a semiconductor memory device including the capacitive element.

  First, in FIG. 5A, a process similar to the process shown in FIG. 2A in the first embodiment is performed.

  Next, as shown in FIG. 5B, an oxygen barrier layer (IrO / Ir / TiAlN formed in order from the upper layer) and Pt are formed on the first hydrogen barrier film 16 and the first contact plug 17. After forming the lower electrode 18b laminated in order from the bottom, patterning is performed using a desired mask so that the first contact plug 16 is covered.

Next, as shown in FIG. 5C, a buried insulating film (for example, an O ₃ -TEOS film) is formed on the first hydrogen barrier film 16 so as to cover the lower electrode 18b, and then CMP is performed. The buried insulating film 26 as shown in FIG. 5C is formed by polishing and removing the buried insulating film existing on the lower electrode 18b to expose the surface of the lower electrode 18b. Here, the lower electrode 18b is embedded in the embedded insulating film 26, but the embedded structure is not necessarily required.

Next, as shown in FIG. 6A, a ferroelectric solution (solution composition: Sr _0.8 Bi _2.44 Ta ₂ O _x ) in which bismuth is excessively added is formed on the lower electrode 18b and the buried insulating film 26. After the application by spin coating, heat treatment is performed at a temperature at which the solvent volatilizes (150 to 300 ° C.) to form a ferroelectric film 19 _b-1 that will later become a capacitive insulating film 19 _b . Next, pre-sintering is performed by the RTP method to form a nucleus serving as a base point for crystal growth. Although the temperature or atmosphere for forming nuclei varies depending on the type of the ferroelectric material, when the ferroelectric film 19 _b-1 is made of an SBT material, it is in an oxygen atmosphere at about 650 ° C. Note that the ferroelectric film 19 _b-1 may be formed by sputtering, MOCVD, or laser ablation.

Next, as shown in FIG. 6B, after the upper electrode 20b made of Pt is formed on the ferroelectric film 19b _-1 that becomes the capacitive insulating film 19b, the buried insulating film 26, the ferroelectric substance are formed. Patterning is performed on the film _19b-1 and the upper electrode 20b. In this case, the buried insulating film 26, the ferroelectric film _19b-1 and the upper electrode 20b are patterned using the same mask, but each of them is patterned using a separate mask. Also good.

Next, as shown in FIG. 7 (a), the ferroelectric film 19b _-1 is crystallized by heat treatment at a high temperature, thereby forming a capacitive insulating film 19b made of the crystallized ferroelectric film. . The crystallization temperature is about 650 ° C. to 800 ° C. when the ferroelectric film 19 _b-1 is made of an SBT material. In the present embodiment, the case where the heat treatment is performed immediately after the application of the ferroelectric film 19 _b-1 and after the patterning shown in FIG. 6B has been described. However, the ferroelectric film 19 _b-1 is formed. After that, the order of performing the heat treatment is not limited to the order of the present embodiment, and the number of heat treatments may be one or more. In this way, the capacitive element 21b composed of the lower electrode 18b, the capacitive insulating film 19b, and the upper electrode 20b is formed.

Next, as shown in FIG. 7B, a second hydrogen barrier film 22 made of SiN is formed so as to cover the buried insulating film 26, the lower electrode 18b, the capacitive insulating film 19b, and the upper electrode 20b. Subsequently, after patterning the second hydrogen barrier film 22, a second interlayer insulating film (O ₃ -TEOS film) 23 is formed so as to cover the second hydrogen barrier film 22. Subsequently, a contact hole reaching the upper surface of the upper electrode 20b is formed in the second interlayer insulating film 23 and the second hydrogen barrier film 22 by etching, and then tungsten is buried in the contact hole so that the lower end is the upper part. A second contact plug 24 in contact with the upper surface of the electrode 20b is formed. Subsequently, on the second interlayer insulating film 23 and the second contact plug 24, TiN / Al / TiN / Ti is formed from the upper layer so that the lower surface is electrically connected to the upper end of the second contact plug 24. A wiring 25 made of a laminated film is formed. In this manner, a capacitor having the structure shown in FIG. 7B and a semiconductor memory device including the capacitor are formed.

As described above, according to the method for forming the capacitor element and the method for manufacturing the semiconductor memory device including the capacitor element according to the second embodiment of the present invention, the method for forming the ferroelectric film 19 _b-1 includes bismuth. Is added to the ferroelectric solution (Sr0.8Bi2.44Ta2, ferroelectric film 19b _-1, bismuth having high volatility diffuses into the lower electrode 18b or the upper electrode 20b, and the ferroelectric film _{19b- Even} if the bismuth constituting ₁ is reduced, the ferroelectric film 19 _b-1 contains excessive bismuth, so that the amount of bismuth in the capacitive insulating film 19 b after the heat treatment step is set to an appropriate value. This prevents the deterioration of the polarization characteristics of the ferroelectric that constitutes the capacitive insulating film 19b.

In the present embodiment, as excess bismuth contained in the ferroelectric film _{Sr y Bi z Ta 2 O x} , in the range (2.2 <Z <2.6) which attained the characteristic improvement of the ferroelectric It is desirable.

In the present embodiment, IrO _x (0 <x <2) may be formed in the portion of the lower electrode 18b or the upper electrode 20b that is in contact with the capacitive insulating film 19b, as in the first embodiment.

(Third embodiment)
A capacitor element and a method for forming the capacitor element according to the third embodiment of the present invention, and a semiconductor memory device including the capacitor element and a method for manufacturing the capacitor element will be described below with reference to FIGS. 8, 9A and 9B, FIG. Description will be made with reference to FIGS. 10 (a) and 10 (b), FIGS. 11 (a) and 11 (b), and FIG.

  FIG. 8 is a fragmentary cross-sectional view showing the structure of a capacitive element and a semiconductor memory device including the capacitive element according to the third embodiment of the present invention. 8 that are the same as those shown in FIG. 4 are the same as those shown in FIG. 8, and therefore description thereof will not be repeated. Therefore, the following description will focus on differences from the capacitive element according to the second embodiment of the present invention and the semiconductor memory device including the capacitive element.

  As shown in FIG. 8, the capacitive insulating film 19c formed on the lower electrode 18b and the buried insulating film 26 includes a region 27a adjacent to the lower electrode 18b and a central portion in the film thickness direction of the capacitive insulating film 19c. The dielectric constant of the region 27a is higher than that of the region 27b. The capacitive insulating film 19c is made of ferroelectric (SBT), and the bismuth composition ratio in the region 27a is larger than the bismuth composition ratio in the region 27b. Further, the bismuth composition ratio in the SBT constituting the capacitive insulating film 19c gradually increases from the side where the upper electrode 20b is formed toward the side where the lower electrode 18b is formed.

  Here, FIGS. 9A and 9B are enlarged cross-sectional views showing an example in which the capacitive element 21c composed of the lower electrode 18b, the capacitive insulating film 19c, and the upper electrode 20b is modified.

First, as shown in FIG. 9 (a), the dielectric constant of the region 27d adjacent to the upper electrode 20b of the capacitor insulating film 19 _c-1, a region including a central portion of the thickness direction of the capacitor insulating film 19 _c-1 It may be higher than the dielectric constant of 27c. In this case, the bismuth composition ratio in the SBT constituting the capacitive insulating film 19 _c-1 gradually decreases from the side where the upper electrode 20b exists toward the side where the lower electrode 18b exists. .

Further, as shown in FIG. 9 (b), the dielectric constant of the region 27e adjacent to the lower electrode 18b of the capacitor insulating film 19 _c-2, a region including a central portion of the thickness direction of the capacitor insulating film 19 _c-2 The dielectric constant of the region 27g adjacent to the upper electrode 20b in the capacitive insulating film _19c-2 is set to be higher than the dielectric constant of 27f, and the dielectric constant of the region 27f including the central portion in the film thickness direction of the capacitive insulating film _19c-2 . It may be higher than the dielectric constant. In this case, the bismuth composition ratio in the SBT constituting the capacitive insulating film _19c-2 gradually decreases from the side where the upper electrode 20b is present toward the side where the lower electrode 18b is present. It is gradually increasing from.

As described above, according to the capacitor element and the semiconductor memory device including the capacitor element according to the third embodiment of the present invention, the regions (27a, 27d, 27b, 27d, 27b, 27b) adjacent to at least one of the lower electrode 18b and the upper electrode 20b. The dielectric constant of 27e or 27g) is higher than the dielectric constant of the region (27b, 27c, or 27f) including the central portion of the capacitive insulating film (19c, 19c _-1 or 19c _-2 ). Therefore, in the step of forming a capacitor element 21c, in the heat treatment step after the formation of the ferroelectric film serving as the capacitor insulating film (19c, 19 _c-1 or 19 _c-2), the capacitor insulating film (19c, 19 _{c -1} or 19 _c-2 ), even if a highly volatile element such as oxygen or bismuth diffuses into the lower electrode 18b or the upper electrode 20b to form an electrode interface layer, the voltage drop is suppressed, so capacitive insulation It is possible to prevent the deterioration of the polarization characteristics of the ferroelectric constituting the film (19c, 19c _-1 or 19c _-2 ). Further, the bismuth composition ratio of SBT constituting the capacitive insulating film (19c, 19c _-1 or 19c _-2 ) is from the side where the upper electrode 20b is formed toward the side where the lower electrode 18b is formed. Since it gradually increases (in the case of FIG. 8), gradually decreases (in the case of FIG. 9 (a)), or gradually decreases and gradually increases (in the case of FIG. 9 (b)), the lower electrode 18b Alternatively, it is possible to prevent an adverse effect such as deterioration in pressure resistance or increase in leakage current due to the concentration of electric charges near the upper electrode 20b.

  The thickness of the regions 27a and 27e adjacent to the lower electrode 18b or the regions 27d and 27g adjacent to the upper electrode 20b can sufficiently exhibit their functions as long as it is 20 nm or less. It is good also as follows.

  Next, FIGS. 10A and 10B, FIGS. 11A and 11B, and FIG. 12 include a method for forming a capacitor according to the third embodiment of the present invention, and the capacitor. It is principal part process sectional drawing which shows the manufacturing method of a semiconductor memory device. Of the components in FIGS. 10A and 10B, FIGS. 11A and 11B, and FIG. 12, FIGS. 5A to 5C, FIGS. Since the parts common to the constituent parts shown in b) and FIGS. 7A and 7B are the same, the description thereof will not be repeated. Therefore, the following description will focus on differences from the method for forming a capacitive element according to the second embodiment of the present invention and the method for manufacturing a semiconductor memory device including the capacitive element.

  First, the process shown in FIG. 10A is performed in the same manner as described with reference to FIGS. 5A to 5C.

Next, as shown in FIG. 10B, a first ferroelectric solution (SBT solution) in which bismuth is added excessively is applied on the lower electrode 18b and the buried insulating film 26 by spin coating. After that, by performing a heat treatment at a temperature at which the solvent volatilizes (150 to 300 ° C.), the ferroelectric film 27 _a-1 to which bismuth that will later become the region 27 a in the capacitive insulating film 19 c is excessively added is formed. . Next, _a second ferroelectric solution (SBT solution) having a bismuth content lower than that of the first ferroelectric solution is applied on the ferroelectric film 27 _a-1 by spin coating. Then, by performing a heat treatment at a temperature at which the solvent volatilizes (150 to 300 ° C.), _a ferroelectric film that later becomes a region 27b in the capacitive insulating film 19c and has a bismuth content lower than that of the ferroelectric film _27a-1. 27 _b-1 is formed. The average composition of the first ferroelectric solution and the second ferroelectric solution is Sr _0.8 Bi _2.44 Ta ₂ O _x . Next, pre-sintering is performed by the RTP method to form a nucleus serving as a base point for crystal growth. The temperature or atmosphere at which the nucleus is formed differs depending on the type of the ferroelectric material, but when it is made of the SBT material constituting the ferroelectric film 27 _a-1 and the ferroelectric film 27 _b-1 , it is about 650 ° C. In an oxygen atmosphere. The formation of the ferroelectric film 27 _a-1 and the ferroelectric film 27 _b-1 may be performed by a sputtering method, an MOCVD method, or a laser ablation method.

Next, as shown in FIG. 11A, after the upper electrode 20b made of Pt is formed on the ferroelectric film _27b-1 constituting a part of the capacitive insulating film 19c, the buried insulating film 26 is formed. Then, the ferroelectric film 27 _a-1 , the ferroelectric film 27 _b-1, and the upper electrode 20 b are patterned. Here, the buried insulating film 26, the ferroelectric film _27a-1 , the ferroelectric film _27b-1 and the upper electrode 20b are patterned using the same mask. Alternatively, patterning may be performed using separate masks.

Next, as shown in FIG. 11B, the ferroelectric film 27 _a-1 and the ferroelectric film 27 _b-1 are crystallized by heat treatment at a high temperature, thereby crystallizing the ferroelectric film. A capacitive insulating film 19c is formed. The capacitive insulating film 19c has a region 27a adjacent to the lower electrode 18b and a region 27b other than the region 27a. The crystallization temperature is about 650 ° C. to 800 ° C. when the ferroelectric film 27 _a-1 and the ferroelectric film 27 _b-1 are made of an SBT material. In the present embodiment, the case where the heat treatment is performed immediately after the application of the ferroelectric film 27 _a-1 and the ferroelectric film 27 _b-1 and after the patterning of FIG. 11A has been described. After the formation of the body film 27 _a-1 and the ferroelectric film 27 _b-1 , the heat treatment order is not limited to the order of this embodiment, and the number of heat treatments may be one or more. In this manner, a capacitive element 21c composed of the lower electrode 18b, the capacitive insulating film 19c, and the upper electrode 20c is formed.

Next, as shown in FIG. 12, a second hydrogen barrier film 22 made of SiN is formed so as to cover the buried insulating film 26, the lower electrode 18b, the capacitive insulating film 19c, and the upper electrode 20b. Subsequently, after patterning the second hydrogen barrier film 22, a second interlayer insulating film (O ₃ -TEOS film) 23 is formed so as to cover the second hydrogen barrier film 22. Subsequently, a contact hole reaching the upper surface of the upper electrode 20b is formed in the second interlayer insulating film 23 and the second hydrogen barrier film 22 by etching, and then tungsten is buried in the contact hole so that the lower end is the upper part. A second contact plug 24 made of tungsten in contact with the upper surface of the electrode 20b is formed. Subsequently, a wiring 25 made of a laminated film of TiN / Al / TiN / Ti is formed on the second interlayer insulating film 23 and the second contact plug 24 from the upper layer. In this manner, a capacitor having the structure shown in FIG. 12 and a semiconductor memory device including the capacitor are formed.

  In order to realize the structure shown in FIG. 9A, the first ferroelectric solution is first applied after the second ferroelectric solution is first applied in the step shown in FIG. 10B. May be applied. Further, in order to realize the structure shown in FIG. 9B, the first ferroelectric solution is further added after applying the second ferroelectric solution in the step shown in FIG. 10B. What is necessary is just to apply.

As described above, according to the method for forming a capacitor element and the method for manufacturing a semiconductor memory device including the capacitor element according to the third embodiment of the present invention, bismuth is excessively added on the lower electrode 18b. on the ferroelectric film 27 _a-1, since the forming the ferroelectric film 27 strength is less bismuth content than _a-1 dielectric film 27 _b-1, the lower electrode 18b is formed The bismuth content in the ferroelectric film 27 _a-1 and the ferroelectric film 27 _{b-1 with} respect to the distance from the side toward the upper electrode 20 _b is as shown by the solid line in FIG. Then, by the heat treatment in FIG. 11B, the bismuth composition ratio in the capacitive insulating film 21c is as shown by the broken line in FIG.

That is, the bismuth composition ratio of SBT constituting the capacitive insulating film 19c gradually increases from the side where the upper electrode 20b is formed toward the side where the lower electrode 18b is formed. Therefore, the dielectric constant of the capacitive insulating film 19c with respect to the distance from the side where the lower electrode 18b is formed to the side where the upper electrode 20b is formed is as shown by the solid line in FIG. The dielectric constant of the region 27a adjacent to the lower electrode 18b in the capacitive insulating film 19c is higher than the dielectric constant of the region 27b including the center of the capacitive insulating film 19c. Accordingly, the ferroelectric film 27 _a-1 and the ferroelectric film 27 _b-1 heat treatment step after forming the forming the capacitor insulating film 19c (FIG. 11 (b)), oxygen or bismuth from the capacitor insulating film 19c Even when a highly volatile element such as diffusing into the lower electrode 18b is formed and the electrode interface layer is formed, the voltage drop is suppressed, so that deterioration of the polarization characteristics of the ferroelectric constituting the capacitive insulating film 19c is prevented. be able to. Further, the bismuth composition ratio of the SBT constituting the capacitive insulating film 19c gradually increases from the side where the upper electrode 20b is formed toward the side where the lower electrode 18b is formed, so that the lower electrode 18b It is also possible to prevent adverse effects such as deterioration of pressure resistance or increase in leakage current due to concentration of charges in the vicinity of. The effect of preventing the deterioration of the polarization characteristics of the ferroelectric and the effect of preventing the adverse effect such as the deterioration of the pressure resistance or the increase of the leakage current are shown in FIG. 9A or FIG. 9B. Even when the above structure is formed, the same structure can be obtained for the lower electrode 18b or the upper electrode 20b.

  In this embodiment, the dielectric constant of the region 27a is 380, and the dielectric constant of the region 27c is 320. However, the dielectric constant of the region 27a is set to a range in which the ferroelectric characteristics can be improved. The dielectric constant of 27c is preferably 1.1 times or more and 2.5 times or less.

In this embodiment, IrO _x (0 <x <2) is formed in the portion of the lower electrode 18b or the upper electrode 20b that is in contact with the capacitive insulating film 19c, as in the first embodiment. Also good.

Example 1
A capacitor element and a method for forming the capacitor according to the first embodiment of the present invention, and a semiconductor memory device including the capacitor element and a method for manufacturing the capacitor element will be described below with reference to FIGS. 1, 2A to 2C, and FIG. ) And (b) and FIG.

  Example 1 of the present invention has a configuration in which the second embodiment is combined with the first embodiment.

  First, the principal part sectional view showing the structure of the capacitive element according to the first embodiment of the present invention and the semiconductor memory device including the capacitive element is the same as FIG.

In the present embodiment, the portion of the lower electrode 18b in contact with the capacitive insulating film 19a has iridium oxide (IrO _x : 0 <x <2) having a composition with less oxygen (deficient) than the stoichiometric composition. In addition to the above, in particular, the ferroelectric (SBT) constituting the capacitive insulating film 19a is a bismuth layered perovskite, and the bismuth composition ratio is a composition in which bismuth is more excessive than stoichiometry. It is.

  Next, main part process sectional views showing the method for forming a capacitor element and the method for manufacturing a semiconductor memory device including the capacitor element according to the first embodiment of the present invention are shown in FIGS. Same as a) and (b).

In the present embodiment, in particular, in the step of forming the lower electrode 18a shown in FIG. 2B, IrO _x is formed on the surface portion of the lower electrode 18a by sputtering in an atmosphere having an oxygen partial pressure of 10%. (0 <x <2) is formed. Thereafter, as post-processing, heat treatment is performed at 650 ° C. for 1 minute by the RTP method.

Next, in the formation process of the ferroelectric film 19 _a-1 shown in FIG. 2C, _a ferroelectric solution (solution composition: Sr _0.8 Bi _2.54 Ta ₂ O _x ) to which bismuth is added excessively is spun. After coating by the coating method, the ferroelectric film 19 _a-1 (Sr _0.8 Bi _2.24 Ta ₂ O to be the capacitive insulating film 19a later) is formed by performing heat treatment at a temperature at which the solvent volatilizes (150 to 300 ° C.). _x ).

  The effects of the capacitive element according to this example will be described below.

FIG. 14 shows the film thickness and polarization amount (spontaneous polarization amount 2Pr and polarization amount Pnv of its non-volatile component) or relaxation rate ((2Pr−Pnv)) of the capacitive insulating film for the capacitive element according to this example (the present invention). / 2Pr). In FIG. 14, for comparison with the capacitive element according to the present embodiment, a capacitive element (conventional example) formed using a ferroelectric solution (solution composition: Sr _0.8 Bi ₂ Ta ₂ O _x ). ) Is also shown.

  As is clear from FIG. 14, in the capacitive element according to this example, the polarization amounts 2Pr and Pnv are not changed and the relaxation rate is increased even in the region where the thickness of the capacitive insulating film is thin compared to the conventional example. It can be seen that there is almost no deterioration.

(Example 2)
Hereinafter, a capacitor according to Example 2 of the present invention, a method for forming the capacitor, a semiconductor memory device including the capacitor, and a method for manufacturing the same will be described with reference to FIGS.

  Example 2 of the present invention has a configuration in which the third embodiment is combined with the first embodiment.

  FIG. 15 is a cross-sectional view of a main part of a capacitor according to Embodiment 2 of the present invention and a semiconductor memory device including the capacitor.

  As shown in FIG. 15, in the element formation region partitioned by the element isolation layer 32 made of a silicon oxide film in the silicon substrate 31, an impurity diffusion layer serving as a source region or a drain region formed in the surface layer portion of the silicon substrate 31. A memory cell transistor including the gate insulating film 34 a and the gate electrode 34 formed on the silicon substrate 31 is formed. A first interlayer insulating film (for example, a silicon oxide film (BPSG film) doped with phosphorus (P) or boron (B)) 35 is formed on the silicon substrate 31 so as to cover the memory cell transistors. Yes. In the first interlayer insulating film 35, a contact plug 36 made of tungsten that penetrates the first interlayer insulating film 35 and has a lower end connected to the impurity diffusion layer 33 is formed.

Further, as shown in FIG. 15, on the first interlayer insulating film 35, the second interlayer insulating film (e.g., O ₃ and silicon oxide film formed by TEOS having a recess (O ₃ -TEOS film) 37. A lower part made of iridium oxide whose lower surface is electrically connected to the upper end of the first contact plug 36 in order from the bottom along the concave portion formed in the second interlayer insulating film 37. An electrode 38, a capacitor insulating film 39 made of a ferroelectric (SBT (SrBiTaO) or BLT (BiLaTiO)) film, and an upper electrode 40 made of iridium oxide are formed. A capacitive element 41 having a stepped shape composed of 39 and the upper electrode 40 is formed.

In this embodiment, the portion of the lower electrode 38 that is in contact with the capacitive insulating film 39 made of a ferroelectric material has iridium oxide (IrO _x : 0) having a composition with less oxygen (deficiency) than the stoichiometric composition. <X <2). Further, the ferroelectric (BLT) constituting the capacitive insulating film 39 is made of bismuth layered perovskite, and the bismuth composition ratio is a composition in which bismuth is more excessive than the stoichiometric composition.

In this embodiment, in particular, when forming the lower electrode 38, IrO _x (0 <x <) is formed on the surface portion of the lower electrode 38 by sputtering in an atmosphere having an oxygen partial pressure of 70%. 2) is formed. As the subsequent treatment, heat treatment is performed at 650 ° C. for 1 minute by the RTP method.

Further, when forming a ferroelectric film to be the capacitive insulating film 39, the ferroelectric film is formed by MOCVD. Specifically, after forming a ferroelectric film (film thickness: 5 nm) having a composition of Bi _4.8 Ti ₃ O _x as a layer containing bismuth excessively on the lower electrode 38 by MOCVD, A ferroelectric film (thickness: 65 nm) having a composition of Bi _3.58 La _0.75 Ti ₃ O _x is formed thereon by MOCVD. Here, the ferroelectric film whose composition is Bi _4.8 Ti ₃ O _x corresponds to the region having a high dielectric constant in the third embodiment.

  The effects of the capacitive element according to this example will be described below.

  FIG. 16 shows the results of measuring the amount of polarization (the amount of spontaneous polarization 2Pr and the amount of polarization Pnv of its non-volatile component) with various changes in the bottom width of the lower electrode 38 in the capacitive element according to this example.

  As is apparent from FIG. 16, 2Pr and Pnv hardly change even when the bottom width of the lower electrode 38 is reduced. Therefore, it can be seen that the thin film produced according to the present invention exhibits performance even in capacitive elements having various three-dimensional structures.

On the other hand, for comparison, a capacitor formed using a conventional ferroelectric film (Bi _3.59 La _0.75 Ti ₃ O _x ) that does not have a high dielectric constant region is provided for comparison. The properties depending on the polarizability (2Pr) and the bottom width of the lower electrode 38 of Pnv are very large. For example, when the bottom width of the lower electrode 38 is 0.5 μm, since 2Pr is 10 μC / cm ² or less, a practical value is not obtained with the conventional ferroelectric film.

In Example 1, a ferroelectric film having a composition of Bi _4.8 Ti ₃ O _x was used as a layer having a high dielectric constant. However, this is a bismuth layered perovskite, and the ratio of bismuth in all metal elements Is higher than the ratio of bismuth in all metal elements in Bi _3.58 La _0.75 Ti ₃ O _x , for example, BiO _x , BiTiO _x, or BiLaO _x .

  Further, in Example 2, a three-dimensional structure capacitive element in which a capacitive insulating film is formed on a lower electrode having a concave portion may be used, but a convex-shaped lower electrode may be used, or the fourth embodiment. Thus, a capacitive element having a planar structure may be used.

  In the second embodiment, the case where the hydrogen barrier film is not formed has been described. However, when hydrogen diffusion into the capacitive element 41 becomes a problem, the first described above is provided so as to surround the capacitive element 41. As in the third embodiment, a hydrogen barrier film may be formed.

In the first embodiment and Examples 1 and 2 described above, IrO _x (0 <x <2) is formed on the portions of the lower electrodes 18a and 38 that are in contact with the ferroelectric. After forming the lower electrode, heat treatment in an oxygen atmosphere may be performed.

Further, IrO _x (0 <x <2) may be formed in the portions of the upper electrodes 20a and 40 that are in contact with the ferroelectric. In this case, the entire lower electrodes 18a and 38 may be Ir.

In addition, the portions of the upper electrodes 20a, 40 or the lower electrodes 18a, 38 that are in contact with the capacitor insulating films 19a, 39 made of a ferroelectric material are made of a noble metal oxide having a composition in which oxygen is more deficient than stoichiometry. Any conductor may be used. The noble metal may be made of one or more kinds of metals selected from Ir, Ru, Rh, Pd and Os. For example, when the noble metal is Ru, Rh, Pd or Os, RuO _x , RhO _x , PdO _x or OsO _x (0 <x <2).

  In addition to the portions of the upper electrodes 20a, 40 or the lower electrodes 18a, 38 that are in contact with the capacitor insulating films 19a, 39 made of a ferroelectric material, 1 selected from Pt, Ir, Ru, Rh, Pd, and Os. One or more kinds of metals, their oxides, TiAlN or TiN may be used.

In the first to third embodiments and Examples 1 and 2 described above, SBTN (SrBiTaNbO _x ) or BLTV (BiLaTiVO _x ) or the like is used as the ferroelectric material in addition to SBT or BLT. Also good.

  Polysilicon may be used as a material for the first or second contact plugs 17 and 24 or the contact plug 36.

Moreover, an insulating material having a hydrogen barrier property such as SiON, TiAlO, or Al ₂ O ₃ may be used for the material of the first or second hydrogen barrier films 16 and 22.

  In the first to third embodiments and Example 1 described above, the first or second hydrogen barrier films 16 and 22 having the effect of suppressing the hydrogen degradation of the ferroelectric material, which is a problem in the integration process. However, the first or second hydrogen barrier films 16 and 22 are not necessarily provided when hydrogen degradation of the ferroelectric material does not cause a problem.

  As described above, according to the capacitive element and the method of forming the same, the semiconductor memory device including the capacitive element, and the method of manufacturing the same, the ferroelectric in the capacitive element including the capacitive insulating film made of the ferroelectric material Therefore, it is useful for realizing a highly integrated ferroelectric memory.

1 is a cross-sectional view of a main part showing the structure of a capacitive element and a semiconductor memory device including the capacitive element according to a first embodiment of the present invention. (A)-(c) is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 1st Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. FIGS. 4A and 4B are main part process cross-sectional views illustrating a method for forming a capacitor element according to the first embodiment of the present invention and a method for manufacturing a semiconductor memory device including the capacitor element. FIGS. It is principal part sectional drawing which shows the structure of the semiconductor memory device containing the capacitive element which concerns on the 2nd Embodiment of this invention, and the capacitive element. (A)-(c) is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 2nd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. (A) And (b) is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 2nd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. (A) And (b) is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 2nd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. It is principal part sectional drawing which shows the structure of the capacitive element which concerns on the 3rd Embodiment of this invention, and the semiconductor memory device containing the capacitive element. It is the enlarged view which showed the modification of the structure of the capacitive element which concerns on the 3rd Embodiment of this invention. (A) And (b) is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 3rd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. (A) And (b) is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 3rd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. It is principal part process sectional drawing which shows the formation method of the capacitive element which concerns on the 3rd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element. It is a figure for demonstrating the effect in the formation method of the capacitive element which concerns on the 3rd Embodiment of this invention, and the manufacturing method of the semiconductor memory device containing the capacitive element, Comprising: (a) is from the surface of a lower electrode. FIG. 6 is a relationship diagram between the distance toward the upper electrode, the bismuth content in the ferroelectric film, and the bismuth composition ratio, and (b) shows the distance from the surface of the lower electrode toward the upper electrode and the dielectric of the capacitive insulating film. It is a relationship figure with a rate. It is a related figure of the film thickness and the amount of polarization of a capacity insulating film concerning Example 1 of the present invention. It is principal part sectional drawing which shows the structure of the capacitive element which concerns on Example 2 of this invention, and the semiconductor memory device containing the capacitive element. It is a related figure of the bottom part width of the lower electrode and the amount of polarization concerning Example 2 of the present invention. It is principal part structure sectional drawing which shows the structure of the semiconductor device provided with the capacitive element which consists of a ferroelectric film concerning a prior art example.

Explanation of symbols

11, 31 Silicon substrate 12, 32 Element isolation layer 13, 33 Impurity diffusion layer 14a, 34a Gate insulating film 14, 34 Gate electrode 15, 35 First interlayer insulating film 16 First hydrogen barrier film 17 First contact plug 18a, 18b, 38 a lower electrode _{19a, 19b, 19c, 19c c} -1, 19c c-2, 39 capacitive insulating film _{19 a-1, 19 b-} 1, the ferroelectric film 20a, 20b, 40 upper electrode 21a, 21b, 21c, 41 Capacitor element 22 Second hydrogen barrier film 23 Second interlayer insulating film 24 Second contact plug 25 Wiring 26 Embedded insulating film 27a Regions 27b, 27c, 27f adjacent to the lower electrode in the capacitive insulating film region 27d containing the center of the insulating film, 27 g capacitor insulating strength is region 27 _a-1 bismuth adjacent the top electrode is excessively added in the film the dielectric film 2 _b-1 bismuth content is less ferroelectric film 101 semiconductor substrate 102 first interlayer insulating film 103 first contact plug 104 lower electrode 105 capacitive insulating film 106 upper electrode 107 capacitor 108 second interlayer insulating film 109 first 2 contact plug 110 wiring

Claims (13)

A capacitive element in which a lower electrode, a capacitive insulating film made of a ferroelectric, and an upper electrode are formed in this order,
The portion in contact with the capacitive insulating film in at least one of the upper electrode and the lower electrode is a conductor made of a noble metal oxide,
The capacitor element, wherein the oxide of the noble metal has a composition with less oxygen than a stoichiometric composition.   2. The capacitor element according to claim 1, wherein the noble metal oxide includes oxygen desorbed from the noble metal oxide at 600 ° C. or higher as a constituent element.   The capacitive element according to claim 1, wherein the noble metal is made of one or more kinds of metals selected from Ir, Ru, Rh, Pd, and Os. A capacitive element in which a lower electrode, a capacitive insulating film made of a ferroelectric, and an upper electrode are formed in this order,
The capacitive element is made of a bismuth layered perovskite having a composition having more bismuth than a stoichiometric composition. A capacitive element in which a lower electrode, a capacitive insulating film made of a ferroelectric, and an upper electrode are formed in this order,
A dielectric constant of a region in the vicinity of at least one surface in contact with the lower electrode or the upper electrode in the capacitive insulating film is higher than a dielectric constant of a neighboring region in the center in the film thickness direction of the capacitive insulating film. Capacitance element.   The capacitive element according to claim 5, wherein a region in the vicinity of the at least one surface has a film thickness of 20 nm or less. A transistor having a source region and a drain region formed on a substrate;
An interlayer insulating film formed on the substrate so as to cover the transistor;
A plug contact formed in the interlayer insulating film so that a lower end thereof is electrically connected to the source region or the drain region;
A semiconductor memory device comprising: the capacitor element according to claim 1, wherein a lower surface is connected to an upper end of the plug contact. Forming a lower electrode on the substrate;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode on the capacitive insulating film,
The portion in contact with the capacitive insulating film in at least one of the lower electrode and the upper electrode is a conductor made of a noble metal oxide,
The method for forming a capacitor element, wherein the noble metal oxide is formed by performing heat treatment in an atmosphere containing oxygen on the deposited metal material film containing the noble metal as a main component. Forming a lower electrode on the substrate;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode on the capacitive insulating film;
A step of crystallizing the capacitive insulating film by performing a heat treatment,
The step of forming the capacitive insulating film includes:
Applying the dielectric solution containing bismuth on the lower electrode so that the crystallized capacitive insulating film has a composition containing more bismuth than the stoichiometric composition, and forming the capacitive insulating film. A method for forming a capacitor element. Forming a lower electrode on the substrate;
Forming a capacitive insulating film on the lower electrode;
Forming an upper electrode on the capacitive insulating film;
Capacitor insulation between at least one of the step of forming the lower electrode and the step of forming the capacitive insulating film and the step of forming the capacitive insulating film and the step of forming the upper electrode Forming a layer having a dielectric constant higher than the dielectric constant of the film. The capacitive insulating film is formed by applying a first dielectric solution,
The layer having a high dielectric constant is formed by applying a second dielectric solution,
The said 2nd dielectric material solution has the solution composition adjusted so that it might have a dielectric constant higher than the dielectric constant of the said capacity | capacitance insulating film, after passing through a crystallization process. A method for forming a capacitor element.   The method for forming a capacitive element according to claim 10, wherein the capacitive insulating film and the layer having a high dielectric constant are formed by vapor deposition. Forming a transistor having a source region and a drain region over a substrate;
Forming an interlayer insulating film on the substrate so as to cover the transistor;
Forming a plug contact in the interlayer insulating film so that a lower end thereof is electrically connected to the source region or the drain region;
The lower electrode, the capacitive insulating film, and the lower electrode are formed in this order using the method for forming a capacitive element according to any one of claims 8 to 12 so that the lower surface is connected to the upper end of the plug contact. A method of manufacturing a semiconductor memory device, comprising the step of forming a capacitive element formed.