JP2006032551A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device along with its manufacturing method capable of improving breakdown strength. <P>SOLUTION: The semiconductor device comprises an insulating layer, a semiconductor layer formed above the insulating layer, a gate insulating layer formed above the semiconductor layer, a gate electrode formed above the gate insulating layer, a source region formed in the semiconductor layer, and a drain region formed in the semiconductor layer. The specific inductive capacity of the insulating layer is higher than that of a silicon oxide. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having excellent pressure resistance and a method for manufacturing the same.

  An insulated gate transistor formed on an SOI (Silicon On Insulator) layer in which a semiconductor layer is provided on an insulating layer achieves lower power consumption and higher speed operation than when formed on a bulk semiconductor layer. As a device that can be used, research and development have been promoted in recent years. In particular, a fully depleted SOI transistor, in which the semiconductor layer on the insulating layer is completely depleted during transistor operation, is excellent in low power consumption, such as low threshold setting and low leakage utilizing steep subthreshold characteristics. Yes. However, the fully depleted SOI transistor has a problem in short channel resistance and drain breakdown voltage because the transistor structure is formed in the ultrathin semiconductor layer so that the semiconductor layer is completely depleted. This is a phenomenon caused by the potential barrier lowering (DIBL) induced from the drain electrode. In a fully depleted SOI transistor, the drain region and the insulating layer are adjacent to each other, and this phenomenon becomes remarkable. .

  An object of the present invention is to provide a semiconductor device excellent in short channel resistance and pressure resistance and a method for manufacturing the same.

(1) A semiconductor device according to the present invention includes:
An insulating layer;
A semiconductor layer formed above the insulating layer;
A gate insulating layer formed above the semiconductor layer;
A gate electrode formed above the gate insulating layer;
A source region formed in the semiconductor layer;
A drain region formed in the semiconductor layer;
Including
The insulating layer has a relative dielectric constant higher than that of silicon oxide.

  For example, when the semiconductor layer is made of a silicon layer and the insulating layer formed below the semiconductor layer is made of silicon oxide, the relative dielectric constant of silicon is 11.9, and the relative dielectric constant of silicon oxide is 3.9. Therefore, the relative dielectric constant difference is large. The potential of the drain region is lowered by the voltage applied to the drain electrode. In the case where the first insulating layer is made of silicon oxide, since the relative dielectric constant difference between the insulating layer and the drain region is large, the potential drop region is likely to enter the direction of the first insulating layer. This is because the potential drop region easily enters a layer having a lower relative dielectric constant. Then, the decrease in the potential that has entered from the first insulating layer goes into the body region through the insulating layer. This is called potential wraparound from the first insulating layer. The potential wrap around the insulating layer lowers the potential barrier and causes a short channel effect.

  According to the semiconductor device of the present invention, since the relative dielectric constant difference between the insulating layer and the drain region is small, it is possible to suppress the potential lowered region from entering the insulating layer as compared with the case where the insulating layer is made of silicon oxide. can do. As a result, potential wraparound from the insulating layer can be suppressed, and short channel resistance and drain breakdown voltage can be improved.

In the semiconductor device according to the present invention,
And further comprising at least another insulating layer formed above the drain region,
The other dielectric layer has a relative dielectric constant higher than that of silicon oxide.

  According to this aspect, compared to the case where silicon oxide is used as the material of the other insulating layer, the relative dielectric constant difference between the other insulating layer and the semiconductor layer is reduced, and the potential is lowered in the other insulating layer. Infiltration can be suppressed. Therefore, potential wraparound from other insulating layers can be suppressed, and short channel resistance and drain breakdown voltage can be improved.

(2) According to the semiconductor device of the present invention,
An insulating layer;
A semiconductor layer formed above the insulating layer;
A gate insulating layer formed above the semiconductor layer;
A gate electrode formed above the gate insulating layer;
A source region formed in the semiconductor layer;
A drain region formed in the semiconductor layer;
A body region formed in the semiconductor layer;
In the semiconductor layer, an electric field relaxation region formed between the drain region and the body region and having a higher dielectric constant than the drain region;
including.

  According to this aspect, since the electric field from the drain region toward the body region 12 can be relaxed, the short channel resistance and the drain breakdown voltage can be improved.

In the semiconductor device according to the present invention,
The electric field relaxation region has a relative dielectric constant higher than that of the body region.

In the semiconductor device according to the present invention,
The electric field relaxation region has a relative dielectric constant that increases from an end on the drain region side toward an end on the body region side.

In the semiconductor device according to the present invention,
The electric field relaxation region includes a first electric field relaxation region provided on the drain region side, and a second electric field relaxation region formed between the body region and the first electric field relaxation region. And
The first electric field relaxation region has a higher relative dielectric constant from an end on the drain region side toward an end on the second electric field relaxation region side,
The second electric field relaxation region has a relative dielectric constant that increases from an end on the body region side toward an end on the first electric field relaxation region side.

In the semiconductor device according to the present invention,
The electric field relaxation region may include a high dielectric material having a relative dielectric constant higher than that of the drain region.

(3) A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming an insulating layer;
(B) forming a semiconductor layer on the insulating layer;
(C) forming a gate insulating layer above the semiconductor layer;
(D) forming a gate electrode above the gate insulating layer;
(E) forming a drain region in the semiconductor layer;
(F) forming a source region in the semiconductor layer,
In the step (a), the insulating layer is formed using a material having a relative dielectric constant higher than that of silicon oxide.

In the method for manufacturing a semiconductor device according to the present invention,
After the step (f), the method may further include a step (g) of forming another insulating layer using a material having a relative dielectric constant higher than that of silicon oxide at least above the drain region.

(4) A method for manufacturing a semiconductor device according to the present invention includes:
(A) forming an insulating layer;
(B) forming a semiconductor layer on the insulating layer;
(C) forming a gate insulating layer above the semiconductor layer;
(D) forming a gate electrode above the gate insulating layer;
(E) forming a drain region in the semiconductor layer;
(F) forming a source region in the semiconductor layer;
(G) forming a body region in the semiconductor layer;
(H) forming an electric field relaxation region having a higher dielectric constant than the drain region between the drain region and the body region.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (h), the electric field relaxation region having a relative permittivity higher than that of the body region is formed.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (h), the electric field is introduced by introducing a high dielectric material having a relative dielectric constant higher than that of the drain region into a given region between the drain region and the body region. A relaxation region can be formed.

In the method for manufacturing a semiconductor device according to the present invention,
In the step (h), the dielectric constant of the electric field relaxation region can be increased by increasing the concentration of the high dielectric material introduced in the electric field relaxation region.

1. Semiconductor Device FIG. 1 is a cross-sectional view schematically showing a semiconductor device 100 according to the present embodiment. The semiconductor device 100 includes a support substrate 6, a first insulating layer 8, a semiconductor layer 10 formed on the first insulating layer 8, a gate insulating layer 20 formed on the semiconductor layer 10, and gate insulation. The gate electrode 22 formed on the layer 20, and the semiconductor layer 10, the gate insulating layer 20, and the second insulating layer 30 formed so as to cover the gate electrode 22 are included.

  The relative dielectric constant of the first insulating layer 8 is higher than that of silicon oxide. The relative dielectric constant of the second insulating layer 30 is higher than that of silicon oxide.

  The semiconductor layer 10 includes a drain region 28, a first electric field relaxation region 14, a second electric field relaxation region 16, a body region 12, and a source region 26. The first electric field relaxation region 14 and the second electric field relaxation region 16 are formed between the body region 12 and the drain region 28. The first electric field relaxation region 14 includes an impurity having the same conductivity type as that of the drain region 28. Second electric field relaxation region 16 includes impurities of the same conductivity type as body region 12.

  The first electric field relaxation region 14 and the second electric field relaxation region 16 have a higher relative dielectric constant than the drain region 28 and the body region 12. The relative dielectric constants of the first electric field relaxation region 14 and the second electric field relaxation region 16 desirably have a distribution as shown in FIG. FIG. 2 schematically shows the distribution of the concentration of the high dielectric material in the first electric field relaxation region 14 and the second electric field relaxation region 16. The vertical axis of the graph shown in FIG. 2 indicates the concentration of the high dielectric material, and the horizontal axis indicates the position in the direction parallel to the substrate surface and the cross section of FIG.

  As shown in FIG. 2, the concentration of the high dielectric material in the first electric field relaxation region 14 increases from the drain region 28 side toward the second electric field relaxation region 16 side. As the concentration of the high dielectric material increases, the relative dielectric constant also increases. Therefore, the relative dielectric constant of the first electric field relaxation region 14 increases from the drain region 28 side toward the second electric field relaxation region 16 side.

  The features of the semiconductor device 100 according to the present embodiment are as follows.

  (1) When the semiconductor layer is made of, for example, a silicon layer and the insulating layer formed below the semiconductor layer is made of silicon oxide, the relative dielectric constant of silicon is 11.9, and the relative dielectric constant of silicon oxide is 3 .9, the relative dielectric constant difference is large. The potential of the drain region is lowered by the voltage applied to the drain electrode (not shown). In the case where the first insulating layer is made of silicon oxide, since the relative dielectric constant difference between the first insulating layer and the drain region is large, the potential drop region is likely to enter the direction of the first insulating layer. This is because the potential drop region easily enters a layer having a lower relative dielectric constant. Then, the decrease in the potential that has entered from the first insulating layer wraps around the body region 12 through the first insulating layer. This is called potential wraparound from the first insulating layer. The potential barrier is lowered by the potential wraparound from the first insulating layer 8.

  Therefore, by making the relative dielectric constant of the first insulating layer 8 higher than the relative dielectric constant of silicon oxide, it is possible to suppress the potential drop from entering the first insulating layer 8. As a result, the potential wraparound from the first insulating layer 8 can be suppressed, and the short channel resistance and the drain breakdown voltage can be improved.

  (2) The relative dielectric constant of the second insulating layer 30 is higher than that of silicon oxide. As a result, the relative dielectric constant difference between the second insulating layer 30 and the semiconductor layer is reduced compared to the case where silicon oxide is used as the material of the second insulating layer 30, and the potential in the second insulating layer 30 is reduced. It is possible to suppress the intrusion of the decrease. Therefore, potential wraparound from the second insulating layer 30 can be suppressed, and short channel resistance and drain breakdown voltage can be improved.

  (3) The first electric field relaxation region 14 and the second electric field relaxation region 16 have a relative dielectric constant higher than that of the drain region 28 and the body region 12. Thereby, since the electric field from the drain region toward the body region 12 can be relaxed, the short channel resistance and the drain breakdown voltage can be improved.

  (4) As shown in FIG. 2, in the first electric field relaxation region 14, the concentration of the high dielectric material increases from the drain region 28 side toward the second electric field relaxation region 16 side. As the concentration of the high dielectric material increases, the relative dielectric constant also increases. Therefore, the relative dielectric constant of the first electric field relaxation region 14 increases from the drain region 28 side toward the second electric field relaxation region 16 side. Thereby, the electric field from the drain region 28 can be efficiently relaxed.

  In the second electric field relaxation region 16, the concentration of the high dielectric material increases from the body region 12 side toward the first electric field relaxation region 14 side. Therefore, the relative dielectric constant of the second electric field relaxation region 16 increases from the body region 12 side toward the first electric field relaxation region 14 side. As a result, the electric field from the drain region 28 can be efficiently relaxed, and entry of the potential lowering region into the body region 12 can be prevented.

  As shown in FIG. 2, since the maximum value of the relative dielectric constant is at the boundary between the first electric field relaxation region 14 and the second electric field relaxation region 16, the electric field from the drain region 28 side is more effectively relaxed. be able to. Therefore, the semiconductor device 100 can improve short channel resistance and pressure resistance by having the first electric field relaxation region 14 and the second electric field relaxation region 16.

2. Method for Manufacturing Semiconductor Device A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. In the manufacturing method described below, the numerical values described as specific examples describe an example in the case of forming an n-channel MOS transistor.

  (1) First, as shown in FIG. 3, the first insulating layer 8 is formed above the support substrate 6. For example, a silicon substrate is used as the support base 6. As the material of the first insulating layer 8, a material having a dielectric constant higher than that of silicon oxide, for example, silicon oxynitride, hafnium oxide, or aluminum oxide is used. The first insulating layer 8 is formed, for example, by depositing silicon oxynitride on the support base 6 by a CVD (Chemical Vapor Deposition) method.

  (2) Next, as shown in FIG. 4, the SOI substrate 50 is completed by forming the semiconductor layer 10 above the first insulating layer 8. As the semiconductor layer 10, for example, Si, Si—Ge, GaAs, InP, GaP, GaN, or the like can be used. The semiconductor layer 10 is formed by a bonding method, for example. The semiconductor layer 10 adheres the silicon substrate and the first insulating layer 8 by, for example, bonding a silicon substrate to the first insulating layer 8 and then performing a heat treatment. When the thickness of the semiconductor layer 10 is different from the desired thickness, the upper portion of the silicon substrate is thinned by polishing, etching, or a peeling method using hydrogen ion implantation, whereby the film of the semiconductor layer 10 is obtained. The thickness can be adjusted.

Next, as shown in FIG. 4, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 in order to adjust the threshold value. This impurity can be introduced by an ion implantation method. For example, in the case where an n-channel MOS transistor is formed using a single crystal silicon layer having a thickness of 50 nm as the semiconductor layer 10, BF ₂ is used as an impurity and the energy of 30 keV is 1 to 5 × 10 ¹² / About ² cm ² can be driven.

  (3) Next, as shown in FIG. 5, a gate insulating layer 20a and a gate electrode 22 are formed. As the gate insulating layer 20a, for example, a silicon oxide film can be formed by a thermal oxidation method. Next, a conductive layer (not shown) for the gate electrode 22 is formed on the gate insulating layer 20a. As the conductive layer, for example, a polycrystalline silicon layer can be deposited to a thickness of about 200 nm. Then, the gate electrode 22 is formed by patterning this conductive layer by a known lithography and etching technique.

  (4) Next, as shown in FIG. 6, a mask layer 24 is formed in a region other than the region where the first electric field relaxation region 14 (see FIG. 1) is formed. Examples of the material of the mask layer 24 include silicon oxide. The mask layer 24 is formed, for example, by depositing silicon oxide over the entire surface of the semiconductor layer 10 by a CVD method and patterning it by lithography and etching techniques.

  Next, as shown in FIG. 6, in order to form the first electric field relaxation region 14 and the second electric field relaxation region 16 (see FIG. 1), a high dielectric having a dielectric constant higher than that of the semiconductor layer 10. A body material is introduced into the semiconductor layer 10. The high dielectric material desirably has a higher relative dielectric constant than silicon, which is the material of the semiconductor layer 10. Specifically, since the relative dielectric constant of silicon is 11.9, examples of the high dielectric material include materials having a relative dielectric constant of 11.9 or more, such as germanium having a relative dielectric constant of 16.0. be able to. The first electric field relaxation region 14 and the second electric field relaxation region 16 are formed by an ion implantation method. In this ion implantation, a high dielectric material can be introduced also into the semiconductor layer 10 covered with the gate electrode 22, as shown in FIG. In this example, germanium (Ge) was introduced as a high dielectric material by an oblique ion implantation method. In the oblique ion implantation method, the implantation angle of ion implantation can be changed according to the film thickness of the gate electrode 22, the opening pattern of the mask layer 24, and the film thickness. Accordingly, the high dielectric material can be introduced so that the concentration of the high dielectric material has a distribution as shown in FIG. By increasing the concentration of the high dielectric material, the relative dielectric constant of the first electric field relaxation region 14 and the second electric field relaxation region 16 can be increased.

  Thereafter, heat treatment is performed. Thereafter, the mask layer 24 is removed by a wet etching technique using hydrofluoric acid, for example.

(5) Next, as shown in FIG. 7, impurities of a predetermined conductivity type are introduced into the semiconductor layer 10 to form the source region 26 and the drain region 28. For example, by using P as an impurity, an amount of about 1 × 10 ¹⁵ / cm ² can be implanted with an energy of 10 keV by an ion implantation method. Thereafter, heat treatment is performed to activate the introduced impurities. This heat treatment can be performed, for example, under the conditions of a processing temperature of 1000 ° C. and a processing time of 30 seconds. Here, impurities are also introduced into the first electric field relaxation region 14.

  (6) Next, the second insulating layer 30 is formed at least above the drain region 28 (see FIG. 1) (see FIG. 1). As the material of the second insulating layer 30, a material having a dielectric constant higher than that of silicon oxide, for example, silicon oxynitride, hafnium oxide, or aluminum oxide is used. The second insulating layer 30 is formed, for example, by depositing silicon oxynitride over the semiconductor layer 10 and the gate electrode 22 by a CVD (Chemical Vapor Deposition) method.

  The characteristics of the manufacturing method of the semiconductor device 100 according to the present embodiment are as follows.

  In the manufacturing method according to the present embodiment, the first electric field relaxation region 14 and the second electric field relaxation are performed by introducing a high dielectric material having a dielectric constant higher than that of the semiconductor layer 10 into the semiconductor layer 10. Region 16 is formed. The relative dielectric constants of the first electric field relaxation region 14 and the second electric field relaxation region 16 are determined according to the concentration of the introduced high dielectric material. Thereby, the relative dielectric constant of the first electric field relaxation region 14 and the second electric field relaxation region 16 can be adjusted to a desired relative dielectric constant.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to these embodiments and can take various forms. For example, in the present embodiment, the relative dielectric constant of the second electric field relaxation region 16 increases from the body region 12 side toward the first electric field relaxation region 14 side. The height may increase from the electric field relaxation region 14 side toward the body region 12 side.

FIG. 3 is a cross-sectional view schematically showing the semiconductor device according to the present embodiment. The schematic diagram which shows distribution of the dielectric constant of an electric field relaxation area | region. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on this Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on this Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on this Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on this Embodiment. Sectional drawing which shows 1 process of the manufacturing method of the semiconductor device which concerns on this Embodiment.

Explanation of symbols

6 Support substrate, 8 Insulating layer, 10 Semiconductor layer, 12 Body region, 14 First electric field relaxation region, 16 Second electric field relaxation region, 20 Gate insulating layer, 22 Gate electrode, 24 Mask layer, 26 Source region, 28 Drain region, 30 second insulating layer, 100 semiconductor device

Claims (13)

An insulating layer;
A semiconductor layer formed above the insulating layer;
A gate insulating layer formed above the semiconductor layer;
A gate electrode formed above the gate insulating layer;
A source region formed in the semiconductor layer;
A drain region formed in the semiconductor layer;
Including
A semiconductor device in which a dielectric constant of the insulating layer is higher than that of silicon oxide. In claim 1,
And further comprising at least another insulating layer formed above the drain region,
A semiconductor device having a relative dielectric constant of the other insulating layer higher than that of silicon oxide. An insulating layer;
A semiconductor layer formed above the insulating layer;
A gate insulating layer formed above the semiconductor layer;
A gate electrode formed above the gate insulating layer;
A source region formed in the semiconductor layer;
A drain region formed in the semiconductor layer;
A body region formed in the semiconductor layer;
In the semiconductor layer, an electric field relaxation region formed between the drain region and the body region and having a higher dielectric constant than the drain region;
Including a semiconductor device. In claim 3,
The semiconductor device, wherein a relative dielectric constant of the electric field relaxation region is higher than a relative dielectric constant of the body region. In claim 3 or 4,
In the semiconductor device, the electric field relaxation region has a higher relative dielectric constant from an end on the drain region side toward an end on the body region side. In claim 3 or 4,
The electric field relaxation region includes a first electric field relaxation region provided on the drain region side, and a second electric field relaxation region formed between the body region and the first electric field relaxation region. And
The first electric field relaxation region has a higher relative dielectric constant from an end on the drain region side toward an end on the second electric field relaxation region side,
The semiconductor device, wherein the second electric field relaxation region has a higher relative dielectric constant from an end on the body region side toward an end on the first electric field relaxation region side. In any of claims 3 to 6,
The semiconductor device, wherein the electric field relaxation region includes a high dielectric material having a relative dielectric constant higher than that of the drain region. (A) forming an insulating layer;
(B) forming a semiconductor layer on the insulating layer;
(C) forming a gate insulating layer above the semiconductor layer;
(D) forming a gate electrode above the gate insulating layer;
(E) forming a drain region in the semiconductor layer;
(F) forming a source region in the semiconductor layer,
In the step (a), the insulating layer is formed using a material having a relative dielectric constant of the insulating layer higher than that of silicon oxide. In claim 8,
After the step (f), the method further includes the step (g) of forming another insulating layer using a material having a relative dielectric constant higher than that of silicon oxide at least above the drain region. Method. (A) forming an insulating layer;
(B) forming a semiconductor layer on the insulating layer;
(C) forming a gate insulating layer above the semiconductor layer;
(D) forming a gate electrode above the gate insulating layer;
(E) forming a drain region in the semiconductor layer;
(F) forming a source region in the semiconductor layer;
(G) forming a body region in the semiconductor layer;
(H) forming an electric field relaxation region having a higher dielectric constant than the drain region between the drain region and the body region. In claim 10,
In the step (h), the electric field relaxation region having a relative permittivity higher than that of the body region is formed. In claim 10 or 11,
In the step (h), the electric field is introduced by introducing a high dielectric material having a relative dielectric constant higher than that of the drain region into a given region between the drain region and the body region. A method for manufacturing a semiconductor device, wherein a relaxation region is formed. In claim 12,
In the step (h), in the electric field relaxation region, the dielectric constant of the electric field relaxation region is increased by increasing the concentration of the high dielectric material to be introduced.

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