JP2006032507A - Capacitor incorporating substrate and substrate - Google Patents

Capacitor incorporating substrate and substrate Download PDF

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Publication number
JP2006032507A
JP2006032507A JP2004206730A JP2004206730A JP2006032507A JP 2006032507 A JP2006032507 A JP 2006032507A JP 2004206730 A JP2004206730 A JP 2004206730A JP 2004206730 A JP2004206730 A JP 2004206730A JP 2006032507 A JP2006032507 A JP 2006032507A
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layer
capacitor
substrate
electrode
electrodes
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Miyoko Nyuraiin
美代子 入来院
Koji Fusayasu
浩嗣 房安
Shiyouichi Mimura
詳一 三村
Seiji Hamada
清司 濱田
Akira Matsubara
亮 松原
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2004206730A priority Critical patent/JP2006032507A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

<P>PROBLEM TO BE SOLVED: To provide a capacitor incorporating substrate which is highly reliable and wherein a capacitor having a necessary capacity is built in. <P>SOLUTION: The substrate having a plurality of internal electrode layers incorporates a capacitor which is composed of two counterelectrodes. At least either of them is provided with two first electrodes that are formed in a first internal electrode layer while they are isolated with a wiring area in between and a second electrode that is formed in a second internal electrode layer while it is opposite to the wiring area. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、コンデンサ内蔵基板に関する。   The present invention relates to a capacitor built-in substrate.

従来から、プリント基板にＩＣ等の電子部品を実装する際に、プリント基板からの伝送・放射ノイズを抑制するために、バイパスコンデンサが用いられている。
図１は従来のバイパスコンデンサの実装方法の一例を示す図である。図１の従来例では、電源パターン１０１とＧＮＤパターン１０２が形成されたプリント基板１００上にボールグリッドアレイ（以下、ＢＧＡと略す）タイプのＩＣ１０４が設けられている。そして、バイパスコンデンサ１０３が電源パターン１０１とＧＮＤパターン１０２間に接続されている。バイパスコンデンサ１０３はインダクタンス成分を減らすために、ＩＣ１０４の近くに配置される。 Conventionally, when electronic components such as ICs are mounted on a printed board, a bypass capacitor has been used to suppress transmission / radiation noise from the printed board.
FIG. 1 is a diagram showing an example of a conventional bypass capacitor mounting method. In the conventional example of FIG. 1, a ball grid array (hereinafter abbreviated as BGA) type IC 104 is provided on a printed circuit board 100 on which a power supply pattern 101 and a GND pattern 102 are formed. A bypass capacitor 103 is connected between the power supply pattern 101 and the GND pattern 102. The bypass capacitor 103 is disposed near the IC 104 in order to reduce the inductance component.

しかし、バイパスコンデンサをＩＣの近くに配置しても、ＩＣ等の電源端子とバイパスコンデンサ１０３には、例えば、実装上の制約により、最小限の間隔をあける必要があり、その距離に比例して、電源パターン配線によるインダクタンス成分が生じる。この配線長によるインダクタンス成分が無視できる周波数では、バイパスコンデンサとして作用するが、無視できない高周波数帯域では、伝送・放射ノイズの抑制が不十分となる。この問題を解決するためのバイパスコンデンサの接続方法と形成方法が、例えば、特開平９−１０２６６３に示されているが、その方法では、ＢＧＡタイプのパッケージを用いたＩＣには適用できない。   However, even if the bypass capacitor is arranged near the IC, it is necessary to leave a minimum distance between the power supply terminal of the IC and the bypass capacitor 103 due to, for example, mounting restrictions, and in proportion to the distance. An inductance component is generated due to the power pattern wiring. At a frequency where the inductance component due to the wiring length can be ignored, it acts as a bypass capacitor, but transmission and radiation noise are not sufficiently suppressed in a high frequency band where it cannot be ignored. A bypass capacitor connecting method and forming method for solving this problem are disclosed in, for example, Japanese Patent Laid-Open No. 9-102663, but this method cannot be applied to an IC using a BGA type package.

また、特開平９−８２５５７には、ＢＧＡ内にコンデンサを形成することによりインダクタンス成分をなくし、伝送・放射ノイズを抑制できる構造が示されているが、ＢＧＡの製造に手間がかかるという問題がある。そこで、インダクタンス成分をなくして伝送・放射ノイズを抑制できる基板内蔵型コンデンサ形成方法が、特開平８−２０４３４１に示されている。
特開平９−１０２６６３号公報 特開平９−８２５５７号公報 特開平８−２０４３４１号公報 Japanese Patent Laid-Open No. 9-82557 discloses a structure in which an inductance component is eliminated by forming a capacitor in the BGA and transmission / radiation noise can be suppressed. However, there is a problem that it takes time to manufacture the BGA. . Japanese Patent Laid-Open No. 8-204341 discloses a method of forming a capacitor with a built-in substrate that can suppress transmission and radiation noise by eliminating an inductance component.
JP-A-9-102663 JP-A-9-82557 JP-A-8-204341

しかしながら、従来の基板内蔵型コンデンサ形成方法では、図４に模式的に示すように、例えば、６層のベース基板内の第３層２０２と第４層２０３を使ってコンデンサを作成した場合、ＩＣベアチップ５４から引き出した配線１５６を第４層２０３に接続する場合には必ず第１のコンデンサ電極１０６を大きく迂回しなければならず、ＩＣとしての信頼性にかけてしまうといった課題があった。
また、４層のベース基板内でコンデンサを形成するならば、配線の引き回しのために第１のコンデンサ電極１０６や第２のコンデンサ電極１０７に穴を開けなければならず、コンデンサの容量を確保することが難しくなるという問題もあった。 However, in the conventional substrate built-in capacitor formation method, as schematically shown in FIG. 4, for example, when a capacitor is formed using the third layer 202 and the fourth layer 203 in the six-layer base substrate, When the wiring 156 drawn from the bare chip 54 is connected to the fourth layer 203, the first capacitor electrode 106 must be largely detoured, and there is a problem that reliability as an IC is increased.
Further, if a capacitor is formed in a four-layer base substrate, a hole must be made in the first capacitor electrode 106 and the second capacitor electrode 107 for wiring, and the capacitance of the capacitor is ensured. There was also the problem that it became difficult.

そこで、本発明は、必要な容量のコンデンサが内蔵された信頼性の高いコンデンサ内蔵基板を提供することを目的とする。   Accordingly, an object of the present invention is to provide a highly reliable built-in capacitor board in which a capacitor having a required capacity is built.

以上の目的を達成するために、本発明に係る基板内蔵コンデンサは、複数の層を有する基板に内蔵されたコンデンサであって、上記コンデンサを構成する２つの対向電極のうちの少なくとも一方の対向電極は、上記複数の層のうちの任意の一つの層であるＡ層に配線領域を挟んで分離されるように形成された一対の第１電極と、上記Ａ層以外の任意の一つの層であるＢ層に上記配線領域に対向するように形成された第２電極とを含んでなることを特徴とする。   In order to achieve the above object, a substrate built-in capacitor according to the present invention is a capacitor built in a substrate having a plurality of layers, and is at least one counter electrode of two counter electrodes constituting the capacitor. Is a pair of first electrodes formed so as to be separated from the A layer, which is any one of the plurality of layers, with the wiring region interposed therebetween, and any one layer other than the A layer. A B layer includes a second electrode formed so as to face the wiring region.

以上のように構成された本発明に係る基板内蔵コンデンサは、例えば、ＩＣのパッケージに内蔵することができ、短い配線で外部端子に接続することが可能であり、配線の伝送損失の増大や放射ノイズを抑制することができるので信頼性の高いパッケージを提供できる。   The substrate built-in capacitor according to the present invention configured as described above can be incorporated in, for example, an IC package, and can be connected to an external terminal with a short wiring, which increases wiring transmission loss and radiation. Since noise can be suppressed, a highly reliable package can be provided.

以下、本発明に係る実施の形態の基板内蔵コンデンサについて説明する。
本実施の形態の基板内蔵コンデンサは、例えば、ＢＧＡパッケージを構成するためのベース基板５に内蔵される容量素子であり、その構成要素である対向電極がそれぞれ複数の層に渡って形成されていることを特徴とするものである。
尚、図２及び図３は、ベース基板５を用いて構成した集積回路の断面図であり、それぞれ以下のように構成される。 Hereinafter, a substrate built-in capacitor according to an embodiment of the present invention will be described.
The substrate built-in capacitor according to the present embodiment is, for example, a capacitive element built in the base substrate 5 for constituting the BGA package, and the counter electrode as the component is formed across a plurality of layers. It is characterized by this.
2 and 3 are cross-sectional views of the integrated circuit configured using the base substrate 5, and are configured as follows.

図２に示す集積回路では、ベース基板５上にＩＣベアチップがいわゆるフェイスアップボンディングされており、ＩＣベアチップ５４の端子はボンディングワイヤ５１によってベース基板５上の電極に接続されて樹脂５０で封止されている。ＩＣベアチップの入出力端子は、ベース基板５内の内部配線によりＩＣ端子５２に接続される。
図３に示す集積回路では、ベース基板５上にＩＣベアチップがいわゆるフェイスダウンで接続されており、ＩＣベアチップ５４はバンプ５３によりベース基板５上の電極に接続され、ベース基板５内の内部配線によりＩＣ端子５２に接続される。ＩＣベアチップ５４は、バンプ５３とともに樹脂５０により封止される。 In the integrated circuit shown in FIG. 2, an IC bare chip is so-called face-up bonded on the base substrate 5, and terminals of the IC bare chip 54 are connected to electrodes on the base substrate 5 by bonding wires 51 and sealed with a resin 50. ing. The input / output terminals of the IC bare chip are connected to the IC terminal 52 by internal wiring in the base substrate 5.
In the integrated circuit shown in FIG. 3, an IC bare chip is connected to the base substrate 5 in a so-called face-down manner, and the IC bare chip 54 is connected to an electrode on the base substrate 5 by a bump 53. Connected to the IC terminal 52. The IC bare chip 54 is sealed with the resin 50 together with the bumps 53.

本実施の形態の基板内蔵コンデンサは、係る集積回路において、例えば、ＩＣベアチップ５４の電源端子に接続されて高周波ノイズを除去するバイパスコンデンサとして形成されるものであり、好ましくは、ベース基板５において実装されるＩＣベアチップ５４の直下の位置に形成される。   The substrate built-in capacitor according to the present embodiment is formed as a bypass capacitor that is connected to the power supply terminal of the IC bare chip 54 and removes high frequency noise in the integrated circuit, and is preferably mounted on the base substrate 5. The IC bare chip 54 is formed at a position immediately below.

以下、本実施の形態の基板内蔵コンデンサについて、図５に示すＢＧＡ用の８層からなるベース基板の内部に形成された例により詳細に説明する。ここでは、ＩＣベアチップ５４がベース基板の上面にフェースダウン（フリップチップ）実装されたものとして図示している。   Hereinafter, the substrate built-in capacitor according to the present embodiment will be described in detail with reference to an example formed inside a base substrate composed of eight layers for BGA shown in FIG. Here, the IC bare chip 54 is illustrated as being face-down (flip chip) mounted on the upper surface of the base substrate.

本実施の形態では、ベース基板において、基板内蔵コンデンサを構成する２つの対向電極のうちの一方の対向電極は、基板内部の第３層２０２（Ａ層）に形成された第１のコンデンサ電極６と第４層２０３（Ｂ層）に形成された第２のコンデンサ電極７とからなり、他方の対向電極は、基板内部の第５層２０４（Ｃ層）に形成された第３のコンデンサ電極８と第６層２０５（Ｄ層）に形成された第４のコンデンサ電極９とからなっている。   In the present embodiment, in the base substrate, one of the two counter electrodes constituting the substrate built-in capacitor is the first capacitor electrode 6 formed on the third layer 202 (A layer) inside the substrate. And the second capacitor electrode 7 formed on the fourth layer 203 (B layer), and the other counter electrode is the third capacitor electrode 8 formed on the fifth layer 204 (C layer) inside the substrate. And the fourth capacitor electrode 9 formed in the sixth layer 205 (D layer).

また、Ａ層において、第１のコンデンサ電極６は配線領域（第１配線領域）を挟んで２つに分離されて一対の電極となっており、Ｂ層において、第２のコンデンサ電極７は配線領域（第２配線領域）を挟んで２つに分離されて一対の電極となっている。そして、分離された第１のコンデンサ電極６の１つはＢ層の第２配線領域に対向し、分離された第２のコンデンサ電極７の１つはＡ層における第１配線領域に対向している。そして、第１のコンデンサ電極６と第２のコンデンサ電極７は互いに一部で対向して重なるように形成されて、その重なった部分でビアホールを用いて接続されることにより一方の対向電極が構成される。   In the A layer, the first capacitor electrode 6 is separated into two with a wiring region (first wiring region) interposed therebetween, and in the B layer, the second capacitor electrode 7 is connected to the wiring. A pair of electrodes is formed by separating the region (second wiring region) into two. One of the separated first capacitor electrodes 6 faces the second wiring region of the B layer, and one of the separated second capacitor electrodes 7 faces the first wiring region of the A layer. Yes. The first capacitor electrode 6 and the second capacitor electrode 7 are formed so as to face each other and overlap each other, and one of the counter electrodes is configured by connecting via the via hole at the overlapping portion. Is done.

さらに、Ｃ層に形成された他方の対向電極の一部を構成する第３のコンデンサ電極８は、２つに分離されてそれぞれ第１のコンデンサ電極６に対向するように形成され、Ｄ層に形成された第４のコンデンサ電極９は２つに分離されてそれぞれ第２のコンデンサ電極７に対向するように形成される。すなわち、Ｃ層において、第３のコンデンサ電極８は配線領域（第３配線領域）を挟んで２つに分離されており、Ｄ層において、第４のコンデンサ電極９は配線領域（第４配線領域）を挟んで２つに分離されている。そして、第３のコンデンサ電極８と第４のコンデンサ電極９は互いに一部で対向して重なるように形成されて、その重なった部分でビアホールを用いて接続されることにより他方の対向電極が構成される。   Further, the third capacitor electrode 8 constituting a part of the other counter electrode formed in the C layer is separated into two and formed so as to face the first capacitor electrode 6, respectively. The formed fourth capacitor electrode 9 is separated into two and is formed to face the second capacitor electrode 7 respectively. That is, in the C layer, the third capacitor electrode 8 is separated into two across the wiring region (third wiring region), and in the D layer, the fourth capacitor electrode 9 is separated from the wiring region (fourth wiring region). ) Is separated into two. The third capacitor electrode 8 and the fourth capacitor electrode 9 are formed so as to face each other and overlap each other, and the other counter electrode is configured by connecting via the via hole at the overlapping portion. Is done.

尚、第１のコンデンサ電極６と第２のコンデンサ電極７からなる一方の対向電極と、第３のコンデンサ電極８と第４のコンデンサ電極９からなる他方の対向電極の間には、いうまでもなく基板を構成する絶縁体からなる誘電体が挟まれており、その誘電体の誘電率と２つの対向電極の対向面積とによって基板内蔵コンデンサの静電容量が決定される。   Needless to say, between one counter electrode composed of the first capacitor electrode 6 and the second capacitor electrode 7 and the other counter electrode composed of the third capacitor electrode 8 and the fourth capacitor electrode 9. In other words, a dielectric made of an insulator constituting the substrate is sandwiched, and the capacitance of the substrate built-in capacitor is determined by the dielectric constant of the dielectric and the opposing area of the two counter electrodes.

このように構成された基板内蔵コンデンサにおいて、例えば、一方の対向電極は、図５に示すように、第２のコンデンサ電極７のある端部から引き出され、第４層２０３、第５層２０４、第６層２０５、第７層２０６を貫通するビアホールを用いて形成された配線５７を介して第８層２０７のコンデンサ端子１０に接続される。
また、他方の対向電極は、例えば、図５に示すように、第４のコンデンサ電極９のある端部から引き出され、第６層２０５及び第７層２０６を貫通するビアホールを用いて形成された配線５８を介して第８層２０７のコンデンサ端子１１に接続される。 In the substrate built-in capacitor configured in this way, for example, one counter electrode is pulled out from an end portion of the second capacitor electrode 7 as shown in FIG. 5, and the fourth layer 203, the fifth layer 204, The capacitor layer 10 is connected to the capacitor terminal 10 of the eighth layer 207 through a wiring 57 formed using a via hole penetrating the sixth layer 205 and the seventh layer 206.
Further, the other counter electrode is formed by using a via hole that is drawn from an end portion of the fourth capacitor electrode 9 and penetrates the sixth layer 205 and the seventh layer 206, as shown in FIG. It is connected to the capacitor terminal 11 of the eighth layer 207 through the wiring 58.

以上のように、内部に基板内蔵コンデンサを構成する対向電極が形成された多層基板においては、ＩＣベアチップ５４の端子のうち、外側に位置する端子は第１層２００の配線５５により外側に引き出され、第２から第７層を貫通するビアホールを介して第８層２０７に形成された所定の端子に接続される。   As described above, in the multilayer substrate in which the counter electrode constituting the substrate built-in capacitor is formed, the terminals located outside of the terminals of the IC bare chip 54 are drawn to the outside by the wiring 55 of the first layer 200. These are connected to predetermined terminals formed in the eighth layer 207 through via holes penetrating the second to seventh layers.

また、ＩＣベアチップ５４の端子のうち内側に位置する端子（例えば、図５に示すＩＣベアチップ５４の端子６０）は、５６の符号を付して示す配線のように、第２層２０１を貫通するビアホールにより端子６０の直下の位置で第１配線領域に形成された配線に接続されて第２コンデンサ電極７及び第４コンデンサ電極９を迂回するように引き出されて第３層２０２、第４層２０３、第５層２０４及び第６層２０５を貫通するビアホールにより第７層２０６に形成された配線に接続され、その配線と第７層２０６を貫通するビアホールを介して第８層２０７の端子６１に接続される。   In addition, among the terminals of the IC bare chip 54, a terminal located inside (for example, the terminal 60 of the IC bare chip 54 shown in FIG. 5) penetrates the second layer 201 like a wiring denoted by reference numeral 56. The third layer 202 and the fourth layer 203 are connected to a wiring formed in the first wiring region at a position immediately below the terminal 60 by a via hole and drawn out so as to bypass the second capacitor electrode 7 and the fourth capacitor electrode 9. , Connected to the wiring formed in the seventh layer 206 by a via hole penetrating the fifth layer 204 and the sixth layer 205, and connected to the terminal 61 of the eighth layer 207 through the wiring and the via hole penetrating the seventh layer 206. Connected.

以上のように構成された本実施の形態の基板内蔵コンデンサは、その容量を構成するための対向電極をそれぞれ複数の層に渡って形成しているので、必要な容量を確保するために必要な対向面積を確保しつつ、その対向電極に制約されることなく、比較的短い配線長でかつ容易にＩＣベアチップ５４の端子と基板の端子とを接続できる。
従って、従来例のように比較的大きな面積のコンデンサ電極を迂回して配線を長く引き回す必要がないので、配線長が長くなることに起因して生じる伝送損失の増加及び放射ノイズの発生を抑制することができる。 In the substrate built-in capacitor according to the present embodiment configured as described above, the counter electrodes for forming the capacitance are formed over a plurality of layers, respectively, so that it is necessary to secure the necessary capacitance. While securing the facing area, the terminals of the IC bare chip 54 and the terminals of the substrate can be easily connected with a relatively short wiring length without being restricted by the facing electrode.
Therefore, it is not necessary to bypass the capacitor electrode having a relatively large area as in the conventional example, and the wiring does not need to be routed long, so that the increase in transmission loss and the generation of radiation noise caused by the long wiring length are suppressed. be able to.

また、本実施の形態では、ＩＣベアチップ５４の端子と基板内蔵コンデンサ間を基板内部で接続することなく、それぞれ基板の外部端子に接続しているので、ＩＣベアチップ５４のどの端子を基板内蔵コンデンサに接続するか、外部で選択できる。
これによって、ベース基板５を用いて構成された集積回路を実装するプリント基板の配線によりプリント基板上において基板内蔵コンデンサの接続を選択又は変更することが可能になる。 In the present embodiment, the terminals of the IC bare chip 54 are connected to the external terminals of the board without connecting the terminals of the IC bare chip 54 and the board built-in capacitor inside the board. Can be connected or externally selected.
Accordingly, it is possible to select or change the connection of the built-in capacitor on the printed circuit board by wiring of the printed circuit board on which the integrated circuit configured using the base substrate 5 is mounted.

尚、本実施の形態では、ＩＣベアチップをフェイスダウンで接続された例で説明したが、本発明はこれに限られるものではなく、ＩＣベアチップをフェイスアップで実装した場合であっても同様に適用できる。
また、ベース基板が８層の場合を例にとって説明したが、８層に限定されるものではない。
また、本実施の形態では、２つの対向電極をそれぞれ相隣り合う層に形成するようにしたが、本発明はこれに限られるものではなく、２つの対向電極を任意の層に形成してもよい。 In the present embodiment, the example in which the IC bare chip is connected face-down has been described. However, the present invention is not limited to this, and the same applies even when the IC bare chip is mounted face-up. it can.
Further, the case where the base substrate has eight layers has been described as an example, but the number is not limited to eight layers.
In this embodiment, the two counter electrodes are formed in adjacent layers, but the present invention is not limited to this, and the two counter electrodes may be formed in any layer. Good.

またさらに、本実施の形態では、２つの対向電極をそれぞれ複数の層に渡って形成するようにしたが、本発明はこれに限られるものではなく、いずれか一方の対向電極を複数層に渡って形成するようにしてもよい。   Furthermore, in this embodiment, the two counter electrodes are formed over a plurality of layers, respectively, but the present invention is not limited to this, and any one counter electrode extends over a plurality of layers. You may make it form.

また、本実施の形態では、一方の対向電極をＡ層に形成した一対の第１のコンデンサ電極６とＢ層に形成した一対の第２のコンデンサ電極７によって構成した。しかしながら、本発明はこれに限られるものではなく、一方の対向電極が、Ａ層及び／又はＢ層に、一対の第１のコンデンサ電極６及び／又は一対の第２のコンデンサ電極７に加えてさらに、それぞれ配線領域を挟んで分離されてなる一対又は二対以上の電極を含んでいてもよい。尚、他方の対向電極についても同様である。   In the present embodiment, one counter electrode is constituted by a pair of first capacitor electrodes 6 formed in the A layer and a pair of second capacitor electrodes 7 formed in the B layer. However, the present invention is not limited to this, and one counter electrode is added to the A layer and / or the B layer in addition to the pair of first capacitor electrodes 6 and / or the pair of second capacitor electrodes 7. Furthermore, a pair of electrodes or two or more pairs of electrodes separated from each other with a wiring region interposed therebetween may be included. The same applies to the other counter electrode.

また、本実施の形態では、ベース基板に１つの基板内蔵コンデンサを形成した例により説明したが、本発明はこれに限られるものではなく、ベース基板に上述のように構成された基板内蔵コンデンサを複数個形成することができ、その複数の基板内蔵コンデンサをプリント基板側の配線により組み合わせることにより、コンデンサの容量を変更することも可能になる。   In the present embodiment, the example in which one substrate built-in capacitor is formed on the base substrate has been described. However, the present invention is not limited to this, and the substrate built-in capacitor configured as described above is formed on the base substrate. A plurality of capacitors can be formed, and the capacitance of the capacitors can be changed by combining the plurality of built-in capacitors with wiring on the printed board side.

また、本実施の形態では、２端子の基板内蔵コンデンサの例を説明したが、本発明はこれに限られるものではなく、３端子コンデンサを構成することもでき、より効果的に伝送損失を抑え、放射ノイズをさらに抑制することも可能である。   In this embodiment, an example of a two-terminal substrate built-in capacitor has been described. However, the present invention is not limited to this, and a three-terminal capacitor can be configured to suppress transmission loss more effectively. It is also possible to further suppress radiation noise.

また、本発明では、ベース基板を構成する絶縁体として、種々の材料を使用することができ、例えば、ガラスエポキシ、ガラス熱硬化ＰＰＯ樹脂などの高誘電率材料を用いることにより、より小さい面積又は体積でより静電容量の高い基板内蔵コンデンサを構成することが可能であり、より伝送特性を良好にし、放射ノイズを抑制することができるようになる。   In the present invention, various materials can be used as the insulator constituting the base substrate. For example, by using a high dielectric constant material such as glass epoxy or glass thermosetting PPO resin, a smaller area or It is possible to constitute a capacitor with a built-in substrate having a higher capacitance by volume, and it becomes possible to improve transmission characteristics and suppress radiation noise.

以上説明したように、本発明による基板内蔵コンデンサは、ＩＣパッケージ内にコンデンサを形成することが可能になり、効率よく伝送・放射ノイズを抑制することができる。   As described above, the substrate built-in capacitor according to the present invention can form a capacitor in an IC package, and can efficiently suppress transmission / radiation noise.

従来例の基板上にＩＣとバイパスコンデンサを実装した従来例の斜視図である。It is a perspective view of the conventional example which mounted IC and the bypass capacitor on the board | substrate of the conventional example. ＩＣベアチップがフェイスアップ実装されたＢＧＡパッケージタイプの集積回路の断面図である。It is sectional drawing of the integrated circuit of a BGA package type in which IC bare chip was mounted face-up. ＩＣベアチップがフェイスダウン実装されたＢＧＡタイプの集積回路の断面図である。It is sectional drawing of the BGA type integrated circuit by which IC bare chip was mounted face-down. 従来の基板内蔵コンデンサの構成を示す分解斜視図である。It is a disassembled perspective view which shows the structure of the conventional board | substrate built-in capacitor | condenser. 本発明に係る実施の形態の基板内蔵コンデンサの構成を示す分解斜視図である。1 is an exploded perspective view showing a configuration of a substrate built-in capacitor according to an embodiment of the present invention.

符号の説明Explanation of symbols

５ ベース基板、６ 第１のコンデンサ電極、７ 第２のコンデンサ電極、８ 第３のコンデンサ電極、９ 第４のコンデンサ電極、１０ コンデンサ端子、１２ ビアホール、５０ 樹脂、５１ ワイヤボンディング、５２ ＩＣ端子、５３ バンプ、５４ ＩＣベアチップ、５５，５６，５７，５８ 配線、２００ 第１層、２０１ 第２層、２０２ 第３層、２０３ 第４層、２０４ 第５層、２０５ 第６層、２０６ 第７層、２０７ 第８層。
5 base substrate, 6 first capacitor electrode, 7 second capacitor electrode, 8 third capacitor electrode, 9 fourth capacitor electrode, 10 capacitor terminal, 12 via hole, 50 resin, 51 wire bonding, 52 IC terminal, 53 Bump, 54 IC bare chip, 55, 56, 57, 58 Wiring, 200 1st layer, 201 2nd layer, 202 3rd layer, 203 4th layer, 204 5th layer, 205 6th layer, 206 7th layer 207, eighth layer.

Claims (9)

複数の層を有する基板に内蔵されたコンデンサであって、
上記コンデンサを構成する２つの対向電極のうちの少なくとも一方の対向電極は、
上記複数の層のうちの任意の一つの層であるＡ層に配線領域を挟んで分離されるように形成された一対の第１電極と、上記複数の層のうちの上記Ａ層以外の任意の一つの層であるＢ層に上記配線領域に対向するように形成された第２電極とを含んでなることを特徴とする基板内蔵コンデンサ。 A capacitor built in a substrate having a plurality of layers,
At least one counter electrode of the two counter electrodes constituting the capacitor is:
A pair of first electrodes formed so as to be separated from the A layer, which is any one of the plurality of layers, with the wiring region interposed therebetween, and any one of the plurality of layers other than the A layer And a second electrode formed so as to face the wiring region in the B layer, which is one of the layers. 上記一対の第１電極はそれぞれその一部で上記第２電極に対向しており、その対向する部分でそれぞれ上記第２電極とビアホールを用いて接続されている請求項１記載の基板内蔵コンデンサ。   2. The substrate built-in capacitor according to claim 1, wherein a part of each of the pair of first electrodes is opposed to the second electrode, and the second part is connected to the second electrode using a via hole. 上記２つの対向電極のうちの他方の対向電極は、上記一対の第１電極にそれぞれ対向するように上記Ａ層と上記Ｂ層以外の任意の一つの層であるＣ層に配線領域を挟んで分離されるように形成された一対の第３電極と、上記第２電極と対向するように上記Ａ層、上記Ｂ層及び上記Ｃ層以外の任意の一つの層であるＤ層に形成された第４電極とを含んでなる請求項１又は２記載の基板内蔵コンデンサ。   The other counter electrode of the two counter electrodes has a wiring region sandwiched between C layers, which is any one layer other than the A layer and the B layer, so as to face the pair of first electrodes, respectively. A pair of third electrodes formed so as to be separated from each other, and a D layer that is an arbitrary layer other than the A layer, the B layer, and the C layer so as to face the second electrode. The substrate built-in capacitor according to claim 1, further comprising a fourth electrode. 上記一対の第３電極はそれぞれその一部で上記第４電極に対向しており、その対向する部分でそれぞれ上記第４電極とビアホールを用いて接続されている請求項３記載の基板内蔵コンデンサ。   4. The substrate built-in capacitor according to claim 3, wherein a part of each of the pair of third electrodes is opposed to the fourth electrode, and the opposite part is connected to the fourth electrode using a via hole. 上記Ｂ層は上記Ａ層と上記Ｃ層の間に位置し、上記Ｃ層は上記Ｂ層と上記Ｄ層の間に位置する請求項３又は４記載の基板内蔵コンデンサ。   5. The substrate built-in capacitor according to claim 3, wherein the B layer is located between the A layer and the C layer, and the C layer is located between the B layer and the D layer. 請求項１〜５のうちのいずれか１つに記載の基板内蔵コンデンサを複数個含む基板。   A substrate comprising a plurality of the substrate built-in capacitors according to claim 1. 上記配線領域に上記コンデンサと電気的に分離された配線を形成した請求項６記載の基板。   The substrate according to claim 6, wherein a wiring electrically isolated from the capacitor is formed in the wiring region. 上記対向電極が上記基板表面の外部接続用端子に接続された請求項６又は７記載の基板。   The substrate according to claim 6 or 7, wherein the counter electrode is connected to an external connection terminal on the surface of the substrate. 上記一方の対向電極は、上記一対の電極とは別にさらに、それぞれ配線領域を挟んで分離されている一対又は二対以上の電極を含む請求項１又は３に記載の基板内蔵コンデンサ。
4. The substrate built-in capacitor according to claim 1, wherein the one counter electrode further includes a pair or two or more pairs of electrodes separated from each other with the wiring region interposed therebetween, in addition to the pair of electrodes.
JP2004206730A 2004-07-14 2004-07-14 Capacitor incorporating substrate and substrate Pending JP2006032507A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008028282A (en) * 2006-07-25 2008-02-07 Rohm Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008028282A (en) * 2006-07-25 2008-02-07 Rohm Co Ltd Semiconductor device

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