JP2006020274A - Communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a communication system capable of accurately measuring a communication distance between two communication terminals. <P>SOLUTION: A communication system comprises a transmitter and a receiver. The transmitter and the receiver are disposed in a radio communication space. The transmitter completely transmit data DATT to the receiver synchronously with a timing t1. When data DARR are completely received from the transmitter, the receiver starts transmitting data DART to the transmitter after the lapse of a fixed time SIFS (in a timing t3). The transmitter then measures a total time between the timing t1 and a timing 6 when starting stably receiving the data DATR, and determines a communication distance to the receiver based on the measured total time. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a communication system, and more particularly to a communication system capable of measuring a communication distance between two communication terminals.

  In a conventional wireless LAN (Local Area Network) system, a CDMA (Code Division Multiple Access) method is used as a physical layer protocol, and a CSMA / CA (Carrier Sense) is used as a medium access control method in a data link layer. Multiple Access with Collation Avidance) is used.

  This CSMA / CA method is a method for avoiding a communication collision by constantly monitoring whether or not another terminal is transmitting a packet and whether or not a packet addressed to itself is being transmitted (non-patent). Reference 1). That is, each terminal transmits data after confirming that the network is continuously available for a predetermined time or more.

Thus, in the conventional wireless LAN system, data communication is performed using the CSMA / CA method.
By Koizumi, “All of Data Communication with Illustrations”, Nihon Jitsugyo Publishing Co., Ltd., November 20, 1999, p. 272.

  However, the conventional wireless LAN system has a problem that the communication distance between two terminals cannot be measured. In addition, when the terminal that is the target of the communication distance is far away from the terminal that measures the communication distance, there is a problem that it is difficult to accurately measure the communication distance.

  Accordingly, the present invention has been made to solve such a problem, and an object thereof is to provide a communication system capable of accurately measuring a communication distance between two communication terminals.

  According to this invention, the communication system is a communication system capable of measuring a communication distance between two communication terminals arranged in a wireless communication space, and includes a transmitter and a receiver. The transmitter completes data transmission via the wireless communication space. The receiver receives data from the transmitter via the wireless communication space, and transmits data for a response to the received data to the transmitter via the wireless communication space. The transmitter and the receiver transmit and receive data in synchronization with the reference clock. Further, the transmitter measures the total time between the first timing for completing transmission of data to the receiver and the second timing for starting to stably receive data from the receiver, and measures the total time. The communication distance to the receiver is determined based on the total time.

  Preferably, the second timing is a reception end timing of a signal indicating the start of a frame.

  Preferably, the signal indicating the start of a frame is a start frame delimiter.

  Preferably, the receiver transmits data to the transmitter after a response time has elapsed after completion of reception of the data from the transmitter. The transmitter then subtracts a certain time including the response time from the total time to calculate a round trip time for data to and from the receiver, and based on the calculated round trip time, calculates the communication distance to the receiver. decide.

  Preferably, the data includes a synchronization signal portion, a frame start portion, and a frame portion sequentially from the top. The fixed time is the sum of the response time, the detection time of the synchronization signal portion, and the detection time of the frame start portion.

  Preferably, the receiver estimates a reference clock signal generated at the transmitter based on data received from the transmitter, determines a response time based on the estimated reference clock signal, and transmits the data to the transmitter. Send.

  Preferably, in communication with the receiver, the transmitter estimates a first reference clock signal generated in the receiver based on data received from the receiver, and transmits a second reference clock signal generated by the transmitter. When the phase of the second reference clock signal is deviated from the phase of the first reference clock signal, the change in the communication distance with the receiver is measured. .

  Preferably, the receiver detects a phase difference between the phase of the data received from the transmitter and the phase of the first reference clock signal generated by the receiver, and the first reference clock signal is based on the detected phase difference. Is matched with the phase of the second reference clock signal generated in the transmitter to measure the response time, and after measuring the response time, the data is transmitted to the transmitter. The transmitter calculates a round trip time for data to and from the receiver by subtracting a certain time including the response time from the total time, and determines a communication distance to the receiver based on the calculated round trip time. .

  Preferably, the receiver detects the phase difference between the phase of the data received from the transmitter and the phase of the first reference clock signal generated by the receiver, converts the detected phase difference into a time length, and The first response time is measured in synchronization with one reference clock signal, and the data and the time length are transmitted to the transmitter after the first response time is measured. The transmitter causes the first response time to match the second response time at the receiver when the phase of the first reference clock signal matches the phase of the second reference clock signal generated by the transmitter. The fixed time including the first response time is adjusted based on the time length, and the fixed time after the adjustment is subtracted from the total time to calculate the round trip time for data to and from the receiver. The communication distance to the receiver is determined based on the round trip time.

  Preferably, the transmitter detects a phase difference between the phase of the data received from the receiver and the phase of the first reference clock signal generated by the transmitter, converts the detected phase difference into a time length, and receives the received signal. Measured in synchronization with the second reference clock at the first response time at the receiver when the phase of the second reference clock signal generated in the machine matches the phase of the first reference clock signal A round trip in which the fixed time including the second response time is adjusted so that the second response time of the receiver matches, and the fixed time after the adjustment is subtracted from the total time to reciprocate data between the receiver and the receiver. The time is calculated, and the communication distance to the receiver is determined based on the calculated round trip time.

  In the communication system according to the present invention, the idle time of communication between the transmitter and the receiver, in which data is increased by the round-trip time between the transmitter and the receiver, is measured to determine the interval between the transmitter and the receiver. The communication distance is determined. The round trip time is measured between a first timing at which the transmitter finishes transmitting data to the receiver and a second timing at which the transmitter starts to stably receive data from the receiver. .

  Therefore, according to the present invention, it is possible to accurately determine the communication distance between the transmitter and the receiver by using the communication idle period between the transmitter and the receiver. Further, the communication distance between the transmitter and the receiver can be accurately determined even when the receiver is far away from the transmitter.

  Further, in the communication system according to the present invention, when the phase of the reference clock signal at the transmitter is shifted from the phase of the reference clock signal at the receiver, either the transmitter or the receiver adjusts the phase shift to transmit data. The round-trip time for reciprocating between the receiver and the receiver is calculated.

  Therefore, according to the present invention, the distance between the transmitter and the receiver can be accurately determined even if the phase of the reference clock signal in the transmitter is shifted from the phase of the reference clock signal in the receiver.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a schematic block diagram of a communication system according to Embodiment 1 of the present invention. The communication system 100 includes a transmitter 10 and a receiver 30. The transmitter 10 and the receiver 30 are disposed in the wireless communication space 20. The transmitter 10 and the receiver 30 perform data communication with each other by the CSMA / CA method via the wireless communication space 20.

  In the following description, it is assumed that the transmitter 10 is a measuring device that measures a communication distance with the receiver 30, and the receiver 30 is a device under measurement.

The transmitter 10 transmits data to the receiver 30 via the wireless communication space 20 at a carrier frequency of 2.4 GHz, for example, using an IFS (Interframe Space) that is a non-communication period in the wireless communication space 20. To do. Then, the transmitter 10 measures the time between the timing at which the transmission of data to the receiver 30 is completed and the timing at which the data from the receiver 30 starts to be stably received, and based on the measured time. Thus, the communication distance to the receiver 30 is determined by a method described later. Note that the timing at which the transmitter 10 starts to stably receive data from the receiver 30 will be described in detail later.

  The receiver 30 receives the data from the transmitter 10 via the wireless communication space 20, and transmits the data to the transmitter 10 via the wireless communication space 20 when a certain time elapses after the data reception is completed.

  FIG. 2 is a schematic block diagram showing the configuration of the transmitter 10 shown in FIG. The transmitter 10 includes an antenna 110, selectors 120 and 240, amplifiers 130 and 290, mixers 140 and 280, low-pass filters 150 and 270, a demodulator 160, a clock adjuster 170, and a carrier detector 180. An A / D converter 190, a counter 200, a controller 210, a crystal oscillator 220, a clock generator 230, a 1 / N frequency divider 250, and a modulator 260.

  The antenna 110 receives a radio wave via the wireless communication space 20 and transmits the received radio wave to the selector 120. Further, the antenna 110 transmits the radio wave from the selector 120 to the wireless communication space 20.

  The selector 120 includes terminals 121 and 122 and a switch 123. Terminal 121 is connected to the input of amplifier 130 and terminal 122 is connected to the output of amplifier 290. The switch 123 is connected to the antenna 110. Selector 120 connects antenna 110 to the input of amplifier 130 or the output of amplifier 290 by switching switch 123 between terminals 121 and 122 based on signal SLT 1 from controller 210. More specifically, the selector 120 connects the switch 123 to the terminal 121 in response to an H (logic high) level signal SLT1 from the controller 210, and generates an L (logic low) level signal SLT1 from the controller 210. Accordingly, the switch 123 is connected to the terminal 122.

  The amplifier 130 receives the received radio wave received by the antenna 110 via the selector 120, amplifies the received received radio wave, and outputs the amplified radio wave to the mixer 140. The mixer 140 mixes the received radio wave from the amplifier 130 and the clock signal CLK_PAT from the clock adjuster 170 and outputs the mixed signal to the low-pass filter 150.

  Low-pass filter 150 removes high-frequency noise from the radio wave from mixer 140 and outputs a baseband signal to demodulator 160 and carrier detector 180. The demodulator 160 detects a frequency shift signal of the baseband signal and outputs the detected frequency shift signal to the clock adjuster 170 and the A / D converter 190. Demodulator 160 demodulates the baseband signal and outputs the demodulated data DATA to controller 210.

  The clock adjuster 170 estimates the carrier frequency of the other party of communication according to the frequency shift signal from the demodulator 160, generates a clock signal CLK_PAT having the estimated carrier frequency, and outputs it to the mixer 140 and the selector 240 To do. Carrier detector 180 detects the end of data reception based on the baseband signal from low-pass filter 150, generates signal DETF indicating the end of data reception, and outputs the signal DETF to controller 210.

  The A / D converter 190 converts the frequency shift signal from the demodulator 160 from an analog signal to a digital signal and outputs the data FSHT to the controller 210. Counter 200 receives signal DETS and signal DTF from controller 210 at terminals GTE1 and GTE2, respectively, and receives clock signal CLK_SEF from clock generator 230 at terminal CLKIN. The counter 200 starts counting the number of components of the clock signal CLK_SEF received at the terminal CLKIN when receiving the signal DTF at the terminal GTE2, and ends the counting when receiving the signal DETS at the terminal GTE1. Then, the counter 200 outputs the count value CNT from the terminal Q to the controller 210.

  When the transmitter 10 receives data, the controller 210 generates an H level signal SLT1 and outputs the signal from the terminal SEL1 to the selector 120. When the transmitter 10 transmits data, the controller 210 generates an L level signal SLT1. Output from the terminal SEL1 to the selector 120.

  Further, when the transmitter 10 receives data, the controller 210 generates an H level signal SLT2 and outputs the signal from the terminal SEL2 to the selector 240. When the transmitter 10 transmits data, the controller 210 transmits an L level signal SLT2. Is output from the terminal SEL2 to the selector 240.

  Further, when the controller 210 receives the signal DETF from the carrier detector 180 at the terminal CDET, the controller 210 measures a certain time by counting the number of components of the divided clock signal CLK_B from the 1 / N frequency divider 250. Then, the controller 210 outputs data from the terminal TDA to the modulator 260 when a certain time elapses.

  Further, when the data transmission is completed, the controller 210 generates a signal DTF indicating that the data transmission is completed, and outputs the signal DTF to the counter 200 from the terminal TFH.

  Further, the controller 210 receives the data DATA from the demodulator 160 at the terminal RDA, detects the timing when the data DATA starts to be stably received by a method described later based on the received data DATA, and stabilizes the data DATA. Then, a signal DETS indicating that reception has started is generated and output to the counter 200 from the terminal RDS.

  Further, when data FSHT is received at terminal RDIF from A / D converter 190 in data communication after the end of IFS, controller 210 detects that the communication partner is moving, and communicates with the communication partner in IFS. The change in distance is measured by the method described later.

  Furthermore, the controller 210 transmits the data DATA received from the terminal RDA to a personal computer (not shown) via the terminal HOSTIF.

  The crystal oscillator 220 generates a predetermined periodic signal and outputs it to the clock generator 230. The clock generator 230 generates a clock signal CLK_SEF based on the periodic signal from the crystal oscillator 220 and outputs the generated clock signal CLK_SEF to the counter 200 and the selector 240.

  The selector 240 includes terminals 241 and 242 and a switch 243. The terminal 241 is connected to the clock adjuster 170. Terminal 242 is connected to clock generator 230. The switch 243 is connected to the 1 / N frequency divider 250 and the mixer 280. Upon receiving the H level signal SLT2 from the controller 210, the selector 240 connects the switch 243 to the terminal 241 and outputs the clock signal CLK_PAT from the clock adjuster 170 to the 1 / N frequency divider 250 and the mixer 280. . When the selector 240 receives the L level signal SLT2 from the controller 210, the selector 240 connects the switch 243 to the terminal 242 and outputs the clock signal CLK_SEF from the clock generator 230 to the 1 / N frequency divider 250 and the mixer 280. .

  The 1 / N divider 250 divides the clock signal CLK_PAT or CLK_SEF from the selector 240 by 1 / N and outputs the divided clock signal CLK_B to the controller 210.

  Modulator 260 modulates data from controller 210 with a predetermined modulation frequency, and outputs the modulated data to low-pass filter 270. The low pass filter 270 converts the modulation data from the modulator 260 into a baseband signal and outputs the baseband signal to the mixer 280.

  The mixer 280 mixes the baseband signal from the low pass filter 270 and the clock signal CLK_PAT or CLK_SEF from the selector 240 and outputs the mixed signal to the amplifier 290. The amplifier 290 amplifies the output of the mixer 280 and outputs it to the selector 120.

  Note that the receiver 30 shown in FIG. 1 also has the same configuration as the transmitter 10 shown in FIG.

  FIG. 3 is a timing chart of transmission data and reception data. Hereinafter, a method for determining the communication distance between the transmitter 10 and the receiver 30 will be described. In FIG. 3, data DATT represents data that the transmitter 10 transmits to the receiver 30 via the wireless communication space 20, and data DARR is received from the transmitter 10 by the receiver 30 via the wireless communication space 20. The data DART represents the data that the receiver 30 transmits to the transmitter 10 via the wireless communication space 20, and the data DATR is received from the receiver 30 via the wireless communication space 20. Represents data to be processed.

  In the CSMA / CA scheme, when the transmitter 10 transmits one packet PKT_n−1 (n is a natural number), the transmitter 10 receives an acknowledgment after a waiting time τ1 + SIFS + τ2 including SIFS (Short Interframe Spacing). Then, after receiving an affirmative response, the transmitter 10 transmits the next packet PKT_n after a waiting time of DIFS (Distributed Interframe Spacing) and a waiting time of BACK_OFF have elapsed.

  In the present invention, the transmitter 10 measures the time during which data (one packet) reciprocates with the receiver 30 using a period in which communication is not performed in the wireless communication space 20 called SIFS. The communication distance with the receiver 30 is determined based on the round trip time.

  The transmitter 10 starts to transmit data DATT to the receiver 30 via the wireless communication space 20, and ends transmission of data DATT at timing t1. Then, the receiver 30 starts to receive the data DARR from the transmitter 10 via the wireless communication space 20, and the transmission end of the data DATT in the transmitter 10 is propagated to the receiver 30 at timing t2. That is, the time during which data is propagated from the transmitter 10 to the receiver 30 via the wireless communication space 20 is τ1.

  The receiver 30 waits until the SIFS elapses after the completion of reception of the data DARR from the transmitter 10, and transmits the data DART via the wireless communication space 20 at a timing t3 when the SIFS elapses. 10 starts transmission. Then, the transmitter 10 starts to receive the data DATR from the receiver 30 via the wireless communication space 20, and the transmission start of the data DART in the receiver 30 is propagated to the transmitter 10 at timing t4. Thereafter, the transmitter 10 detects the timing t6 at which the data DATR is stably received by the method described later, that is, the end position of the frame start portion.

  Since the timing at which the transmission start of the data DART in the receiver 30 is propagated to the transmitter 10 is the timing t4, the time during which the data is propagated from the receiver 30 to the transmitter 10 is the time from the timing t3 to the timing t4. However, in the present invention, the time τ3 from the timing t3 to the timing t4 is not set as the time when the data is propagated from the receiver 30 to the transmitter 10, but the timing t5 and the transmitter 10 change the data DATR. The time τ2 between the timing t6 at which reception starts stably is a time during which data is propagated from the receiver 30 to the transmitter 10. That is, the time at which the end position of the data frame start portion SFD is propagated from the receiver 30 to the transmitter 10 via the wireless communication space 20 is the time τ 2 at which the data is propagated from the receiver 30 to the transmitter 10. .

  The reason why the time τ2 from the timing t5 to the timing t6 is set as the time during which data is propagated from the receiver 30 to the transmitter 10 will be described later.

  As described above, the counter 200 of the transmitter 10 starts counting the number of components of the clock signal CLK_SEF when receiving the signal DTF at the terminal GTE2, and stops counting the number of components of the clock signal CLK_SEF when receiving the signal DETS at the terminal GTE1. To do. That is, the counter 200 counts the number of components of the clock signal CLK_SEF between the timing t1 and the timing t6.

  Then, by multiplying the count value CNT by the period length of the clock signal CLK_SEF, a total time Ttotal from timing t1 to timing t6 is obtained. As a result, the following equation is established.

Ttotal = τ1 + Tfix + τ2 (1)
Since the fixed time Tfix is measured by the controller 210 as described above, τ1 + τ2 is obtained by subtracting the fixed time Tfix from the total time Ttotal. This τ1 + τ2 is a round trip time in which the data travels back and forth between the transmitter 10 and the receiver 30.

  The fixed time Tfix measured in the receiver 30 is determined in advance between the transmitter 10 and the receiver 30 by the following equation, and the controller 210 of the transmitter 10 holds the determined fixed time Tfix. is doing. Therefore, the transmitter 10 can easily calculate the round-trip time τ1 + τ2 based on the equation (1).

  The fixed time Tfix is determined by the following equation.

Tfix = SIFS + SYNC + SFD (2)
From Expression (2), the fixed time Tfix is determined as the sum of SIFS (the response time of the receiver 30), the detection time of the synchronization signal unit SYNC, and the detection time of the frame start unit SFD.

  When the receiver 30 stops moving, the propagation time τ1 at which the end of data transmission at the transmitter 10 is propagated to the receiver 30 is the propagation time τ1 at which the data transmission start at the receiver 30 is propagated to the transmitter 10 Since it is equal to the time τ 2, half of the round-trip time τ 1 + τ 2 (τ 1 + τ 2) / 2 is the data propagation time between the transmitter 10 and the receiver 30.

  Therefore, the controller 210 of the transmitter 10 determines the communication distance between the transmitter 10 and the receiver 30 by multiplying the time (τ1 + τ2) / 2 by the speed of light c.

  As is apparent from FIG. 3, since the fixed time Tfix is a fixed value, the total time Ttotal is increased by the data propagation time τ1 + τ2.

  Therefore, the present invention determines the communication distance between the transmitter 10 and the receiver 30 by utilizing the fact that the total time Ttotal is increased by the data propagation time τ1 + τ2 between the transmitter 10 and the receiver 30. It is characterized by that.

  FIG. 4 is a diagram for explaining a method of detecting timing t6 at which the transmitter 10 starts to stably receive the data DATA from the receiver 30. A packet PKT, which is data DATA transmitted / received between the transmitter 10 and the receiver 30, includes a synchronization signal part SYNC, a frame start part SFD, and a frame part FRM. The synchronization signal part SYNC is provided at the head of the packet PKT. The frame start unit SFD is provided subsequent to the synchronization signal unit SYNC. The frame part FRM is provided subsequent to the frame start part SFD.

  The synchronization signal part SYNC is a field for arranging data for synchronization when data DATA is transmitted and received between the transmitter 10 and the receiver 30. The frame start part SFD is called a start frame delimiter (Start Frame Delimiter) and is a field indicating the start of the frame part FRM. The frame start unit SFD is composed of, for example, an 8-bit pattern of [10101011]. The frame part FRM is a field for arranging data to be transmitted / received.

  The transmitter 10 finishes transmitting the packet PKT having the above-described configuration to the receiver 30 at timing t1. Then, the transmitter 10 starts to receive the packet PKT from the receiver 30 at timing t4.

  As a result, the transmitter 10 receives the synchronization signal part SYNC and the frame start part SFD of the packet PKT during the period from the timing t4 to the timing t6. While the synchronization signal section SYNC is received, the data received by the transmitter 10 is discontinuous, and the receiving circuit (amplifier 130, mixer 140, demodulator 160, carrier detector 180, and controller 210) of the transmitter 10 The tuning is not achieved, the gain is unstable, and the synchronization data cannot be demodulated.

  However, as the reception of the synchronization signal unit SYNC is continued, that is, as the timing t6 is approached, the data gradually continues, the gain begins to stabilize, and the synchronization data can be demodulated. At the timing t6 when the reception of the frame start unit SFD ends, the receiving circuit (amplifier 130, mixer 140, demodulator 160, carrier detector 180, and controller 210) of the transmitter 10 is tuned.

  Therefore, in the present invention, the timing t6 at which the reception of the frame start unit SFD ends is set as the timing at which the transmitter 10 starts to receive data from the receiver 30 stably.

  Then, the controller 210 of the transmitter 10 receives the data DATA from the demodulator 160 and detects the end position of the frame start unit SFD based on the received data DATA. More specifically, since the frame start unit SFD is composed of the 8-bit pattern of [10101011] as described above, the controller 210 detects [11] which is the last 2 bits of this 8-bit pattern from the data DATA. As a result, the end position of the frame start unit SFD is detected.

  When the controller 210 detects the end position of the frame start unit SFD, the controller 210 generates a signal DETS and outputs the signal DETS to the counter 200 from the terminal RDS.

  Thus, during the period of receiving the synchronization signal part SYNC of the packet PKT, the receiving circuit (amplifier 130, mixer 140, demodulator 160, carrier detector 180 and controller 210) of the transmitter 10 is not tuned and gain Is unstable, and the synchronous data cannot be demodulated. When the receiver 30 is far away from the transmitter 10, the reception of data from the receiver 30 becomes more unstable during the period of receiving the synchronization signal part SYNC.

  However, even when the receiver 30 is far away from the transmitter 10, at the timing t6 when the transmitter 10 detects the end position of the frame start unit SFD, the receiver circuit (amplifier 130, mixer 140, demodulator 160) of the transmitter 10 is detected. Since the carrier detector 180 and the controller 210) are tuned, the transmitter 10 can stably receive data from the receiver 30.

  Therefore, in the present invention, the time τ2 from the timing t5 to the timing t6 is set as the time for the data to propagate from the receiver 30 to the transmitter 10.

  FIG. 5 is a flowchart for explaining the operation of determining the communication distance between the transmitter 10 and the receiver 30. When a series of operations is started, the controller 210 of the transmitter 10 generates an L level signal SLT1 and outputs it to the selector 120, and generates an L level signal SLT2 and outputs it to the selector 240. Then, the selector 120 connects the switch 123 to the terminal 122 in accordance with the L level signal SLT1. The selector 240 connects the switch 243 to the terminal 242 in response to the L level signal SLT2.

  On the other hand, the controller 210 of the receiver 30 generates an H level signal SLT1 and outputs it to the selector 120, and generates an H level signal SLT2 and outputs it to the selector 240. Then, the selector 120 connects the switch 123 to the terminal 121 in accordance with the H level signal SLT1. The selector 240 connects the switch 243 to the terminal 241 in response to the H level signal SLT2.

  The controller 210 of the transmitter 10 outputs data from the terminal TDA to the modulator 260. The modulator 260 modulates the data from the controller 210 with a predetermined modulation frequency and outputs the modulated data to the low pass filter 270. The low pass filter 270 removes high frequency noise from the modulation data and outputs a baseband signal to the mixer 280.

  The crystal oscillator 220 of the transmitter 10 generates a predetermined periodic signal and outputs it to the clock generator 230. The clock generator 230 generates a clock signal CLK_SEF based on the periodic signal and outputs it to the counter 200 and the selector 240. Then, the selector 240 outputs the clock signal CLK_SEF to the 1 / N frequency divider 250 and the mixer 280. The mixer 280 mixes the baseband signal from the low pass filter 270 and the clock signal CLK_SEF from the selector 240 and outputs the mixed signal to the amplifier 290. That is, the mixer 280 outputs the baseband signal to the amplifier 290 in synchronization with the clock signal CLK_SEF. The amplifier 290 amplifies the output of the mixer 280 and outputs it to the selector 120. The selector 120 transmits the output of the amplifier 290 via the antenna 110. Thereby, transmission of the data to the receiver 30 is started (step S1).

  Thereafter, the data is transmitted to the receiver 30 via the wireless communication space 20, and when the transmission of data in the transmitter 10 is completed (step S2), the controller 210 of the transmitter 10 generates a signal DTF and sends it to the counter 200. Output. When the counter 200 receives the signal DTF at the terminal GTE2, the counter 200 starts counting the number of components of the clock signal CLK_SEF (step S3).

  Data transmitted from the transmitter 10 is transmitted to the receiver 30 via the wireless communication space 20. The antenna 110 of the receiver 30 supplies data received via the wireless communication space 20 to the amplifier 130 via the selector 120. The amplifier 130 amplifies the data supplied from the selector 120 and outputs the amplified data to the mixer 140. The mixer 140 mixes the output of the amplifier 130 and the clock signal CLK_PAT from the clock adjuster 170 and outputs the mixed signal to the low-pass filter 150. That is, the mixer 140 outputs the baseband signal to the low-pass filter 150 in synchronization with the clock signal CLK_PAT. The low pass filter 150 removes high frequency noise from the output of the mixer 140 and outputs a baseband signal to the demodulator 160 and the carrier detector 180.

  The demodulator 160 detects a frequency shift signal of the baseband signal and outputs the detected frequency shift signal to the clock adjuster 170 and the A / D converter 190. Demodulator 160 demodulates the baseband signal and outputs the demodulated data DATA to controller 210. The clock adjuster 170 estimates the carrier frequency of the transmitter 10 according to the frequency shift signal from the demodulator 160, generates a clock signal CLK_PAT having the estimated carrier frequency, and outputs it to the mixer 140 and the selector 240. . As a result, the receiver 30 receives the data DATA in synchronization with the clock signal CLK_SEF generated in the transmitter 10 that is the communication partner (step S4).

  Based on the baseband signal from the low-pass filter 150, the carrier detector 180 of the receiver 30 detects the end of data reception (step S5) and generates a signal DETF indicating the end of data reception. And output to the controller 210.

  On the other hand, the controller 210 of the receiver 30 generates an L-level signal SLT 1 and outputs it to the selector 120. The selector 120 connects the switch 123 to the terminal 122 according to the L level signal SLT1. The selector 240 also outputs the clock signal CLK_PAT from the clock adjuster 170 to the 1 / N frequency divider 250 and the mixer 280. The 1 / N frequency divider 250 divides the clock signal CLK_PAT by 1 / N and outputs the divided clock signal CLK_B to the controller 210.

  When controller 210 receives signal DETF from carrier detector 180 at terminal CDET, controller 210 counts the number of components of divided clock signal CLK_B received at terminal MCLK and measures SIFS for a certain period of time. That is, the receiver 30 waits for a certain time SIFS for data transmission (step S6).

  In this way, the receiver 30 measures SIFS for a certain time based on the clock signal CLK_PAT having the carrier frequency of the transmitter 10 estimated by the clock adjuster 170.

  When SIFS elapses for a certain time, the controller 210 of the receiver 30 outputs data to the modulator 260 from the terminal TDA. The modulator 260 modulates data with a predetermined modulation frequency. The low pass filter 270 removes high frequency noise from the modulation data and outputs a baseband signal to the mixer 280. The mixer 280 mixes the baseband signal from the low pass filter 270 and the clock signal CLK_PAT from the selector 240 and outputs the mixed signal to the amplifier 290. That is, the mixer 280 outputs the baseband signal to the amplifier 290 in synchronization with the clock signal CLK_PAT. The amplifier 290 amplifies the output of the mixer 280 and outputs it to the selector 120. The selector 120 transmits the output of the amplifier 290 via the antenna 110. Thereby, transmission of data from the receiver 30 to the transmitter 10 is started (step S7).

  Thus, the receiver 30 transmits and receives data from the transmitter 10 in synchronization with the clock signal CLK_PAT having the same carrier frequency as the carrier frequency in the transmitter 10.

  Thereafter, the controller 210 of the transmitter 10 generates an H level signal SLT 1 and outputs the signal SLT 1 to the selector 120. The selector 120 connects the switch 123 to the terminal 121 in accordance with the H level signal SLT1.

  Then, the antenna 110 of the transmitter 10 supplies the data received via the wireless communication space 20 to the amplifier 130 via the selector 120. The amplifier 130 amplifies the data supplied from the selector 120 and outputs the amplified data to the mixer 140. The mixer 140 mixes the output of the amplifier 130 and the clock signal CLK_PAT from the clock adjuster 170 and outputs the mixed signal to the low-pass filter 150. The low pass filter 150 removes high frequency noise from the output of the mixer 140 and outputs a baseband signal to the demodulator 160.

  Demodulator 160 demodulates the baseband signal and outputs the demodulated data DATA to controller 210. Then, controller 210 detects the end position of frame start unit SFD based on the data DATA received from demodulator 160 by the method described above. Thereby, the transmitter 10 starts receiving data DATA from the receiver 30 (step S8).

  When the controller 210 detects the end position of the frame start unit SFD, the controller 210 generates a signal DETS indicating that data reception has started, and outputs the signal DETS to the counter 200.

  When the counter 200 receives the signal DETS from the controller 210 to the terminal GTE1, the counter 200 finishes counting the number of components of the clock signal CLK_SEF and outputs the count value CNT from the terminal Q to the controller 210. When controller 210 receives count value CNT at terminal TAV, controller 210 calculates the cycle length of clock signal CLK_SEF based on frequency-divided clock signal CLK_B (in transmitter 10, frequency-divided clock signal CLK_B divides clock signal CLK_SEF. The total time Ttotal is calculated by multiplying the calculated cycle length by the count value CNT (step S9).

  When the controller 210 calculates the total time Ttotal, the controller 210 calculates the round trip time τ1 + τ2 by subtracting the fixed time Tfix from the total time Ttotal. The controller 210 determines the communication distance between the transmitter 10 and the receiver 30 by multiplying the half of the round trip time τ1 + τ2 (τ1 + τ2) / 2 by the speed of light c (step S10).

  Thereby, a series of operations are completed.

  As described above, the receiver 30 measures SIFS for a certain period of time based on the clock signal CLK_PAT having the carrier frequency of the transmitter 10 that is the communication partner (see step S6). The receiver 30 transmits and receives data from the transmitter 10 in synchronization with the clock signal CLK_PAT having the same carrier frequency as the carrier frequency in the transmitter 10 (see steps S4 and S7).

  Therefore, the data reception end timing, the fixed time SIFS length, and the data transmission start timing in the receiver 30 can be determined in synchronization with the clock signal CLK_SEF generated in the transmitter 10, and the transmitter 10 The total time Ttotal = τ1 + Tfix + τ2 can be accurately measured. As a result, the communication distance between the transmitter 10 and the receiver 30 can be accurately determined.

  Further, when the transmitter 10 detects the end position of the frame start unit SFD included in the data DATA from the receiver 30, the transmitter 10 ends the measurement of the total time Ttotal (see step S9), so the total time Ttotal is accurately determined. it can. That is, even when the receiver 30 is far from the transmitter 10, the transmitter 10 can accurately determine the timing to start receiving data from the receiver 30, and the data propagates from the receiver 30 to the transmitter 10. The propagation time τ2 can be accurately determined. Then, the total time Ttotal can be accurately determined.

  As a result, the communication distance between the transmitter 10 and the receiver 30 can be accurately determined.

  The fixed time Tfix may be set to a PIFS longer than the SIFS in the wireless LAN system using the CSMA_CA method.

  Since SIFS and PIFS are fixed time fixed for each terminal connected to the wireless LAN system, the communication distance between the transmitter 10 and the receiver 30 can be accurately determined by using SIFS or PIFS as the fixed time Tfix. Can be determined.

  The transmitter 10 determines the communication distance with the receiver 30 by the above-described method using the period (IFS) in which communication is not performed in the wireless communication space 20, that is, after the idle period ends, Data communication is performed with the receiver 30, and it is determined whether or not the phase of data transmitted to the receiver 30 is shifted from the phase of data received from the receiver 30. Then, when the phase of the data transmitted to the receiver 30 is shifted from the phase of the data received from the receiver 30, the transmitter 10 determines that the receiver 30 is moving, and the receiver 30 in the idle period. Measure the change in communication distance with.

  More specifically, the transmitter 10 transmits data to the receiver 30 in synchronization with the clock signal CLK_SEF generated by itself by the method described above. Then, the receiver 30 transmits the data received from the transmitter 10 to the transmitter 10 in synchronization with the clock signal CLK_SEF generated by itself. During normal data communication, the receiver 30 transmits data in synchronization with the clock signal CLK_SEF generated by itself instead of the clock signal CLK_SEF (= CLK_PAT) generated by the transmitter 10 that is the communication partner. .

  The clock signal CLK_SEF generated in the transmitter 10 is referred to as a clock signal CLK_SEF_T, and the clock signal CLK_SEF generated in the receiver 30 is referred to as a clock signal CLK_SEF_R. Further, data transmitted from the transmitter 10 to the receiver 30 in synchronization with the clock signal CLK_SEF_T is DATA_T, and data transmitted from the receiver 30 to the transmitter 10 in synchronization with the clock signal CLK_SEF_R is DATA_R.

  As a result, the transmitter 10 transmits data DATA_T to the receiver 30 and receives data DATA_R from the receiver 30. Then, the transmitter 10 determines whether or not the phase of the data DATA_T is shifted from the phase of the data DATA_R.

  That is, the demodulator 160 of the transmitter 10 detects a frequency shift signal of the data DATA_R received from the receiver 30, that is, a phase shift of the data DATA_R, and outputs it to the A / D converter 190. A / D converter 190 converts the phase shift from demodulator 160 from an analog signal to a digital signal, and outputs data FSHT to controller 210. Accordingly, the A / D converter 190 generates the phase shift data FSHT and outputs it to the controller 210.

  Controller 210 detects that a phase shift has occurred in data DATA_R by receiving data FSHT at terminal RDIF. Then, when a phase shift occurs in the data DATA_R, the controller 210 measures a change in the communication distance with the receiver 30 during the idle period by the following method.

  When the receiver 30 stops moving, the propagation time τ1 is equal to the propagation time τ2, and therefore, when the total time is Ttotal1, the round-trip time for data to reciprocate between the transmitter 10 and the receiver 30 is 2τ1. = A (= Ttotal1-Tfix). Further, when the receiver 30 is moving and the total time is Ttotal2, the round-trip time for data to reciprocate between the transmitter 10 and the receiver 30 is expressed as τ1 + τ2 = b (= Ttotal2-Tfix). Can do.

  Therefore, from these two expressions, | τ1−τ2 | = | a−b |, and the change in the communication distance between the transmitter 10 and the receiver 30 during the idle period is | a−b | × c.

  The controller 210 stores the round-trip time a when the receiver 30 is stopped. When it is determined that the receiver 30 is moving, the communication distance as described above using the measured round-trip time b. Change | a−b | × c.

  Note that determining that the phase of the data DATA_R received from the receiver 30 is out of phase with the phase of the data DATA_T transmitted to the receiver 30 means that the phase of the clock signal CLK_SEF_R generated by the receiver 30 is determined by the transmitter 10. This corresponds to determining that the phase of the generated clock signal CLK_SEF_T is out of phase. This is because the data DATA_R is synchronized with the clock signal CLK_SEF_R, and the data DATA_T is synchronized with the clock signal CLK_SEF_T.

  In general, the modulation frequency for modulating data is equal to the carrier frequency (carrier frequency) of the clock signals CLK_SEF and CLK_PAT, but the modulation frequency may be different from the carrier frequency. CLK_SEF and CLK_PAT may be generated based on either the modulation frequency or the carrier frequency.

  FIG. 6 is a diagram illustrating the relationship between communication idle time and communication distance. In FIG. 6, the vertical axis represents the measured communication idle time, and the horizontal axis represents the measured communication distance. The communication distance is a communication distance between the transmitter 10 and the receiver 30 measured by the method described above.

  As shown in FIG. 6, the idle time of communication becomes longer according to the communication distance between the transmitter 10 and the receiver 30. More specifically, the communication idle time becomes longer in proportion to the communication distance in the range where the communication distance between the transmitter 10 and the receiver 30 is up to 350 m.

  As described above, the communication idle time Ttotal is expressed by τ1 + Tfix + τ2, and changes according to the data propagation time τ1 + τ2 between the transmitter 10 and the receiver 30. The propagation time τ1 + τ2 changes in proportion to the communication distance between the transmitter 10 and the receiver 30. As a result, the communication idle time Ttotal changes in proportion to the communication distance between the transmitter 10 and the receiver 30.

  Therefore, the actually measured communication idle time reflects that the data propagation time τ1 + τ2 has become longer according to the communication distance.

  Further, even when the receiver 30 is far from the transmitter 10 by about 350 m, the communication idle time becomes longer according to the communication distance, and the timing at which the transmitter 10 starts to receive data from the receiver 30. It is understood that the communication idle time can be measured accurately by setting the timing t6 to detect the end position of the frame start unit SFD.

  In the present invention, measuring the time from the timing t1 at which the transmission of data from the transmitter 10 to the receiver 30 is completed to the timing t6 at which the end position of the frame start unit SFD is detected is from the transmitter 10. Equivalent to measuring the total time between the first timing at which data transmission to the receiver 30 is completed and the second timing at which the transmitter 10 starts to stably receive data from the receiver 30. To do.

  The timing t6 corresponds to the reception end timing of the frame start unit SFD (= frame start delimiter) which is a signal indicating the start of the frame (frame unit FRM).

[Embodiment 2]
In the first embodiment, the distance between the transmitter 10 and the receiver 30 is measured on the assumption that the phase of the clock signal generated by the transmitter 10 and the phase of the clock signal generated by the receiver 30 are equal. The method was explained.

  However, in practice, the phase of the clock signal generated by the transmitter 10 and the phase of the clock signal generated by the receiver 30 may be shifted. In such a case, SIFS is not constant, and the distance between the transmitter 10 and the receiver 30 cannot be measured accurately.

  FIG. 7 is a diagram illustrating a change in the sampling timing of the received signal when the phase of the clock signal generated by the receiver 30 is shifted from the phase of the clock signal generated by the transmitter 10.

  The receiver 30 receives the reception signal RD, and transmits the transmission signal TD to the transmitter 10 after SIFS has elapsed. In this case, when the phase of the clock signal generated in the receiver 30 is shifted from the phase of the clock signal generated in the transmitter 10, SIFS is not constant.

  SIFS corresponds to the time length between the timing tf at which the reception signal RD is received and the timing ti at which the transmission signal TD starts to be transmitted. The reception signal RD_F is a signal indicating the end portion of the reception signal RD.

  Each of clock signals CLK <b> 1 to CLKN (N is a positive integer) is a clock signal generated in receiver 30, and its phase is shown with respect to the phase of the clock signal generated in transmitter 10. . Therefore, in FIG. 7, the clock signals CLK <b> 1 to CLKN generated in the receiver 30 indicate that the phase changes variously with respect to the phase of the clock signal generated in the transmitter 10.

  When the reception signal RD_F is sampled in synchronization with the clock signal CLK1, the end timing tf of the reception signal RD_F is detected by the sampling timing ST1. When the reception signal RD_F is sampled in synchronization with the clock signal CLK2, the end timing tf of the reception signal RD_F is detected by the sampling timing ST2. Furthermore, when the reception signal RD_F is sampled in synchronization with the clock signal CLKN, the end timing tf of the reception signal RD_F is detected by the sampling timing STN.

  Accordingly, when the phase of the clock signals CLK1 to CLKN generated in the receiver 30 changes variously with respect to the phase of the clock signal generated in the transmitter 10, the detection timing of the end timing tf of the reception signal RD_F changes variously. SIFS is not constant. As a result, the distance between the transmitter 10 and the receiver 30 cannot be measured accurately.

  Therefore, in the second embodiment, even when the phase of the clock signal generated in the receiver 30 is shifted from the phase of the clock signal generated in the transmitter 10, the transmitter 10 and the receiver 30 A method for accurately measuring the distance between the two will be described.

  FIG. 8 is a schematic block diagram showing a configuration of a receiver 30A according to the second embodiment. The receiver 30A according to the second embodiment is different from the carrier detector 180 and the 1 / N frequency divider 250 in the configuration of the receiver 30 according to the first embodiment (see FIG. 2). The configuration is the same as that shown in FIG.

  The carrier detector 180A, based on the baseband signal received from the low-pass filter 150, uses a method described later, and the phase difference of the clock signal CLK_SEF_R generated in the receiver 30A with respect to the phase of the clock signal CLK_SEF_T generated in the transmitter 10 While detecting θd, it is detected that the reception of data has been completed.

  The carrier detector 180A outputs the detected phase difference θd to the 1 / N frequency divider 250A, generates a signal DETF indicating that reception of data has been completed, and outputs the signal DETF to the controller 210.

  The 1 / N frequency divider 250A divides the clock signal CLK_PAT or CLK_SEF from the selector 240 by 1 / N, and the phase difference received from the carrier detector 180A is the phase of the frequency-divided clock signal CLK_B. The phase of the divided clock signal CLK_B is advanced by θd so as to match the phase of the clock signal CLK_SEF_T generated in the transmitter 10. Then, 1 / N frequency divider 250 </ b> A outputs frequency-divided clock signal CLK_BT having the same phase to controller 210.

  FIG. 9 is a diagram for explaining a method of detecting the phase difference θd of the clock signal CLK_SEF_R generated in the receiver 30A with respect to the phase of the clock signal CLK_SEF_T generated in the transmitter 10.

  The receiver 30A receives the reception data DARR from the transmitter 10. Then, the carrier detector 180A of the receiver 30A samples the reception data DARR from the low-pass filter 150 in synchronization with the clock signal CLK_SEF_R1, and detects the end of reception of the reception data DARR at the sampling timing ST1.

  The reception data DARR is data modulated by QPSK (Quadrature Phase Shift Keying). Therefore, when the phase of the clock signal CLK_SEF_R1 generated in the receiver 30A matches the phase of the clock signal CLK_SEF_T generated in the transmitter 10, the sampling timing for detecting the end of reception of the reception data DARR is the reception data DARR. Coincides with the end timing t_df.

  However, since the phase of the clock signal CLK_SEF_R1 is actually shifted from the phase of the clock signal CLK_SEF_T, the sampling timing ST1 for detecting the end of the reception data DARR does not coincide with the end timing t_df of the reception data DARR.

  Therefore, the carrier detector 180A represents the received data DARR by sin (ωt + θd), and determines the phase difference θd so that sin (ωt + θd) matches the actually received data DARR. Thereby, the carrier detector 180A detects the phase difference θd. In FIG. 9, the phase difference θd is θd1.

  When the carrier detector 180A detects the phase difference θd, the carrier detector 180A outputs the detected phase difference θd to the 1 / N frequency divider 250A. The 1 / N frequency divider 250A divides the clock signal CLK_SEF_R1 from the selector 240 by 1 / N to generate a divided clock signal CLK_B, and the phase of the generated divided clock signal CLK_B is detected by the carrier detector. The divided clock signal CLK_BT is generated by advancing by the phase difference θd1 received from 180A. As a result, a divided clock signal CLK_BT that matches the phase of the clock signal CLK_SEF_T generated in the transmitter 10 is generated.

  When the clock signal generated in the receiver 30A is the clock signal CLK_SEF_R2, the carrier detector 180A detects the phase difference θd2 by the method described above. Then, the 1 / N frequency divider 250A advances the phase of the divided block signal CLK_B by the phase difference θd2 and generates the divided clock signal CLK_BT.

  FIG. 10 is a signal space diagram of data modulated by QPSK. In FIG. 10, the horizontal axis represents the in-phase component I of the phase, and the vertical axis represents the quadrature component Q of the phase. When the phase of the clock signal CLK_SEF_R generated in the receiver 30A is not shifted from the phase of the clock signal CLK_SEF_T generated in the transmitter 10, the received data DARR is a component SS1 present at the four vertices of the square 1 ~ SS4.

  However, when the phase of the clock signal CLK_SEF_R is shifted from the phase of the clock signal CLK_SEF_T, the reception data DARR is composed of components SS′1 to SS′4 present at the four vertices of the square 2. The diagonal 4 of the square 2 is offset from the diagonal 3 of the square 1. Therefore, the difference between the angle of the diagonal line 3 with respect to the horizontal axis and the angle of the diagonal line 4 with respect to the horizontal axis is the phase difference θd.

  Therefore, the carrier detector 180A holds the signal space diagram shown in FIG. 10, plots the components of the received data DARR received from the transmitter 10 in the signal space diagram, and calculates the angle of the diagonal line 3 and the angle of the diagonal line 4 May be detected as the phase difference θd.

  As described above, the carrier detector 180A has the phase difference θd of the clock signal CLK_SEF_R generated in the receiver 30A with respect to the phase of the clock signal CLK_SEF_T generated in the transmitter 10 by one of the two methods described above. Is detected.

  FIG. 11 is another timing chart of transmission data and reception data. When the phase of the clock signal CLK_SEF_R matches the phase of the clock signal CLK_SEF_T, SIFS is equal to the time length between the timing t2 and the timing t3.

  However, when the phase of the clock signal CLK_SEF_R is shifted from the phase of the clock signal CLK_SEF_T, the SIFS is extended to the time length SIFS_diff between the timing t2 and the timing t7.

  Then, the start frame delimiter timing that is the end timing of the frame start unit SFD included in the transmission data DART transmitted from the receiver 30A to the transmitter 10 is shifted from the timing t5 to the timing t9. As a result, the timing at which the transmitter 10 starts to stably receive the reception data DATR from the receiver 30A is shifted from the timing t6 to the timing t10, and the transmitter 10 receives the reception data after completing the transmission of the transmission data DATT. The time τ1 + Tfix_diff + τ2 until the DATR is stably received is measured.

  In this case, the time length from timing t5 to timing t9 is equal to the time length from timing t6 to timing t10, and is the time length td (= θd / ω) corresponding to the above-described phase difference θd. Further, the time length from the timing t3 to the timing t7 is also equal to the time length td.

  Since the transmitter 10 grasps the fixed time including the response time in the receiver 30A as Tfix, even if the fixed time Tfix is subtracted from the time τ1 + Tfix_diff + τ2, the round trip time τ1 + τ2 between the transmitter 10 and the receiver 30A is obtained. I can't ask for it. As is apparent from FIG. 11, Tfix_diff = Tfix + td, and the fixed time Tfix_diff changes according to the phase difference θd (= ωtd) between the phase of the clock signal CLK_SEF_T and the phase of the clock signal CLK_SEF_R.

  Therefore, as described above, in the receiver 30A, the 1 / N frequency divider 250A advances the phase by the phase difference θd (corresponding to the time td on the time axis) detected by the carrier detector 180A, and the divided clock signal When the controller 210 receives the signal DETF from the carrier detector 180A, it generates the CLK_BT (clock signal that matches the phase of the clock signal CLK_SEF_T generated by the transmitter 10), and counts the number of components of the divided clock signal CLK_BT. And measure a certain time.

  Then, the controller 210 of the receiver 30A transmits the data to the transmitter 10 after measuring for a certain time, so that the transmitter 10 starts to receive the reception data DATR stably at the timing t6. As a result, the time from the completion of transmission of the transmission data DATT measured by the transmitter 10 to the start of reception of the reception data DATR is τ1 + Tfix + τ2, and the transmitter 10 subtracts the fixed time Tfix from the time τ1 + Tfix + τ2 to transmit the data to the transmitter The round-trip time for reciprocating between 10 and the receiver 30A is τ1 + τ2. Then, the distance between the transmitter 10 and the receiver 30A can be accurately measured by the method described in the first embodiment.

  FIG. 12 is a flowchart for explaining the operation of determining the communication distance between transmitter 10 and receiver 30A in the second embodiment. The flowchart shown in FIG. 12 is the same as the flowchart shown in FIG. 5 except that step S6 of the free chart shown in FIG. 5 is replaced with steps S6A, S6B, and S6C.

  When the carrier detector 180A of the receiver 30A detects the end of data reception (step S5), the phase of the clock signal CLK_SEF_T in the transmitter 10 and the phase of the clock signal CLK_SEF_R in the receiver 30A are determined by the method described above. Is detected (step S6A), and the detected phase difference θd is output to the 1 / N frequency divider 250A. Further, carrier detector 180A generates a signal DETF indicating that the reception of data has been completed and outputs the signal DETF to controller 210.

  The 1 / N frequency divider 250A divides the clock signal CLK_SEF from the selector 240 by a factor of N to generate a divided clock signal CLK_B, and the phase of the generated divided clock signal CLK_B is set to a phase difference θd. And the divided clock signal CLK_BT is generated (step S6B). Then, the 1 / N frequency divider 250 </ b> A outputs the divided clock signal CLK_BT to the terminal MCLK of the controller 210.

  When controller 210 receives signal DETF from carrier detector 180A at terminal CDET, controller 210 counts the number of components of divided clock signal CLK_BT received at terminal MCLK, and measures response time SIFS. That is, the receiver 30A waits for the response time SIFS based on the divided clock signal CLK_BT (step S6C).

  Thereafter, steps S7 to S10 described in the first embodiment are executed, and the distance between the transmitter 10 and the receiver 30A is determined.

[Another method 1 for accurately measuring the distance between transceivers]
In the above, the transmitter 10 and the receiver 30A are adjusted by adjusting the phase difference between the phase of the clock signal CLK_SEF_R generated in the receiver 30A and the phase of the clock signal CLK_SEF_T generated in the transmitter 10 in the receiver 30A. A method for accurately measuring the distance between the two has been described.

  In the second embodiment, a time length td corresponding to the phase difference θd detected by the receiver 30A is transmitted to the transmitter 10, and the transmitter 10 accurately obtains the round trip time τ1 + τ2 based on the time length td. May be.

  In this case, the receiver includes a receiver 30B shown in FIG. FIG. 13 is another schematic block diagram showing the configuration of the receiver according to the second embodiment. The receiver 30B according to the second embodiment is obtained by replacing the carrier detector 180 and the controller 210 with the carrier detector 180B and the controller 210A, respectively, in the configuration of the receiver 30 according to the first embodiment (see FIG. 2). Others are the same as the structure shown in FIG.

  The carrier detector 180B detects the phase difference θd by the same method as the carrier detector 180A based on the received data from the low-pass filter 150, outputs the detected phase difference θd to the controller 210A, and receives received data. Is generated and output to the controller 210A.

  Controller 210A receives signal DETF and phase difference θd from carrier detector 180B at terminal CDET. Then, the controller 210A converts the phase difference θd into a time length td = θd / ω. When the controller 210A receives the signal DETF at the terminal CDET, it measures the response time SIFS_diff by the same method as the controller 210 shown in FIG. 2, measures the response time SIFS_diff, and then converts the data DART and the time length td into the modulator 260. , Low-pass filter 270, mixer 280, amplifier 290, selector 120 and antenna 110 for transmission to transmitter 10.

  In this case, the data DART and the time length td are transmitted to the transmitter 10 in synchronization with the clock signal CLK_SEF_R generated in the receiver 30B.

  The transmitter 10 receives the data DATR and the time length td from the receiver 30B, and measures the time τ1 + Tfix_diff + τ2 (see FIG. 11) from the end of transmission of the data DATT to the start of stable reception of the data DATR. . Then, the transmitter 10 adds the received time length td to the fixed time Tfix including the response time in the receiver 30B that it knows, and subtracts the addition result Tfix + td from the time τ1 + Tfix_diff + τ2.

  In this case, as apparent from FIG. 11, since Tfix_diff = Tfix + td, the round trip time τ1 + τ2 is obtained by subtracting the addition result Tfix + td from the time τ1 + Tfix_diff + τ2.

  Therefore, the transmitter 10 calculates the round trip time τ1 + τ2 between the transmitter 10 and the receiver 30B by subtracting the addition result Tfix + td from the time τ1 + Tfix_diff + τ2.

  Thereafter, the transmitter 10 calculates the distance between the transmitter 10 and the receiver 30B by the method described in the first embodiment.

  Note that adding the time length td received by the transmitter 10 from the receiver 30B to the fixed time Tfix and subtracting the addition result from the time τ1 + Tfix_diff + τ2 means that the phase of the clock signal CLK_SEF_R matches the phase of the clock signal CLK_SEF_T. Constant including the response time SIFS_diff measured in the receiver 30B based on the time length td so that the response time (SIFS_diff) measured in the receiver 30B matches the response time (SIFS) in the receiver 30B. This corresponds to adjusting the time Tfix_diff and subtracting the adjusted fixed time from the time τ1 + Tfix + τ2 (= total time) to calculate the round-trip time τ1 + τ2.

  When the round trip time τ1 + τ2 is obtained from the time τ1 + Tfix_diff + τ2 measured by the transmitter 10 in synchronization with the clock signal CLK_SEF_T, the controller 210 of the transmitter 10 sets the time length td corresponding to the phase shift of the clock signal CLK_SEF_R in the receiver 30B to the time τ1 + Tfix_diff + τ2. Then, the fixed time Tfix is further subtracted from the subtraction result τ1 + Tfix_diff + τ2-td.

  In this case, the subtraction result τ1 + Tfix_diff + τ2-td can be transformed as the following equation.

τ1 + Tfix_diff + τ2-td
= Τ1 + τ2 + (Tfix_diff−td)
= Τ1 + τ2 + Tfix (3)
In Expression (3), subtracting the time length td from the fixed time Tfix_diff including the response time (SIFS_diff) measured in synchronization with the clock signal CLK_SEF_R in the receiver 30B means that the phase of the clock signal CLK_SEF_R is the same as that of the clock signal CLK_SEF_T. Since this corresponds to obtaining the fixed time Tfix including the response time (SIFS) in the receiver 30B when it matches the phase, subtracting the time length td from the fixed time Tfix_diff means that “the phase of the clock signal CLK_SEF_R is Based on the time length td, the receiver 3 so that the response time (SIFS_diff) measured in the receiver 30B matches the response time (SIFS) in the receiver 30B when it matches the phase of the clock signal CLK_SEF_T. Adjusting the predetermined time Tfix_diff including the measured response times SIFS_diff in B "especially corresponding.

  Then, the round trip time τ1 + τ2 is obtained by subtracting the adjusted fixed time Tfix = Tfix_diff−td from the total time τ1 + τ2 + Tfix.

  Therefore, when the transmitter 10 adds the time length td received from the receiver 30B to the fixed time Tfix and subtracts the addition result from the time τ1 + Tfix_diff + τ2, the phase of the clock signal CLK_SEF_R matches the phase of the clock signal CLK_SEF_T. Constant including the response time SIFS_diff measured in the receiver 30B based on the time length td so that the response time (SIFS_diff) measured in the receiver 30B matches the response time (SIFS) in the receiver 30B. This corresponds to adjusting the time Tfix_diff and subtracting the adjusted fixed time from the time τ1 + Tfix + τ2 (= total time) to calculate the round-trip time τ1 + τ2.

  FIG. 14 is another flowchart for explaining the operation of determining the communication distance between the transmitter and the receiver in the second embodiment. In the flowchart shown in FIG. 14, step S5A is inserted between step S5 and step S6 of the flowchart shown in FIG. 5, and steps S7, S8, and S10 are replaced with steps S7A, S8A, and S10A, respectively. Is the same as the flowchart shown in FIG.

  When the carrier detector 180B of the receiver 30B detects the end of data reception (step S5), the phase of the clock signal CLK_SEF_T in the transmitter 10 and the phase of the clock signal CLK_SEF_R in the receiver 30B are determined by the method described above. The phase difference θd is detected, and the detected phase difference θd is output to the controller 210A, and a signal DETF indicating the end of data reception is generated and output to the controller 210A.

  The controller 210A receives the signal DETF and the phase difference θd from the carrier detector 180B. Then, the controller 210A converts the phase difference θd into a time length td (= θd / ω) and measures the number of components of the divided clock signal CLK_B from the 1 / N divider 250 in response to reception of the signal DETF. Then, the response time SIFS_diff (see FIG. 11) is measured. That is, the receiver 30B waits for a predetermined time SIFS_diff based on the divided clock signal CLK_B (step S6).

  When the fixed time SIFS_diff elapses, the controller 210A of the receiver 30B outputs the data and the time length td from the terminal TDA to the modulator 260. The modulator 260 modulates the data and the time length td with a predetermined modulation frequency. The low pass filter 270 removes high frequency noise from the modulation data and outputs a baseband signal to the mixer 280. The mixer 280 mixes the baseband signal from the low pass filter 270 and the clock signal CLK_PAT from the selector 240 and outputs the mixed signal to the amplifier 290. That is, the mixer 280 outputs the baseband signal to the amplifier 290 in synchronization with the clock signal CLK_PAT. The amplifier 290 amplifies the output of the mixer 280 and outputs it to the selector 120. The selector 120 transmits the output of the amplifier 290 via the antenna 110. Thereby, transmission of the data and the time length td from the receiver 30B to the transmitter 10 is started (step S7A).

  Thereafter, the controller 210 of the transmitter 10 generates an H level signal SLT 1 and outputs the signal SLT 1 to the selector 120. The selector 120 connects the switch 123 to the terminal 121 in accordance with the H level signal SLT1.

  Then, the antenna 110 of the transmitter 10 supplies the data received via the wireless communication space 20 and the time length td to the amplifier 130 via the selector 120. The amplifier 130 amplifies the data and the time length td supplied from the selector 120 and outputs them to the mixer 140. The mixer 140 mixes the output of the amplifier 130 and the clock signal CLK_PAT from the clock adjuster 170 and outputs the mixed signal to the low-pass filter 150. The low pass filter 150 removes high frequency noise from the output of the mixer 140 and outputs a baseband signal to the demodulator 160.

  Demodulator 160 demodulates the baseband signal and outputs the demodulated data DATA and time length td to controller 210. Then, controller 210 detects the end position of frame start unit SFD based on the data DATA received from demodulator 160 by the method described above. Thereby, the transmitter 10 starts to stably receive the data DATA and the time length td from the receiver 30 (step S8A).

  Then, the controller 210 of the transmitter 10 executes step S9 described in the first embodiment, and calculates the total time Ttotal_diff = τ1 + Tfix_diff + τ2.

  When the controller 210 of the transmitter 10 calculates the total time Ttotal_diff = τ1 + Tfix_diff + τ2, the time length td is added to the fixed time Tfix, and the addition result Tfix + td (= Tfix_diff) is subtracted from the total time Ttotal_diff = τ1 + Tfix_τ2 + τ2 + τ2 Calculate. Then, the controller 210 determines the communication distance between the transmitter 10 and the receiver 30B by multiplying the half of the round-trip time τ1 + τ2 (τ1 + τ2) / 2 by the speed of light c (step S10A).

  Thereby, a series of operation | movement is complete | finished.

[Another method 2 for accurately measuring the distance between the transceivers]
In the second embodiment, the transmitter transmits data to the receiver, detects the phase difference between the phase of the data received from the receiver and the phase of the clock signal generated in the transmitter, and detects the detected phase difference. Based on the phase difference, the round trip time for the data to and from the receiver may be accurately measured.

  FIG. 15 is a schematic block diagram showing a configuration of a transmitter according to the second embodiment. The transmitter 10A according to the second embodiment is the same as the transmitter 10 except that the carrier detector 180 and the controller 210 of the transmitter 10 shown in FIG. 2 are replaced with the carrier detector 180C and the controller 210B, respectively. is there.

  Based on the received data from the low-pass filter 150, the carrier detector 180C calculates a phase difference θd between the phase of the clock signal CLK_SEF_T generated in the transmitter 10A by the method described later and the phase of the received data received from the receiver 30. The detected phase difference θd is output to the controller 210B. Other than that, the carrier detector 180C performs the same function as the carrier detector 180.

  The controller 210B measures the total time Ttotal_diff = τ1 + Tfix_diff + τ2 (see FIG. 11) from the timing t1 at which the transmission of the data DATT is completed to the timing t10 at which the data DATR starts to be stably received, and the received position from the carrier detector 180C. The phase difference θd is converted into a time length td (= θd / ω).

  Then, the controller 210B adds the time length td to the fixed time Tfix when the phase of the clock signal CLK_SEF_R matches the phase of the clock signal CLK_SEF_T, and the addition result Tfix + td (= Tfix_diff) is calculated from the total time Ttotal_diff = τ1 + Tfix_diff + τ2. A round-trip time τ1 + τ2 in which data is reciprocated with the receiver 30 by subtraction is calculated. Thereafter, the controller 210B calculates the distance to the receiver 30 by the same method as the controller 210 based on the round trip time τ1 + τ2.

  Note that adding the time length td received from the receiver 30 by the controller 210B of the transmitter 10A to the fixed time Tfix and subtracting the addition result from the total time Ttotal_diff = τ1 + Tfix_diff + τ2 means that the phase of the clock signal CLK_SEF_R is the clock signal CLK_SEF_T. Measured at the receiver 30 based on the time length td so that the response time (SIFS_diff) measured at the receiver 30 matches the response time (SIFS) at the receiver 30 when the phase coincides with This corresponds to adjusting the fixed time Tfix_diff including the response time SIFS_diff and subtracting the fixed time after the adjustment from the time τ1 + Tfix + τ2 (= total time) to calculate the round trip time τ1 + τ2. The reason is as described in [Other method 1 for accurately measuring the distance between the transceivers].

  FIG. 16 is a diagram for explaining a method of detecting phase difference θd in carrier detector 180C shown in FIG. Since the phase of the clock signal CLK_SEF_R generated in the receiver 30 is shifted from the phase of the clock signal CLK_SEF_T generated in the transmitter 10A, the phase of the reception data DARR received by the receiver 30 is different from the phase of the clock signal CLK_SEF_R. In the case of deviation (see (a) of FIG. 16), the timing (SFD end position) t_SFD at which the transmitter 10A starts to receive the reception data DATR stably is synchronized with the clock signal CLK_SEF_T generated by the transmitter 10A. Deviation from sampling timing.

  The response time SIFS_diff reflecting the phase difference θd1 in the receiver 30 is measured in the receiver 30, and data is transmitted from the receiver 30 to the transmitter 10A in synchronization with the clock signal CLK_SEF_R that is out of phase with the clock signal CLK_SEF_T. Because it is done.

  As a result, the timing t_SFD is detected at the sampling timing ST2, and the time td (= θd / ω) corresponding to the phase difference θd1 is compared with the case where the phase of the clock signal CLK_SEF_R is not shifted from the phase of the clock signal CLK_SEF_T. Be late.

  Therefore, the carrier detector 180C of the transmitter 10A detects the phase difference θd1 by the same method as the carrier detector 180A. Then, carrier detector 180C outputs the detected phase difference θd to controller 210B.

  Thereby, even if the phase shift is not adjusted on the receiver 30 side, the transmitter 10A can adjust the phase shift of the clock signal CLK_SEF_R in the receiver 30 and accurately measure the distance to the receiver 30.

  FIG. 17 is still another flowchart for explaining the operation of determining the communication distance between the transmitter and the receiver in the second embodiment. The flowchart shown in FIG. 17 is the same as the flowchart shown in FIG. 5 except that step S10 of the flowchart shown in FIG. 5 is replaced with steps S9A and S10A.

  The controller 210B of the transmitter 10A measures the total time Ttotal_diff = τ1 + Tfix_diff + τ2 (see FIG. 11) from the timing t1 when the transmission of the data DATT is completed to the timing t10 when the data DATR starts to be stably received (step S9). Then, the carrier detector 180C detects the phase difference θd between the phase of the clock signal CLK_SEF_T generated in the transmitter 10A and the timing at which the reception data from the receiver 30 starts to be stably received by the method described above. The detected phase difference θd is output to the controller 210B.

  The controller 210B converts the phase difference θd into a time length td (= θd / ω) (step S9A). Then, the controller 210B adds the time length td to the fixed time Tfix, and calculates the round trip time τ1 + τ2 by subtracting the addition result Tfix + td (= Tfix_diff) from the total time Ttotal_diff = τ1 + Tfix_diff + τ2. Thereafter, the controller 210B multiplies half the round trip time τ1 + τ2 (τ1 + τ2) / 2 by the speed of light c to determine the communication distance between the transmitter 10A and the receiver 30 (step S10A).

  Thereby, a series of operation | movement is complete | finished.

  The data modulation method in the second embodiment is not limited to QPSK, and may be CCK (Complementary Code Keying), OFDM (Orthogonal Frequency Division Multiplexing), or the like.

  As described above, in the second embodiment, the phase and sampling of data generated due to the phase of the clock signal generated in the receiver being shifted from the phase of the clock signal generated in the transmitter. The phase difference from the timing is detected, and the phase of the clock signal at the receiver is adjusted based on the detected phase difference, or the total time from when the data is transmitted to the receiver until it is received by the transmitter It is characterized by accurately measuring the round-trip time during which the data is reciprocated between the transmitter and the receiver.

  With this feature, the distance between the transmitter and the receiver can be accurately measured even when the phase of the clock signal generated at the receiver is shifted from the phase of the clock signal generated at the transmitter.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and is intended to include meanings equivalent to the scope of claims for patent and all modifications within the scope.

  The present invention is applied to a communication system capable of accurately measuring a communication distance between two communication terminals.

1 is a schematic block diagram of a communication system according to Embodiment 1 of the present invention. It is a schematic block diagram which shows the structure of the transmitter shown in FIG. It is a timing chart of transmission data and reception data. It is a figure for demonstrating the method to detect the timing which a transmitter starts receiving the data from a receiver stably. It is a flowchart for demonstrating the operation | movement which determines the communication distance between a transmitter and a receiver. It is a figure which shows the relationship between the communication idle time and communication distance. It is a figure which shows the change of the sampling timing of a received signal when the phase of the clock signal which the receiver produced | generated has shifted | deviated with respect to the phase of the clock signal which the transmitter produced | generated. 6 is a schematic block diagram illustrating a configuration of a receiver according to Embodiment 2. FIG. It is a figure for demonstrating the method to detect the phase difference of the clock signal produced | generated in the receiver with respect to the phase of the clock signal produced | generated in the transmitter. It is a signal space figure of the data modulated by QPSK. It is another timing chart of transmission data and reception data. 10 is a flowchart for explaining an operation of determining a communication distance between a transmitter and a receiver in the second embodiment. FIG. 10 is another schematic block diagram illustrating a configuration of a receiver according to the second embodiment. 10 is another flowchart for explaining an operation of determining a communication distance between a transmitter and a receiver in the second embodiment. 6 is a schematic block diagram illustrating a configuration of a transmitter according to Embodiment 2. FIG. FIG. 16 is a diagram for explaining a method of detecting a phase difference in the carrier detector shown in FIG. 15. 10 is still another flowchart for explaining an operation of determining a communication distance between a transmitter and a receiver in the second embodiment.

Explanation of symbols

  10, 10A transmitter, 20 wireless communication space, 30, 30A, 30B receiver, 100 communication system, 110 antenna, 120, 240 selector, 121, 122, 241, 242 terminal, 123, 243 switch, 130, 290 amplifier 140,280 mixer, 150,270 low pass filter, 160 demodulator, 170 clock adjuster, 180, 180A, 180B, 180C carrier detector, 190 A / D converter, 200 counter, 210, 210A, 210B controller, 220 Crystal oscillator, 230 clock generator, 250, 250A 1 / N divider, 260 modulator.

Claims (10)

A communication system capable of measuring a communication distance between two communication terminals arranged in a wireless communication space,
A transmitter for completing transmission of data via the wireless communication space;
A receiver that receives data from the transmitter via the wireless communication space and transmits data for a response to the received data to the transmitter via the wireless communication space;
The transmitter and the receiver transmit and receive the data in synchronization with a reference clock,
The transmitter measures a total time between a first timing for completing the transmission of the data to the receiver and a second timing for starting to stably receive the data from the receiver; A communication system for determining a communication distance to the receiver based on the measured total time.   The communication system according to claim 1, wherein the second timing is a reception end timing of a signal indicating the start of a frame.   The communication system according to claim 2, wherein the signal indicating the start of the frame is a start frame delimiter. The receiver transmits the data to the transmitter after a response time has elapsed after completion of reception of the data from the transmitter,
The transmitter calculates a round trip time in which the data reciprocates with the receiver by subtracting a certain time including the response time from the total time, and reaches the receiver based on the calculated round trip time. The communication system according to any one of claims 1 to 3, wherein a communication distance is determined. The data includes a synchronization signal portion, a frame start portion, and a frame portion sequentially from the beginning,
The communication system according to claim 4, wherein the predetermined time is a sum of the response time, a detection time of the synchronization signal portion, and a detection time of the frame start portion.   The receiver estimates a reference clock signal generated in the transmitter based on data received from the transmitter, determines the response time based on the estimated reference clock signal, and determines the data The communication system according to claim 4 or 5, which transmits to a transmitter.   The transmitter estimates a first reference clock signal generated in the receiver based on data received from the receiver in communication with the receiver, and generates a second reference clock signal generated by itself. Is compared with the estimated phase of the first reference clock signal, and when the phase of the second reference clock signal is shifted from the phase of the first reference clock signal, the communication distance with the receiver The communication system according to claim 1, which measures a change in. The receiver detects a phase difference between a phase of data received from the transmitter and a phase of a first reference clock signal generated by the receiver, and based on the detected phase difference, the first reference clock signal The response time is measured by matching the phase of the second reference clock signal generated in the transmitter with the phase, and after the response time is measured, the data is transmitted to the transmitter.
The transmitter calculates a round trip time in which the data reciprocates with the receiver by subtracting a certain time including the response time from the total time, and reaches the receiver based on the calculated round trip time. The communication system according to any one of claims 1 to 3, wherein a communication distance is determined. The receiver detects a phase difference between a phase of data received from the transmitter and a phase of a first reference clock signal generated by the receiver, converts the detected phase difference into a time length, and Measuring a first response time in synchronization with one reference clock signal, and after measuring the first response time, transmitting the data and the time length to the transmitter;
The transmitter transmits the first response time to a second response time at the receiver when the phase of the first reference clock signal matches the phase of the second reference clock signal generated by the transmitter. The fixed time including the first response time is adjusted based on the time length so as to match, and the fixed time after the adjustment is subtracted from the total time, so that the data goes back and forth between the receiver and the receiver. The communication system according to any one of claims 1 to 3, wherein a round trip time to be calculated is calculated, and a communication distance to the receiver is determined based on the calculated round trip time.   The transmitter detects a phase difference between a phase of data received from the receiver and a phase of a first reference clock signal generated by the transmitter, converts the detected phase difference into a time length, and receives the reception In synchronization with the second reference clock at a first response time at the receiver when the phase of the second reference clock signal generated at the receiver matches the phase of the first reference clock signal. The fixed time including the second response time is adjusted so that the measured second response time of the receiver coincides, and the adjusted fixed time is subtracted from the total time to receive the data. The communication system according to any one of claims 1 to 3, wherein a reciprocating time for reciprocating with a device is calculated, and a communication distance to the receiver is determined based on the calculated reciprocating time.

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