JP2006019629A - Power-supply protecting circuit and semiconductor device having same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable power-supply protecting circuit and a semiconductor device having the same circuit whereby its current flowing in between its power-supply input terminals and its through current to the ground are prevented from occurring during its ordinarily operating term, and whereby a semiconductor circuit is protected from an ESD. <P>SOLUTION: The power-supply protecting circuit has a first PMOS transistor P1 connected with the input terminal 11 of a first power supply and connected with the input terminal 12 of the second power supply, and has a power-supply-voltage monitoring circuit 15 connected with the first PMOS transistor P1. The power-supply-voltage monitoring circuit 15 has a second PMOS transistor P2, a third PMOS transistor P3, a first controlling circuit M1, a second controlling circuit M2, and a delay element 16. The power-supply-voltage monitoring circuit 15 is so constituted favorably as not to make any current flow in between the power-supply input terminals 11, 12 during the ordinarily operating term of the power-supply protecting circuit and as to be able to prevent a through current to the ground from occurring during its ordinarily operating term. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power protection circuit and a semiconductor device including the same, and more particularly to a power protection circuit that prevents a problem caused by ESD (electrostatic discharge) or the like from occurring in a semiconductor integrated circuit having a plurality of power input terminals. The present invention relates to a semiconductor device including the same.

  Conventionally, many power protection circuits for protecting a semiconductor integrated circuit from ESD have been developed (see, for example, Patent Document 1).

  As a general power protection circuit, there is a circuit in which a PMOS transistor is installed between two power input terminals. In such a power supply protection circuit, during normal operation, the power supply potential (VCC1) at one power supply input terminal is greater (or equal) than the power supply potential (VCC2) at the other power supply input terminal. When turned off, no current flows between both power input terminals. On the other hand, when the potential of the power supply input terminal of VCC2 rises due to ESD in a state where the power supply potential is not supplied to both power supply input terminals, the PMOS transistor is turned on and the power supply input terminal of VCC2 Current flows to the power input terminal. As a result, the potential rise at the power input terminal of VCC2 is alleviated.

  On the other hand, Patent Document 1 and the like disclose a power supply protection circuit intended to prevent damage to semiconductor elements even when voltages are input in random order from a plurality of power supply input terminals. Specifically, a voltage monitoring switching circuit including a series of diodes connected in series, a PMOS transistor, an NMOS transistor, and the like is provided in the power supply protection circuit.

JP 2000-243842 A

  The conventional power supply protection circuit described above has a problem that a current steadily flows from the power supply input terminal of VCC2 to the power supply input terminal of VCC1 when a voltage is supplied only to the power supply input terminal of VCC2.

On the other hand, by arranging diodes, PMOS transistors, and NMOS transistors at predetermined positions in the power supply protection circuit as in Patent Document 1, voltage is supplied to only one of both power supply input terminals during normal operation. Even in this case, it is possible to prevent a current from flowing to the other power input terminal. Furthermore, even when the power supply potential is not supplied to both power input terminals and the potential of the power input terminal of VCC2 rises due to ESD, a current is supplied to the power supply input terminal of VCC1 and the potential at the power input terminal of VCC2 is The rise can be mitigated.
However, when the potential of the power input terminal of VCC1 rises due to ESD, a smooth current path may not be formed by the diode.

  In order to solve such a problem, it is conceivable to install a power supply voltage monitor circuit composed mainly of a plurality of PMOS transistors and NMOS transistors in the power supply protection circuit. That is, a power supply voltage monitoring circuit that does not use a diode causes a current to flow to the VCC2 side power input terminal when the potential rises at the VCC1 side power input terminal, and a VCC1 side power input when the potential rises at the VCC2 side power input terminal. By flowing a current to the terminal, it is possible to smoothly flow a current regardless of the rise in power supply potential.

  However, even in that case, when VCC2 is at a higher potential than VCC1 during normal operation, a through current flows from the VCC2 side power input terminal to the ground (GND), resulting in an increase in power consumption. Can be considered. Further, depending on the set values of VCC1 and VCC2 during normal operation, there may be a problem that current flows from the VCC2 side power input terminal to the VCC1 side power input terminal.

  The present invention has been made in order to solve the above-described problems. In any case, the magnitude of the two power supply voltages input to the two power supply input terminals and the combination thereof are not affected during normal operation. It is an object of the present invention to provide a highly reliable power supply protection circuit and a semiconductor device including the same, which prevent generation of a current between power supply input terminals and a through current to the ground and protect a semiconductor circuit from ESD.

  A power protection circuit according to a first aspect of the present invention is a power protection circuit connected to a circuit having a plurality of power input terminals, wherein a drain or a source is connected to the first power input terminal. A first PMOS transistor having a source or drain connected to two power supply input terminals, and a control signal transmitted to a back gate of the first PMOS transistor, and a delay element connected to the gate of the first PMOS transistor; A power supply voltage monitor circuit connected to transmit a control signal, the power supply voltage monitor circuit having a drain connected to the first power supply input terminal and transmitting a control signal to a back gate and a source Connected second PMOS transistor and drain connected to the second power input terminal A third PMOS transistor connected to transmit a control signal to the back gate and the source, a first signal input unit connected to the first power input terminal, and a second signal input unit connected to the second power input. A first control circuit connected to the terminal and having a signal output connected to the gate of the second PMOS transistor; a first signal input connected to the second power input terminal; and a second signal input connected to the first power input terminal. A second control circuit connected to a power supply input terminal and having a signal output unit connected to the gate of the third PMOS transistor.

  A power protection circuit according to a second aspect of the invention is the power supply protection circuit according to the first aspect of the invention, wherein both the first control circuit and the second control circuit are input potentials of the first signal input unit. 0V is output from the signal output unit when the input potential of the second signal input unit is smaller than the input potential of the second signal input unit. An output potential of the second signal input unit is output from the output unit, and 0 V is output from the signal output unit when the input potential of the first signal input unit is equal to the input potential of the second signal input unit. It is composed of.

  According to a third aspect of the present invention, in the power supply protection circuit according to the first or second aspect of the present invention, the first control circuit and the second control circuit are both a fourth PMOS transistor and a second PMOS transistor. A fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a capacitor, wherein the fourth PMOS transistor has a source and a back gate connected to the second signal input unit, and a gate connected to the second signal input unit. The fifth PMOS transistor has a source and a back gate connected to the first signal input unit, a gate connected to the second signal input unit, and the first NMOS transistor has a source connected to the first signal input unit. Is connected to the drain of the third NMOS transistor and back The second NMOS transistor has a gate connected to the first signal input unit, a source connected to the drain of the fourth NMOS transistor, a back gate grounded, and a gate connected to the second signal input. The third NMOS transistor and the fourth NMOS transistor are connected to each other, and the source and back gate are grounded, respectively, and the drain of the fifth PMOS transistor, the drain of the second NMOS transistor, and the gate of the third NMOS transistor are connected to each other. A common terminal connected to the other terminal of the capacitive element with one of the terminals grounded, a drain of the fourth PMOS transistor, a drain of the first NMOS transistor, and a gate of the fourth NMOS transistor; Output from the signal output section It is.

  According to a fourth aspect of the present invention, in the power supply protection circuit according to the third aspect of the present invention, the capacitor element is a capacitor.

  According to a fifth aspect of the present invention, in the power supply protection circuit according to the third aspect of the present invention, the capacitive element is an NMOS transistor.

  According to a sixth aspect of the present invention, a semiconductor device includes the power supply protection circuit according to any one of the first to fifth aspects.

  In the present invention, a first PMOS transistor and a power supply voltage monitor circuit including a plurality of PMOS transistors, a plurality of control circuits, a delay element, and the like are installed in the power supply protection circuit. As a result, a current between the power supply input terminals and a through current to the ground during normal operation occur regardless of the magnitude of the two power supply voltages input to the two power supply input terminals and the combination thereof. In addition, it is possible to provide a highly reliable power protection circuit and a semiconductor device including the power protection circuit that prevent the ESD and protect the semiconductor circuit from ESD.

Embodiment.
Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings. In addition, in each figure, the same code | symbol is attached | subjected to the part which is the same or it corresponds, The duplication description is simplified or abbreviate | omitted suitably.

FIG. 1 is a circuit diagram showing a semiconductor device 1 according to the embodiment.
The semiconductor device 1 of the present embodiment is an application having a plurality of power supplies. The main components of the semiconductor device 1 are a plurality of power input terminals 11 and 12, an output buffer 3 that performs interface (signal exchange) with the external 7, an internal circuit 2 that drives the output buffer 3, and the like.

  The semiconductor device 1 configured as described above changes the interface voltage level with the external 7 by changing the power supply voltage of the output buffer 3. For example, the internal circuit 2 operates by setting the potential VCC2 at the second power input terminal 12 to 2.5V. The interface with the external 7 changes the potential VCC1 at the first power input terminal 11 to 3.3V and 1.5V, so that the interface level (output H level) is also 3.3V and 1.5V. It is variable.

  The power supply protection circuit in the present embodiment is normal even when the power supply voltages VCC1 and VCC2 at the plurality of power supply input terminals 11 and 12 and the combination thereof vary as in the semiconductor device 1 of FIG. It ensures operation and protection from ESD.

The power protection circuit 10 mounted on the semiconductor device 1 of FIG. 1 will be described in detail with reference to FIGS.
As shown in FIG. 2, the power supply protection circuit 10 mainly includes a first power supply input terminal 11, a second power supply input terminal 12, a first PMOS transistor P <b> 1, and a power supply voltage monitor circuit 15. The power supply voltage monitor circuit 15 includes a delay element 16, a second PMOS transistor P2, a third PMOS transistor P3, a first control circuit M1, and a second control circuit M2.

  The first power input terminal 11 and the second power input terminal 12 of the power protection circuit 10 are connected to the first power input terminal 11 and the second power input terminal 12 of the semiconductor device 1, respectively.

The first PMOS transistor P <b> 1 of the power protection circuit 10 has a drain D connected to the first power input terminal 11 and a source S connected to the second power input terminal 12.
The gate G of the first PMOS transistor P 1 is connected to the delay element 16 (delay circuit) in the power supply voltage monitor circuit 15. The delay element 16 is connected to the second PMOS transistor P2 and the third PMOS transistor P3 in the power supply voltage monitor circuit 15, and transmits the control signal generated by the power supply voltage monitor circuit 15 to the first PMOS transistor P1. Note that the delay element 16 can be constituted by, for example, the resistor 22 and the capacitor 21 shown in FIG.
The back gate (substrate gate) BG of the first PMOS transistor P1 is connected to the second PMOS transistor P2 and the third PMOS transistor P3 in the power supply voltage monitor circuit 15, and the control signal generated by the power supply voltage monitor circuit 15 is transmitted. Is done.

The second PMOS transistor P2 of the power supply voltage monitor circuit 15 has a drain connected to the first power supply input terminal 11 and is connected so that a control signal is transmitted to the source and back gate.
The third PMOS transistor P3 of the power supply voltage monitor circuit 15 is connected so that the drain is connected to the second power supply input terminal 12 and the control signal is transmitted to the source and back gate.

The first control circuit M1 and the second control circuit M2 of the power supply voltage monitor circuit 15 are provided with a first signal input unit A, a second signal input unit B, and a signal output unit C, respectively.
In the first control circuit M1, the first signal input unit A is connected to the first power input terminal 11, the second signal input unit B is connected to the second power input terminal 12, and the signal output unit C is the second PMOS transistor P2. Connected to the gate.
In the second control circuit M2, the first signal input section A is connected to the second power input terminal 12, the second signal input section B is connected to the first power input terminal 11, and the signal output section C is the third PMOS transistor P3. Connected to the gate.

The first control circuit M1 and the second control circuit M2 connected in this way operate as shown in the table of FIG.
That is, when the input potential of the first signal input unit A is larger than the input potential of the second signal input unit B, 0 V is output from the signal output unit C. On the other hand, when the input potential of the first signal input unit A is smaller than the input potential of the second signal input unit B, the input potential (B potential) of the second signal input unit B is changed from the signal output unit C. Output. When the input potential of the first signal input unit A is equal to the input potential of the second signal input unit B, 0 V is output from the signal output unit C.

The configurations of the first control circuit M1 and the second control circuit M2 that perform such operations will be described with reference to FIG.
As shown in FIG. 5, the control circuits M1 and M2 mainly include a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a capacitive element 18, Consists of.

The fourth PMOS transistor P4 in the control circuits M1 and M2 has a source and a back gate connected to the second signal input unit B and a gate connected to the first signal input unit A.
The fifth PMOS transistor P5 has a source and a back gate connected to the first signal input unit A and a gate connected to the second signal input unit B.

The first NMOS transistor N1 in the control circuits M1 and M2 has a source connected to the drain of the third NMOS transistor N3, a back gate grounded (GND), and a gate connected to the first signal input unit A.
The second NMOS transistor N2 has a source connected to the drain of the fourth NMOS transistor N4, a back gate grounded, and a gate connected to the second signal input unit B.
The third NMOS transistor N3 and the fourth NMOS transistor N4 have their sources and back gates grounded, respectively.

The drain of the fifth PMOS transistor P5, the drain of the second NMOS transistor N2, and the gate of the third NMOS transistor N3 are connected in common at a contact point 19 (OUTB).
The drain of the fourth PMOS transistor P4, the drain of the first NMOS transistor N1, the gate of the fourth NMOS transistor N4, and one terminal of the capacitive element 18 are connected in common. Here, the other terminal of the capacitive element 18 is grounded.
With such a configuration, the output signal described with reference to FIG. 4 is output from the signal output unit C.
In addition, as the capacitive element 18 provided in the control circuits M1 and M2, an NMOS transistor shown in FIG. 6 can be used instead of the capacitor.

Hereinafter, the operation of the power supply protection circuit 10 configured as described above will be described with reference to FIG.
First, the operation of the power supply protection circuit 10 when the power supply potential VCC1 of the first power supply input terminal 11 is high and the power supply potential VCC2 of the second power supply input terminal 12 is low (VCC1> VCC2) will be described.

In this case, the output at the signal output unit C of the first control circuit M1 is 0V (see FIG. 4). As a result, the second PMOS transistor P2 is turned on.
On the other hand, the output at the signal output unit C of the second control circuit M2 is the B potential (VCC1). As a result, the third PMOS transistor P3 is turned off.
Thus, the high potential VCC1 is supplied to the back gate BG of the first PMOS transistor P1 via the second PMOS transistor P2. Similarly, the high potential VCC1 is supplied to the gate G of the first PMOS transistor P1 through the second PMOS transistor P2 and the delay element 16.

  As described above, when the high potential VCC1 is supplied to the back gate BG and the gate G of the first PMOS transistor P1, the first PMOS transistor P1 is turned off. Further, since the third PMOS transistor P3 is also turned off, no current flows between the power supply input terminals 11 and 12 in the power supply protection circuit 10.

Next, the operation of the power supply protection circuit 10 when the power supply potential VCC1 of the first power supply input terminal 11 is low and the power supply potential VCC2 of the second power supply input terminal 12 is high (VCC1 <VCC2) will be described.
In this case, the output of the second control circuit M2 is 0V. As a result, the third PMOS transistor P3 is turned on.
On the other hand, the output of the first control circuit M1 becomes the B potential (VCC2). As a result, the second PMOS transistor P2 is turned off.
Thus, the high potential VCC2 is supplied to the back gate BG of the first PMOS transistor P1 via the third PMOS transistor P3. Similarly, the high potential VCC2 is supplied to the gate G of the first PMOS transistor P1 through the third PMOS transistor P3 and the delay element 16.

  As described above, when the high potential VCC2 is supplied to the back gate BG and the gate G of the first PMOS transistor P1, the first PMOS transistor P1 is turned off. Furthermore, since the second PMOS transistor P2 is also turned off, no current flows between the power supply input terminals 11 and 12.

Next, the operation of the power supply protection circuit 10 when the power supply potential VCC1 of the first power supply input terminal 11 and the power supply potential VCC2 of the second power supply input terminal 12 are the same potential (VCC1 = VCC2) will be described.
In this case, the output of the first control circuit M1 becomes 0V, and the second PMOS transistor P2 is turned on. Similarly, the output of the second control circuit M2 becomes 0V, and the third PMOS transistor P3 is turned on. Thus, a potential is supplied to the first PMOS transistor P1 through the second PMOS transistor P2 and the third PMOS transistor P3.

  Here, since the same potential is supplied to the back gate BG and the gate G of the first PMOS transistor P1, the first PMOS transistor P1 is turned off. On the other hand, although the second PMOS transistor P2 and the third PMOS transistor P3 are turned on, since VCC1 and VCC2 are at the same potential, no current flows between the power supply input terminals 11 and 12.

  As described above, according to the power supply protection device 10 of the present embodiment, regardless of the relationship between VCC1 and VCC2 during the normal operation of the semiconductor device 1, There is no problem that current flows between the power input terminals 11 and 12.

Hereinafter, the effect of suppressing the generation of the through current in the power supply protection circuit 10 of the present embodiment will be described with reference to FIG.
In the power supply protection circuit 10 according to the present embodiment, the configuration of the control circuits M1 and M2 described in FIG. 5 prevents a through current from being generated in the circuit.

First, the operation of the control circuits M1 and M2 when the input potential of the first signal input unit A is smaller than the input potential of the second signal input unit B (A <B) will be described.
In this case, the fourth PMOS transistor P4 is turned on and the fifth PMOS transistor P5 is turned off. On the other hand, the first NMOS transistor N1 and the second NMOS transistor N2 are turned on.

  Here, since the fourth PMOS transistor P4 is turned on, the output potential (OUT) at the signal output unit C rises and the fourth NMOS transistor N4 is turned on. As a result, the potential (OUTB) at the contact point 19 is lowered, the third NMOS transistor N3 is turned off, and the B potential is output from the signal output unit C via the fourth PMOS transistor P4 (in the on state). At this time, since the fifth PMOS transistor P5 and the third NMOS transistor N3 are turned off, a through current to GND does not occur.

Next, the operation of the control circuits M1 and M2 when the input potential of the first signal input unit A is higher than the input potential of the second signal input unit B (A> B) will be described.
In this case, the fourth PMOS transistor P4 is turned off and the fifth PMOS transistor P5 is turned on. The first NMOS transistor N1 and the second NMOS transistor N2 are turned on.

  Here, since the fifth PMOS transistor P5 is turned on, the potential (OUTB) at the contact 19 rises and the third NMOS transistor N3 is turned on. As a result, the output potential (OUT) at the signal output unit C decreases, and 0 V is output from the signal output unit C. At this time, since the fourth PMOS transistor P4 is turned off and the fourth NMOS transistor N4 is also turned off when the output potential is 0 V, no through current to GND is generated.

Next, the operation of the control circuits M1 and M2 when the input potential of the first signal input unit A and the input potential of the second signal input unit B are the same potential (A = B) will be described.
In this case, the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are turned off. The first NMOS transistor N1 and the second NMOS transistor N2 are turned on.

  Here, the output potential (OUT) and the contact potential (OUTB) are intermediate potentials, but the output potential (OUT) is closer to 0 V than the contact potential (OUTB) by the capacitive element 18. Further, the fourth NMOS transistor N4 having the output potential (OUT) as a gate input is in a state close to OFF, and the contact potential (OUTB) rises. As a result, the third NMOS transistor N3 is turned on, and 0 V is output from the signal output unit C. At this time, since the fourth PMOS transistor P4 and the fifth PMOS transistor P5 are turned off, a through current to GND does not occur.

  Note that the power supply protection circuit 10 of the present embodiment penetrates into the circuit by the configuration of the control circuits M1 and M2 even if any of the plurality of power supply input electrodes 11 and 12 in the semiconductor device 1 rises in potential due to ESD or the like. The semiconductor device 1 is protected without generating a current.

First, the operation of the control circuits M1 and M2 when the input potential of the first signal input unit A is 0 V and the input potential of the second signal input unit B rises will be described.
In this case, the first NMOS transistor N1 is turned off. Further, since the contact potential (OUTB) becomes 0V, the third NMOS transistor N3 is turned off. Further, the fourth PMOS transistor P4 is turned on, and the B potential is output from the signal output unit C. At this time, since the potential of the first signal input portion A is 0 V and the first NMOS transistor N1 is turned off, no through current to GND is generated.

Next, the operation of the control circuits M1 and M2 when the input potential of the second signal input unit B is 0 V and the input potential of the first signal input unit A rises will be described.
In this case, the output potential (OUT) of the signal output unit C is 0V. At this time, since the potential of the second signal input portion B is 0V and the second NMOS transistor N2 is turned off, no through current to GND is generated.

  As described above, according to the configuration of the power supply protection circuit 10 in the present embodiment, the magnitude of the two power supply voltages VCC1 and VCC2 input to the two power supply input terminals 11 and 12, respectively, and the combination thereof are in any case. Even in this case, no current flows between the power input terminals 11 and 12 during normal operation, and it is possible to prevent a through current from being generated to the ground. In other words, the semiconductor device 1 can be protected from ESD without problems with a relatively simple configuration.

  It should be noted that the present invention is not limited to the present embodiment, and it is obvious that the present embodiment can be modified as appropriate within the scope of the technical idea of the present invention, other than suggested in the present embodiment. is there. Further, the number, position, shape, and the like of the above-described constituent members are not limited to the present embodiment, and the number, position, shape, and the like that are suitable for implementing the present invention can be used.

It is a circuit diagram which shows the semiconductor device in embodiment of this invention. FIG. 2 is a circuit diagram showing a power supply protection circuit installed in the semiconductor device of FIG. 1. FIG. 3 is a circuit diagram illustrating a delay element in the power protection circuit of FIG. 2. It is a table | surface figure which shows the input / output relationship in the control circuit of a power supply voltage monitor circuit. It is a circuit diagram which shows the control circuit in a power supply voltage monitor circuit. It is a figure which shows another form of the capacitive element in a power supply voltage monitor circuit.

Explanation of symbols

1 semiconductor device, 2 internal circuit, 3 output buffer,
10 power protection circuit, 11 first power input terminal, 12 second power input terminal,
15 power supply voltage monitor circuit, 16 delay element, 18 capacitive element,
P1 first PMOS transistor, P2 second PMOS transistor,
P3 third PMOS transistor, P4 fourth PMOS transistor,
P5 fifth PMOS transistor,
N1 first NMOS transistor, N2 second NMOS transistor,
N3 third NMOS transistor, N4 fourth NMOS transistor,
M1 first control circuit, M2 second control circuit,
A 1st signal input part, B 2nd signal input part, C signal output part.

Claims (6)

A power protection circuit connected to a circuit having a plurality of power input terminals,
A first PMOS transistor having a drain or source connected to the first power input terminal and a source or drain connected to the second power input terminal;
A power supply voltage monitor circuit connected to the back gate of the first PMOS transistor so as to transmit a control signal and connected to the gate of the first PMOS transistor via a delay element; With
The power supply voltage monitor circuit has a drain connected to the first power input terminal and a second PMOS transistor connected to transmit a control signal to a back gate and a source, and a drain connected to the second power input terminal. A third PMOS transistor connected to transmit a control signal to the back gate and the source, a first signal input unit connected to the first power input terminal, and a second signal input unit connected to the second power input. A first control circuit connected to the terminal and having a signal output connected to the gate of the second PMOS transistor; a first signal input connected to the second power input terminal; and a second signal input connected to the first power input terminal. A second control circuit connected to a power input terminal and having a signal output unit connected to a gate of the third PMOS transistor; Power supply protection circuit that. The first control circuit and the second control circuit both output 0 V from the signal output unit when the input potential of the first signal input unit is larger than the input potential of the second signal input unit, When the input potential of the first signal input unit is smaller than the input potential of the second signal input unit, the input potential of the second signal input unit is output from the signal output unit, and the input of the first signal input unit 2. The power protection circuit according to claim 1, wherein when the potential is equal to the input potential of the second signal input unit, 0 V is output from the signal output unit. Each of the first control circuit and the second control circuit includes a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a capacitor.
The fourth PMOS transistor has a source and a back gate connected to the second signal input unit and a gate connected to the first signal input unit,
The fifth PMOS transistor has a source and a back gate connected to the first signal input unit and a gate connected to the second signal input unit,
The first NMOS transistor has a source connected to the drain of the third NMOS transistor, a back gate grounded, and a gate connected to the first signal input unit.
The second NMOS transistor has a source connected to the drain of the fourth NMOS transistor, a back gate grounded, and a gate connected to the second signal input unit.
The third NMOS transistor and the fourth NMOS transistor have their source and back gate grounded,
The drain of the fifth PMOS transistor, the drain of the second NMOS transistor, and the gate of the third NMOS transistor are connected in common, and one terminal of the capacitor is grounded, and the drain of the fourth PMOS transistor 3. The power protection circuit according to claim 1, wherein the drain of the first NMOS transistor and the gate of the fourth NMOS transistor are connected in common and output from the signal output unit. 4. The power supply protection circuit according to claim 3, wherein the capacitive element is a capacitor. The power supply protection circuit according to claim 3, wherein the capacitive element is an NMOS transistor. 6. A semiconductor device comprising the power protection circuit according to claim 1.

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