JP2006019623A - Semiconductor wafer - Google Patents

Semiconductor wafer Download PDF

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Publication number
JP2006019623A
JP2006019623A JP2004197914A JP2004197914A JP2006019623A JP 2006019623 A JP2006019623 A JP 2006019623A JP 2004197914 A JP2004197914 A JP 2004197914A JP 2004197914 A JP2004197914 A JP 2004197914A JP 2006019623 A JP2006019623 A JP 2006019623A
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semiconductor wafer
notch
generated
notch portion
solvent
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JP2004197914A
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Japanese (ja)
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Tamotsu Suwa
保 諏訪
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Toshiba Corp
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Toshiba Corp
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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems that a notch formed in a semiconductor wafer is passed through from its backside to its surface, and by the notch to the surface of the semiconductor wafer, the scattering of its solvent is generated in its resist removing process, and further, the variations of its patterns are generated in the case of its immersion exposure, and moreover, the deterioration of the adhesiveness of its protective tape, etc. are generated in its protective-tape separating process. <P>SOLUTION: There is provided a semiconductor wafer having its notch formed out of a groove which is not passed through from its backside to its front surface. Consequently, since the notch is not exposed to the front surface of the semiconductor wafer, the faults caused by the notch can be prevented from being generated when executing miscellaneous processes. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、改良されたノッチ構造を有する半導体ウェハに関する。   The present invention relates to a semiconductor wafer having an improved notch structure.

半導体ウェハの外周の一部に形成されるノッチ部は、半導体ウェハ自身の結晶方位や各種の半導体製造装置にて処理を行う場合のウェハ基準点を決定するうえで重要な役割を果たしている。一般的に利用されているノッチ部の構造は、図5に示すように、半導体ウェハ51の外周に表面51aから裏面51bに貫通する溝によりノッチ部52が形成されている。ノッチ部52の形状は図5に示した例では略U字状であるが、他にV字状も利用されている。   A notch portion formed in a part of the outer periphery of the semiconductor wafer plays an important role in determining the crystal orientation of the semiconductor wafer itself and a wafer reference point when processing is performed by various semiconductor manufacturing apparatuses. As shown in FIG. 5, the structure of the notch portion that is generally used is formed with a notch 52 formed on the outer periphery of the semiconductor wafer 51 by a groove penetrating from the front surface 51a to the back surface 51b. The shape of the notch portion 52 is substantially U-shaped in the example shown in FIG. 5, but a V-shape is also used.

上述したような半導体ウェハ51の表面51aから裏面51bに貫通する形状のノッチ部52においては、IC製造工程のいくつかのプロセスにて問題が発生している。すなわち、図6に示すように、露光工程にて半導体ウェハ61の表面にフォトレジスト62を塗布した後に半導体ウェハ61の外周のフォトレジスト膜を溶剤にて除去する。この工程では、半導体ウェハ61を回転させながら溶剤63を噴射部材64にて半導体ウェハ61の外周へ吹き付ける(図6a)。この際、溶剤63はノッチ部60に当たり周囲に飛散し半導体ウェハ61上に落下する。   In the notch portion 52 having a shape penetrating from the front surface 51a to the back surface 51b of the semiconductor wafer 51 as described above, problems occur in some processes of the IC manufacturing process. That is, as shown in FIG. 6, after the photoresist 62 is applied to the surface of the semiconductor wafer 61 in the exposure process, the photoresist film on the outer periphery of the semiconductor wafer 61 is removed with a solvent. In this step, the solvent 63 is sprayed onto the outer periphery of the semiconductor wafer 61 by the spray member 64 while rotating the semiconductor wafer 61 (FIG. 6a). At this time, the solvent 63 hits the notch 60 and scatters around and falls onto the semiconductor wafer 61.

この結果、飛散した溶剤65は半導体ウェハ61のフォトレジスト62上に付着してしまう(図6b)。このため、その後の工程にて半導体ウェハ61表面に各種のレジストパターン66を形成した際に、飛散した溶剤65が素子形成領域67のレジストパターン66を崩す問題が発生していた(図6c)。   As a result, the scattered solvent 65 adheres to the photoresist 62 of the semiconductor wafer 61 (FIG. 6b). For this reason, when various resist patterns 66 are formed on the surface of the semiconductor wafer 61 in the subsequent process, there has been a problem that the scattered solvent 65 causes the resist pattern 66 in the element formation region 67 to be destroyed (FIG. 6c).

また、露光方式として液浸露光技術が知られている。図7には従来の半導体ウェハ(図5)に液浸露光を行った状態を示してある。すなわち、ウェハステージ71にノッチ部72を有する半導体ウェハ73が装着され、露光レンズ74並びに液体75を介して露光が行われる。このとき、図7の拡大図に示すように、半導体ウェハ73のノッチ部72にかかるショットでは、液体75の表面張力のバランスが崩れて液体75を均一に盛れなくなる。この結果、気泡76が液中に入り屈折率のゆらぎが生じてしまい、ショット内パターンのばらつきを悪化させるほか、結像に大きな影響を及ぼす。   In addition, immersion exposure technology is known as an exposure method. FIG. 7 shows a state in which immersion exposure is performed on a conventional semiconductor wafer (FIG. 5). That is, a semiconductor wafer 73 having a notch 72 is mounted on the wafer stage 71 and exposure is performed through the exposure lens 74 and the liquid 75. At this time, as shown in the enlarged view of FIG. 7, in the shot applied to the notch portion 72 of the semiconductor wafer 73, the balance of the surface tension of the liquid 75 is lost and the liquid 75 cannot be uniformly deposited. As a result, the bubbles 76 enter the liquid and the refractive index fluctuates, which not only deteriorates the variation in the pattern in the shot, but also has a great influence on the image formation.

このほか、ラップ工程では半導体ウェハの裏面を研磨するため、図8に示すように半導体ウェハ81の表面に保護テープ82を貼り付ける。その後、余分な保護テープ82を半導体ウェハ81の外周に沿って切り離す際に、ノッチ部83の部分において応力が集中し半導体ウェハ81との密着性が悪化する。このため、半導体ウェハ81の裏面研磨中に使用する水分84がノッチ部83から半導体ウェハ81と保護テープ82の間に染み込み保護テープ82に剥がれを起こす問題が発生している。   In addition, in the lapping process, a protective tape 82 is attached to the surface of the semiconductor wafer 81 as shown in FIG. Thereafter, when the excess protective tape 82 is cut along the outer periphery of the semiconductor wafer 81, stress concentrates at the notch portion 83, and the adhesion to the semiconductor wafer 81 deteriorates. For this reason, there is a problem that moisture 84 used during polishing of the back surface of the semiconductor wafer 81 soaks into the protective tape 82 from the notch 83 between the semiconductor wafer 81 and the protective tape 82.

本発明は、このような従来の課題を解決するためになされたもので、簡単な構成で各種課題を解決しプロセス精度の向上を図ることを可能とした半導体ウェハを提供することを目的とする。   The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a semiconductor wafer that can solve various problems with a simple configuration and can improve process accuracy. .

本発明に係わる半導体ウェハは、裏面から表面に達しない溝によりノッチ部が形成されていることを要旨とする。   The gist of the semiconductor wafer according to the present invention is that notches are formed by grooves that do not reach the front surface from the back surface.

本発明に係わる半導体ウェハにおいては、ノッチ部がウェハ表面に達していないため、ノッチ部での溶剤飛散によるパターン崩しを防止することができ、液浸露光ではノッチにかかるショットでの液体を均一に盛ることができ、気泡の発生を防止することができ、更にラップ工程での保護テープ切り離しの際のノッチ部での応力集中による半導体ウェハとの密着性悪化を防止することなどが可能となった。   In the semiconductor wafer according to the present invention, since the notch portion does not reach the wafer surface, pattern breakage due to solvent scattering at the notch portion can be prevented, and in immersion exposure, the liquid in the shot on the notch is uniformly distributed. It is possible to prevent the generation of bubbles, and it is possible to prevent the deterioration of the adhesion to the semiconductor wafer due to the stress concentration at the notch when the protective tape is separated in the lapping process. .

以下に本発明に係わる半導体ウェハを図を参照して説明する。図1には本発明に係わる半導体ウェハの一実施形態を示す。すなわち、半導体ウェハ11の表面12に達することなく裏面13側のみに片面ノッチ部14を形成したものである。従って、半導体ウェハ11の表面12には片面ノッチ部14の切り込みが現れない。なお、半導体ウェハ11の表面には各種プロセス工程によって素子が形成される。   A semiconductor wafer according to the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of a semiconductor wafer according to the present invention. That is, the single-sided notch portion 14 is formed only on the back surface 13 side without reaching the front surface 12 of the semiconductor wafer 11. Therefore, the notch of the single-side notch portion 14 does not appear on the surface 12 of the semiconductor wafer 11. Note that elements are formed on the surface of the semiconductor wafer 11 by various process steps.

このような構造の半導体ウェハ11を用いることにより、従来発生していた各種の問題を解決することが可能となった。図2には片面ノッチ部14が形成された半導体ウェハ11の表面にフォトレジスト15を塗布した後、外周のフォトレジスト膜を除去するために噴射部材16から溶剤17を回転する半導体ウェハ11の外周へ吹き付けた場合の例を示してある。この結果、溶剤17が吹き付けられた半導体ウェハ11の外周には片面ノッチ部14の切り込みが現れていないことから、吹き付けられた溶剤17はノッチ部に当たることもなくフォトレジスト15の表面に溶剤17が飛散することがなくなり、パターン崩しを防止することが可能となった。   By using the semiconductor wafer 11 having such a structure, it has become possible to solve various problems that have conventionally occurred. In FIG. 2, after the photoresist 15 is applied to the surface of the semiconductor wafer 11 on which the single-sided notch portion 14 is formed, the outer periphery of the semiconductor wafer 11 that rotates the solvent 17 from the spray member 16 to remove the outer peripheral photoresist film. An example of spraying is shown. As a result, since the notch of the single-sided notch portion 14 does not appear on the outer periphery of the semiconductor wafer 11 to which the solvent 17 is sprayed, the sprayed solvent 17 does not hit the notch portion, and the solvent 17 is applied to the surface of the photoresist 15. It is no longer scattered and pattern breakage can be prevented.

また、図3には片面ノッチ部31が形成された半導体ウェハ32に、露光レンズ33、液体34を介して液浸露光を行う場合を示してあるが、拡大図にも示すように半導体ウェハ32の表面にはノッチ部が現れていないため、ショットでの液体を均一に盛ることができ、気泡の発生を防止することができるようになった。すなわち、気泡による屈折率のゆらぎから生じるショット内パターンのバラツキを防止することができる。   3 shows a case where immersion exposure is performed on the semiconductor wafer 32 formed with the one-side notch portion 31 via the exposure lens 33 and the liquid 34. As shown in the enlarged view, the semiconductor wafer 32 is also shown. Since the notch portion does not appear on the surface, liquid on the shot can be uniformly deposited, and generation of bubbles can be prevented. That is, it is possible to prevent variations in the pattern in the shot caused by fluctuation of the refractive index due to bubbles.

更に、図4に示すように、片面ノッチ部41が形成された半導体ウェハ42のラップ工程においては、余分なテープを切り離す際に片面ノッチ部41にて応力が集中することがなく、保護テープ43は半導体ウェハ42の全面に密着して貼り付けることが可能となる。この結果、半導体ウェハ42の裏面を研磨中に使用する水分が片面ノッチ部41から半導体ウェハ42と保護テープ43の間に染み込むこともなく、テープ剥がれも発生しない。   Further, as shown in FIG. 4, in the lapping process of the semiconductor wafer 42 on which the single-sided notch portion 41 is formed, stress is not concentrated on the single-side notch portion 41 when the excess tape is cut off, and the protective tape 43 Can be adhered in close contact with the entire surface of the semiconductor wafer 42. As a result, moisture used during polishing of the back surface of the semiconductor wafer 42 does not permeate between the semiconductor wafer 42 and the protective tape 43 from the single-sided notch portion 41, and tape peeling does not occur.

本発明の実施形態を示す図。The figure which shows embodiment of this invention. 本発明の実施形態に係わる半導体ウェハの機能を説明するための図。The figure for demonstrating the function of the semiconductor wafer concerning embodiment of this invention. 本発明の実施形態に係わる半導体ウェハの他の機能を説明するための図。The figure for demonstrating the other function of the semiconductor wafer concerning embodiment of this invention. 本発明の実施形態に係わる半導体ウェハの更に他の機能を説明するための図。The figure for demonstrating the further another function of the semiconductor wafer concerning embodiment of this invention. 従来の半導体ウェハを示す図。The figure which shows the conventional semiconductor wafer. 従来の半導体ウェハを用いた工程を説明するための図。The figure for demonstrating the process using the conventional semiconductor wafer. 従来の半導体ウェハを用いた他の工程を説明するための図。The figure for demonstrating the other process using the conventional semiconductor wafer. 従来の半導体ウェハを用いた更に他の工程を説明するための図。The figure for demonstrating the further another process using the conventional semiconductor wafer.

符号の説明Explanation of symbols

11、32、42…半導体ウェハ、12…表面、13…裏面、14、31、41…片面ノッチ部。   DESCRIPTION OF SYMBOLS 11, 32, 42 ... Semiconductor wafer, 12 ... Front surface, 13 ... Back surface, 14, 31, 41 ... Single-sided notch part.

Claims (2)

半導体ウェハにおいて、裏面から表面に達しない溝によりノッチ部が形成されていることを特徴とする半導体ウェハ。   A semiconductor wafer, wherein a notch is formed by a groove that does not reach the front surface from the back surface. 前記半導体ウェハの表面には各種プロセス工程によって素子が形成されることを特徴とする請求項1記載の半導体ウェハ。   2. The semiconductor wafer according to claim 1, wherein elements are formed on the surface of the semiconductor wafer by various process steps.
JP2004197914A 2004-07-05 2004-07-05 Semiconductor wafer Pending JP2006019623A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010010677A (en) * 2008-06-26 2010-01-14 Asml Netherlands Bv Lithography equipment and method of operating the same
CN101833248A (en) * 2009-03-13 2010-09-15 Asml荷兰有限公司 Substrate table, immersion lithographic apparatus and device manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010010677A (en) * 2008-06-26 2010-01-14 Asml Netherlands Bv Lithography equipment and method of operating the same
US8441609B2 (en) 2008-06-26 2013-05-14 Asml Netherlands B.V. Lithographic apparatus and a method of operating the lithographic apparatus
CN101833248A (en) * 2009-03-13 2010-09-15 Asml荷兰有限公司 Substrate table, immersion lithographic apparatus and device manufacturing method

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