JP2006018312A - Electronic circuit, electrooptical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic circuit for making low power consumption compatible with sufficient display quality, an electrooptical device, a method for driving an electrooptical device and an electronic apparatus. <P>SOLUTION: A driving current coresponding to digital data VDGDATAm or analog data voltage VANDATAm is supplied via a data line Xm to an organic EL element 21 in a pixel circuit 20 laid corresponding to the intersection of a scanning line Yn and the data line Xm. When halftone is controlled by digital gray scale to reduce power consumption, the digital data VDGDATAm is supplied to the pixel circuit 20. When halftone is controlled by analog gray scale to increase the display quality, the analog data voltage VANDATAm is supplied to the pixel circuit 20. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an electronic circuit, an electro-optical device, and an electronic apparatus.

  In recent years, an electro-optical device using an organic EL element has attracted attention. In this type of electro-optical device, there is an analog gradation method as a driving method for controlling the halftone of the organic EL element. (For example, patent document 1).

Japanese Patent Laid-Open No. 10-319908

  By the way, it is difficult in terms of accuracy to configure a DA converter circuit used in this analog gradation with a thin film transistor (TFT) employed in a pixel circuit, and it is common to use an external IC driver. It was.

  However, the DA converter circuit configured with an external IC driver has a problem that power consumption is larger than that of a TFT driver circuit formed on a display panel. In view of this, a digital gradation method that can reduce power consumption can be considered because a DA conversion circuit that generates multi-values (analog values) is not required. However, the digital gradation method has a problem that the display quality is inferior to the analog gradation method. On the other hand, one embodiment of the present invention is effective for the above problems.

  The electronic circuit of the present invention includes a first transistor and a second transistor, and in the first mode in which the conduction state of the second transistor is set by the first data, the second transistor Is controlled to be either an on state or an off state, and in the second mode in which the second transistor is set to be conductive by the second data, the second transistor is set to the second data. In accordance with the present invention, the second data is analog data.

  In the above electronic circuit, it is preferable that the first data is digital data.

  The electronic circuit further includes a capacitor, and the capacitor holds the first data as a charge in the first mode, and holds the second data as a charge in the second mode. You may make it do.

  The electronic circuit may further include a third transistor for resetting the charge held in the capacitor to a predetermined state.

  The electronic circuit may further include a fourth transistor disposed between the gate and the drain of the second transistor.

  In the electronic circuit, the first data and the second data may be supplied as a digital data voltage and an analog data voltage, respectively.

  In the electronic circuit, it is preferable that a threshold voltage of the second transistor is performed in the second mode.

  The electro-optical device of the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits, and each of the plurality of unit circuits includes an electro-optical element and the plurality of scanning lines. In a first mode, which includes a first transistor that conducts when one scanning line is selected, and a second transistor, and the luminance of the electro-optic element is set by first data, the electro-optic In the second mode in which the element is set to either a light-on state or a light-off state, and the luminance of the electro-optical element is set by second data, the luminance of the electro-optical element is set by the second data This corresponds to the conduction state of the second transistor.

  In the above electro-optical device, it is preferable that the first data and the second data are digital data and analog data, respectively.

  In the above electro-optical device, the plurality of data lines include a plurality of first data lines and a plurality of second data lines, and the first data is the plurality of first data lines. The second data may be supplied to the plurality of unit circuits via the plurality of second data lines.

In the electro-optical device, each of the plurality of unit circuits further includes a capacitive element, and the capacitive element holds the first data as a charge in the first mode, and the second mode. In the above, it is preferable to hold the second data as electric charges.
In the above electro-optical device, each of the plurality of unit circuits preferably further includes a fourth transistor disposed between the gate and the drain of the second transistor.

In the electro-optical device, the electro-optical element is preferably an EL element.
In the electro-optical device, it is preferable that a threshold voltage of the second transistor is performed in the second mode.

In the electro-optical device, it is preferable that the number of gradations in the first mode is smaller than the number of gradations in the second mode.
The above electro-optical device can be used as part of an electronic apparatus.

  In the above electronic apparatus, the electro-optical device is used as a display unit of the electronic apparatus, and when priority is given to display quality of the display unit, the second mode is used, and low power consumption of the display unit is achieved. If priority is given, the first mode may be used.

  Another electronic circuit according to the present invention includes a first transistor that is turned on when a scanning line is selected, and a capacitive element that holds a charge amount corresponding to a data signal supplied from the data line via the first transistor. And a second transistor whose conduction state is controlled based on the amount of charge held in the capacitive element and supplies an electric current to the electronic element relative to the conduction state, the capacitive element including the data signal Even when one of the binary data voltage and the multi-value data voltage is supplied, the charge amount corresponding to the data signal can be accumulated.

  According to this, by using the binary data voltage and the multi-value data voltage properly, for example, halftone can be expressed by two methods of digital gradation and analog gradation. As a result, for example, if you want to prioritize low power consumption without requiring much display quality, select digital gradation, and if display quality is required, select analog gradation to represent halftones. Can do.

  In this electronic circuit, a binary data voltage and a multi-value data voltage are supplied through the same first switching transistor.

  According to this, for example, even when the digital gradation and the analog gradation are performed, the binary data voltage for the digital gradation and the multi-value data for the analog gradation are respectively transmitted through the first switching transistor. A voltage is supplied to each capacitive element.

  The electronic circuit includes a third transistor that resets the amount of charge held in the capacitor.

  According to this, the binary data voltage held in the capacitive element is reset by the third transistor, and the capacitive element waits for the supply of the next new binary data voltage.

  In this electronic circuit, the fourth transistor is turned on in a conductive state based on a multi-valued data voltage, and a fourth transistor for compensating for the threshold voltage of the second transistor is connected between the gate and drain of the second transistor. did.

  According to this, the manufacturing variation of the threshold voltage of the second transistor is compensated by the fourth transistor, and the second transistor is brought into a conduction state corresponding to the multi-value data voltage without being influenced by the threshold voltage. Become.

  The electronic circuit includes a fifth transistor that determines drive timing of the electronic element in a conductive state based on a multi-value data voltage.

  According to this, the fifth transistor supplies the electronic element with a current amount corresponding to the conduction state based on the multi-value data voltage of the second transistor, and starts driving.

  In this electronic circuit, the electronic element is an EL element.

  According to this, the EL element emits light relative to the conduction state of the second transistor.

  In this electronic circuit, the EL element has a light emitting layer made of an organic material.

  According to this, the EL element is an organic EL element in which a light emitting layer is formed of an organic material.

  Another electro-optical device according to the present invention is an electro-optical device including a plurality of scanning lines, a plurality of data lines, and a plurality of unit circuits, wherein the plurality of data lines are provided to each of the plurality of unit circuits. A first data voltage output circuit for outputting a binary data voltage as a data signal via the second data circuit, and a second data voltage for outputting a multi-value data voltage to each of the plurality of unit circuits via the plurality of data lines. Data voltage output circuit.

  According to this, digital gradation is performed when a binary data voltage is input from the first data voltage output circuit, and analog gradation is performed when a multi-value data voltage is input from the second data voltage output circuit. it can.

  In this electro-optical device, a binary data voltage and a multi-value data voltage are supplied through the same data line.

  According to this, when performing digital gradation and analog gradation, a binary data voltage and a multi-value data voltage are supplied via the same data line in any case.

  In this electro-optical device, the binary data voltage and the multi-value data voltage are supplied via separate data lines.

    According to this, a binary data voltage and a multi-value data voltage are supplied to the unit circuit via different data lines depending on whether digital gradation is performed or analog gradation is performed.

  Another electro-optical device according to the invention includes a plurality of scanning lines, a plurality of data lines wired so as to intersect the scanning lines, and intersections of the scanning lines and the data lines. A unit circuit that is provided correspondingly and supplies a drive current corresponding to a data voltage supplied via the data line to the electro-optical element, and for digitally gradation the electro-optical element based on image data Control means for generating and outputting either a binary data voltage or a multi-value data voltage for analog gradation of the electro-optic element is provided.

  According to this, the control means can express the halftone with respect to the electro-optic element by two methods of digital gradation and analog gradation. As a result, for example, if you want to prioritize low power consumption without requiring much display quality, select digital gradation, and if display quality is required, select analog gradation to represent halftones. Can do.

  In this electro-optical device, the unit circuit includes a first transistor that is turned on when the scanning line is selected, and a binary value for digital gradation that is supplied from the data line through the first transistor. A capacitor element that holds a multi-value data voltage for analog gradation or a multi-value data voltage as an amount of charge, and a conduction state is controlled based on the amount of charge held in the capacitor element, and a current relative to the conduction state A second transistor for supplying a quantity to the electro-optic element.

  According to this, the capacitor element holds a binary data voltage at the time of digital gradation, and the second transistor becomes conductive / non-conductive based on the held binary data voltage. The capacitor element holds a multi-value data voltage in the case of analog gradation, and the second transistor is in a conductive state relative to the held multi-value data voltage.

  In this electro-optical device, the unit circuit includes a third transistor that resets the amount of charge held in the capacitive element.

  According to this, the binary data voltage held in the capacitive element is reset by the third transistor, and the capacitive element waits for the supply of the next new binary data voltage.

  In this electro-optical device, the unit circuit is turned on at the time of the analog gradation, and a fourth transistor for compensating the threshold voltage of the second transistor is connected between the gate and the drain of the second transistor.

  According to this, the manufacturing variation of the threshold voltage of the second transistor is compensated by the fourth transistor, and the second transistor is brought into a conduction state corresponding to the multi-value data voltage without being influenced by the threshold voltage. Become.

  In this electro-optical device, the unit circuit includes a fifth transistor that determines the drive timing of the electro-optical element during the analog gradation.

  According to this, the fifth transistor supplies the electro-optic element with a current amount relative to the conduction state based on the multi-value data voltage of the second transistor, and starts light emission.

  In this electro-optical device, the electro-optical element is an EL element.

  According to this, the EL element emits light relative to the conduction state of the second transistor.

  In this electro-optical device, the EL element has a light emitting layer made of an organic material.

  According to this, the EL element is an organic EL element in which a light emitting layer is formed of an organic material.

  In the electro-optical device, the control unit generates a binary data voltage for digital gradation of the electro-optical element in the low power consumption mode, and the non-low power consumption mode. A multi-value data voltage for analog gradation of the electro-optic element is created, and the electro-optic element is driven.

  According to this, the control means can represent the halftone with the digital gradation in the low power consumption mode and the analog gradation in the non-low power consumption mode with respect to the electro-optical element.

  In the electro-optical device, when the image data is the first display data, the control unit creates a binary data voltage for digital gradation of the electro-optical element, and the image data is the first data. In the case of the second display data having a display quality higher than that of the display data, a multi-value data voltage for analog gradation of the electro-optical element is created and the electro-optical element is driven.

  According to this, when the display quality is not required by the control means, it is possible to express a halftone with a digital gradation with respect to the electro-optic element, and when the display quality is required with an analog gradation. .

  In this electro-optical device, the control means includes a binary data voltage generation circuit for generating a binary data voltage for digital gradation of the electro-optical element, and a multivalue for analog gradation of the electro-optical element. And a multi-value data voltage generation circuit for generating the data voltage.

  According to this, a binary data voltage for digital gradation is generated in the binary data voltage generation circuit, and a multi-value data voltage for analog gradation is generated in the multi-value data voltage generation circuit. The

  In this electro-optical device, a first output circuit that outputs a binary data voltage from the binary data voltage generation circuit, and a multi-value data voltage generation circuit between the control unit and each data line. A second output circuit that outputs a multi-value data voltage, and outputs one of the binary data voltage from the first output circuit and the multi-value data voltage from the second output circuit. A switching circuit for outputting to the data line is provided.

  According to this, a binary data voltage is output from the first output circuit to the data line by the switching circuit at the digital gradation, and a multi-value data voltage is output from the second output circuit to the data line at the analog gradation.

  In this electro-optical device, the digital gradation is a time division gradation.

  According to this, the halftone of the electro-optic element is controlled by time division gradation.

  In this electro-optical device, the time-division gradation has a current level corresponding to the binary data voltage at the same time that the binary data voltage is written to the unit circuit corresponding to one scanning line that is sequentially selected. In this gradation method, a current is started to be supplied to the electro-optic element, and the current supply to the electro-optic element is cut off after a predetermined time.

  According to this, for the electro-optic element, the binary data voltage is written into the unit circuit corresponding to one scanning line that is sequentially selected, and at the same time, the current level corresponding to the binary data voltage is set. A halftone is controlled by supplying a current and shutting off the current supply after a predetermined time.

  The electro-optical device driving method according to the present invention includes a plurality of scanning lines, a plurality of data lines wired so as to intersect the scanning lines, and intersections of the scanning lines and the data lines. And a unit circuit that supplies a drive current corresponding to a data voltage supplied via the data line to the electro-optic element. In this case, a binary data voltage for digital gradation of the electro-optical element is created. In a non-low power consumption mode, a multi-value data voltage for analog gradation of the electro-optical element is generated. Then, the electro-optic element is driven.

  According to this, the halftone of the electro-optical element is controlled with digital gradation in the low power consumption mode and with analog gradation in the non-low power consumption mode.

  The electro-optical device driving method according to the present invention includes a plurality of scanning lines, a plurality of data lines wired so as to intersect the scanning lines, and intersections of the scanning lines and the data lines. And a unit circuit that supplies a drive current corresponding to a data voltage supplied via the data line to the electro-optical element. In the case of the display data, a binary data voltage for digital gradation of the electro-optic element is created, and the image data is the second display data having a higher display quality than the first display data. Generates a multi-value data voltage for analog gradation of the electro-optical element, and drives the electro-optical element.

  According to this, when the electro-optic element does not require display quality, halftone is controlled by digital gradation, and when display quality is required, halftone is controlled by analog gradation.

  In this electro-optical device driving method, the digital gradation is a time-division gradation.

  According to this, the halftone of the electro-optic element is controlled by time division gradation.

  In the driving method of the electro-optical device, the time-division gradation corresponds to the binary data voltage simultaneously with writing the binary data voltage to the unit circuit corresponding to one scanning line that is sequentially selected. In this gradation method, a current having a current level is started to be supplied to the electro-optical element, and the current supply to the electro-optical element is cut off after a predetermined time.

  According to this, for the electro-optic element, the binary data voltage is written into the unit circuit corresponding to one scanning line that is sequentially selected, and at the same time, the current level corresponding to the binary data voltage is set. A halftone is controlled by supplying a current and shutting off the current supply after a predetermined time.

  The electronic apparatus according to the present invention has the electro-optical device according to any one of claims 8 to 22 mounted thereon.

  According to this, both low power consumption and sufficient display quality can be achieved.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS.

  FIG. 1 is a block circuit diagram showing an electrical configuration of an organic EL display 10 as an electro-optical device. In FIG. 1, an organic EL display 10 is a display that can express halftones by either digital gradation or analog gradation. More specifically, in this embodiment, the digital gradation is a time division gradation, and the binary data voltage is applied to the pixel circuit corresponding to one scanning line sequentially selected in the time division gradation method. At the same time that the current having a current level corresponding to the binary data voltage is started to be supplied to the electro-optical element, and 64 gradations are obtained by a gradation method in which the current supply to the electro-optical element is cut off after a predetermined time. It comes to express. In analog gray scale, the drive transistor for supplying a current at a current level corresponding to a multi-value data voltage to the electro-optic element is driven by setting the gate-source voltage to the threshold voltage of the transistor. Is supposed to be expressed.

  Incidentally, in this time-division gradation, as shown in FIG. 3, the scanning (one frame) for displaying one image is divided into six, and the divided frames are set as sub-frames SF1 to SF6. In each of the subframes SF1 to SF6, each scanning line is selected in turn, and at the same time, the organic EL elements on the selected scanning line are turned on and individually turned off in turn after a certain time (light emission time). is there.

  Each of the subframes SF1 to SF6 includes light emission times (light emission periods) TL1 to TL6, and these light emission times (light emission periods) TL1 to TL6 are set as follows.

32TL1 = 16TL2 = 8TL3 = 4TL4 = 2TL5 = TL6
That is, each light emission time TL1 to TL6 is:
A time ratio of TL1: TL2: TL3: TL4: TL5: TL6 = 1: 2: 4: 8: 16: 32 is set.

  When the luminance gradation of “7” is obtained, the pixel circuit is driven to emit the organic EL element during the first to third subframes SF1 to SF3, and the fourth to sixth subframes SF4 to SF4 are emitted. At SF6, the pixel circuit is stopped and the organic EL element is turned off.

  In order to obtain a luminance gradation of “32”, the pixel circuit is driven to emit light in the sixth subframe SF6, and the organic EL element emits light. In the first to fifth subframes SF1 to SF5, the pixel is driven. The circuit is stopped and the organic EL element is turned off.

  Further, in order to obtain a luminance gradation of “44”, the pixel circuit is driven to emit light from the organic EL element in the third, fourth and sixth subframes SF3, SF4, SF6, and the first, first, In the second and fifth subframes SF1, SF2, and SF5, the pixel circuit is stopped and the organic EL element is turned off.

  In this way, a halftone can be obtained by appropriately selecting the subframes SF1 to SF6 for each frame.

  In FIG. 1, the organic EL display 10 includes a display panel unit 11, a scanning line driving circuit 12, a data line driving circuit 13, and a control circuit 14.

  The display panel unit 11, the scanning line driving circuit 12, the data line driving circuit 13, and the control circuit 14 of the organic EL display 10 may be configured by independent electronic components. For example, the scanning line driving circuit 12, the data line driving circuit 13, and the control circuit 14 may be configured by a one-chip semiconductor integrated circuit device. Alternatively, the display panel unit 11, the scanning line driving circuit 12, the data line driving circuit 13, and the control circuit 14 may be configured as an electronic component in which all or part of them are integrated. For example, the data line driving circuit 13 and the scanning line driving circuit 12 may be integrally formed on the display panel unit 11. All or a part of the scanning line driving circuit 12, the data line driving circuit 13, and the control circuit 14 may be configured by a programmable IC chip, and the function may be realized by software by a program written in the IC chip.

  As shown in FIG. 1, the display panel unit 11 has a plurality of electronic circuits or pixel circuits 20 as unit circuits arranged in a matrix. That is, each pixel circuit 20 includes a plurality (m) of data lines X1 to Xm (m is an integer) extending along the column direction and a plurality (n) of scanning lines Y1 to Yn extending along the row direction. It is arranged corresponding to the intersection with (n is an integer). Each pixel circuit 20 is arranged in a matrix by being connected between each corresponding data line X1 to Xm and each scanning line Y1 to Yn. Each pixel circuit 20 includes an organic EL element 21 having a light emitting layer made of an organic material as an electronic element or an electro-optical element. Note that a transistor described later formed in the pixel circuit 20 is usually composed of a thin film transistor (TFT).

  FIG. 2 is an electric circuit diagram for explaining the internal circuit configuration of the pixel circuit 20. For convenience of explanation, the pixel circuit 20 arranged at the point of the mth data line Xm and the nth scanning line Yn and connected between the data line Xm and the scanning line Yn will be described.

  The pixel circuit 20 includes a driving transistor Q1, a switching transistor Q2, a resetting transistor Q3, a compensating transistor Q4, a starting transistor Q5, a holding capacitor C1 and a capacitor C2 as capacitive elements. The switching transistor Q2 as the first transistor, the resetting transistor Q3 as the third transistor, the compensating transistor Q4 as the fourth transistor, and the starting transistor Q5 as the fifth transistor are composed of N-channel FETs. Has been. The driving transistor Q1 as the second transistor is composed of a P-channel FET.

  The drive transistor Q1 has a drain connected to the anode of the organic EL element 21 via a start transistor Q5, and a source connected to a power supply line L1 to which a power supply voltage VOEL is supplied. A holding capacitor C1 is connected between the gate of the driving transistor Q1 and the power supply line L1. A compensating transistor Q4 is connected between the gate and drain of the driving transistor Q1. The gate of the compensation transistor Q4 is connected to the second sub-scanning line Yn2 constituting the scanning line Yn, and the second scanning signal SCn2 is input from the second sub-scanning line Yn2.

  Further, the gate of the driving transistor Q1 is connected to the data line Xm via the capacitor C2 and the switching transistor Q2. The gate of the switching transistor Q2 is connected to the first sub-scan line Yn1 constituting the scan line Yn, and the first scan signal SCn1 is input from the first sub-scan line Yn1. The reset transistor Q3 is connected in parallel to the holding capacitor C1. The gate of the reset transistor Q3 is connected to the fourth sub-scanning line Yn4 constituting the scanning line Yn, and the reset signal SRESTn is input from the fourth sub-scanning line Yn4. The gate of the start transistor Q5 is connected to the third sub-scanning line Yn3 constituting the scanning line Yn, and the third scanning signal SCn3 is input from the third sub-scanning line Yn3.

  In the pixel circuit 20 configured as described above, a binary data voltage is written into the pixel circuit 20 corresponding to one sequentially selected scanning line, and at the same time, a current having a current level corresponding to the binary data voltage. Is supplied to the organic EL element 21, and after a predetermined time, the current supply to the organic EL element 21 is cut off and time division gradation is performed as follows. As shown in FIG. 4, in each of the subframes SF1 to SF6, the compensation transistor Q4 is in a non-conductive (off) state and the start transistor Q5 is in a conductive (on) state based on the second scanning signal SCn2 and the third scanning signal SCn3. Kept in a state. Then, in each of the subframes SF1 to SF6, by outputting a first scanning signal SCn1 and a reset signal SRESTn for controlling on / off of the switching transistor Q2 and the resetting transistor Q3 at a predetermined timing, halftone by digital gradation is output. Is supposed to be expressed.

  That is, when the scanning signal SCn1 is output to the first sub-scanning line Yn1 in a state where the compensation transistor Q4 is kept non-conductive and the start transistor Q5 is kept conductive, the switching transistor Q2 is turned on. Become. When the switching transistor Q2 is turned on, the charge amount corresponding to the binary value output from the data line Xm, that is, the digital data VDGDATAm that is either “L level” or “H level” is held. Accumulated in capacitor C1. The digital data VDGDATAm composed of the “L level” or “H level” is data for setting the driving transistor Q1 to either the on state or the off state. The holding capacitor C1 holding the digital data VDGDATAm holds the previously stored digital data VDGDATAm even when the scanning signal SCn1 disappears and the switching transistor Q2 is turned off.

  The driving transistor Q1 is controlled to be either on or off based on the contents of the stored digital data VDGDATAm. When the driving transistor Q1 is on, the organic EL element 21 is supplied with a driving current and emits light. On the other hand, when the driving transistor Q1 is in the OFF state, the organic EL element 21 stops supplying light and stops emitting light.

  Next, when the reset signal SRESTn is output to the fourth sub-scanning line Yn4, the reset transistor Q3 is turned from the off state to the on state. When the reset transistor Q3 is turned on, the power supply voltage VOEL is applied from the power supply line L1 to the holding capacitor C1 via the reset transistor Q3, and the previous digital data VDGDATAm is erased, and the gate of the drive transistor Q1 Is the potential of the power supply voltage VOEL. That is, the holding capacitor C1 is reset.

  When the holding capacitor C1 is reset, the driving transistor Q1 is turned off, and the organic EL element 21 that has emitted light based on the previous digital data VDGDATAm stops emitting light. And it waits for the light emission operation | movement performed next. That is, when time division gradation is performed, the light emission period TL1 to TL6 of the organic EL element 21 of each pixel circuit 20 is the light emission period from when the scanning signal SCn1 is output until the reset signal SRESTn is output. Become.

  On the other hand, in the pixel circuit 20, the analog gradation of the driving method using the gate-source voltage of the driving transistor Q1 as the threshold voltage of the transistor Q1 is performed as follows. As shown in FIG. 5, the reset transistor Q3 is held in a non-conductive state based on the reset signal SRESTn. Then, by outputting the first to third scanning signals SCn1 to SCn3 for controlling on / off of the switching transistor Q2, the compensating transistor Q4, and the starting transistor Q5 at a predetermined timing, halftone by analog gradation is expressed. It is supposed to be.

  That is, when the reset transistor Q3 is kept in a non-conductive state, when the H level scanning signal SCn1 is output to the first sub-scanning line Yn1, the switching transistor Q2 is turned on. At this time, the bias voltage (= VOEL) applied to the data line Xm at this time is applied to the capacitor C2 via the switching transistor Q2. Furthermore, in the previous cycle period (before the H level scanning signal SCn1 is output), the start transistor Q5 is in the ON state by the H level scanning signal SCn3 output to the third sub-scanning line Yn3. The organic EL element 21 is in a state where current flows. As a result, the drain potential of the driving transistor Q1 is sufficiently close to the ground potential of the organic EL element 21. Therefore, the drain potential of the driving transistor Q1 is sufficiently negative, and the driving transistor Q1 is kept open.

  Subsequently, when the scanning signal SCn2 output to the second sub-scanning line Yn2 changes from the L level to the H level, the compensation transistor Q4 is turned on. Further, the scanning signal SCn3 disappears (becomes L level) on the third sub-scanning line Yn3, and the start transistor Q5 is turned off.

  When the compensation transistor Q4 is turned on and the start transistor Q5 is turned off, the current of the power supply voltage VOEL flows to the gate of the driving transistor Q1, and the potential of the gate is raised. The driving transistor Q1 is turned off when the voltage applied to the gate is pushed up to the voltage Vg (= VOEL−Vth) obtained by subtracting the threshold voltage Vth of the driving transistor Q1 from the power supply voltage VOEL.

  Next, when the scanning signal SCn2 of the second sub-scanning line Yn2 becomes L level, the compensation transistor Q4 is turned off. At this time, the voltage Vg (= VOEL−Vth) applied to the gate of the driving transistor Q1 is held.

  When the voltage Vg (= VOEL−Vth) is held at the gate of the driving transistor Q1, the analog data voltage VANDATAm (<VOEL) is supplied from the data line Xm. At this time, since the driving transistor Q1 and the compensating transistor Q4 are in the off state, the gate side of the driving transistor Q1 of the capacitor C2 is in a floating state. As a result, due to the capacitive coupling of the capacitor C2 and the holding capacitor C1, the voltage Vg at the gate of the driving transistor Q1 drops according to the analog data voltage VANDATAm. In this state, the scanning signal SCn1 of the first sub-scanning line Yn1 becomes L level, and the switching transistor Q2 is turned off. When the switching transistor Q2 is turned off, the voltage Vg at the gate of the driving transistor Q1 is held at a potential lowered according to the analog data voltage VANDATAm.

  Subsequently, an H-level scanning signal SCn3 is output from the third sub-scanning line Yn3, and the start transistor Q5 is turned on. When the start transistor Q5 is turned on, the drive transistor Q1 becomes conductive according to the value of the analog data voltage VANDATAm, and a drive current according to the analog data voltage VANDATAm is supplied to the organic EL element 21. The organic EL element 21 emits light with a luminance corresponding to the analog data voltage VANDATAm.

  The scanning line driving circuit 12 selects one of the plurality of scanning lines Y1 to Yn, that is, outputs a scanning signal and drives a group of pixel circuits 20 connected to the selected scanning line. It is. The scanning line driving circuit 12 outputs the scanning signals SC1 to SCn at predetermined timings to the scanning lines Y1 to Yn based on various signals from the control circuit 14, respectively.

  More specifically, as described above, a binary data voltage is written into the pixel circuit 20 corresponding to one scanning line that is sequentially selected, and at the same time, a current at a current level corresponding to the binary data voltage is supplied to the organic EL element 21. In the gradation method in which the current supply to the organic EL element 21 is interrupted after a predetermined time, the pixel circuit groups on the scanning lines Y1 to Yn are sequentially arranged in the subframes SF1 to SF6 constituting one frame. It is necessary to drive. Therefore, the scanning line driving circuit 12 sequentially selects the scanning signals SC1 to SCn so as to sequentially select the scanning lines Y1 to Yn in the period of the subframes SF1 to SF6 in order to display an image of one frame. Generate and output. Further, the scanning line driving circuit 12 outputs the scanning signals SC1 to SCn corresponding to the scanning lines Y1 to Yn, respectively, and when a predetermined time (light emission time) has elapsed, the reset signal SREST1 is sent to the corresponding scanning lines Y1 to Yn. ~ SRESTn are output respectively.

  That is, in each of the subframes SF1 to SF6, it is set to emit light for the light emission times TL1 to TL6, respectively.

  On the other hand, the scanning line driving circuit 12 applies the scanning signals SC1 to SCn to the scanning lines Y1 to Yn at a predetermined timing based on the various signals from the control circuit 14 as described above in the analog gradation described above. Output.

  As shown in FIG. 2, the data line driving circuit 13 has a digital data voltage output circuit 13a as a first data voltage output circuit and analog data as a second data voltage output circuit for each of the data lines X1 to Xm. A voltage output circuit 13b is provided. The digital data voltage output circuit 13a receives the digital data VDGDATA1 to VDGDATAm from the control circuit 14, and the digital data VDGDATA1 to VDGDATAm is synchronized with the scanning signals SC1 to SCn via the first switch Q11. Output to lines X1 to Xm. On the other hand, the analog data voltage output circuit 13b receives the analog data voltages VANDATA1 to VANDATAm from the control circuit 14, and the analog data voltages VANDATA1 to VANDATAm are synchronized with the scanning signals SC1 to SCn via the second switch Q12. Output to the corresponding data lines X1 to Xm.

  The first switch Q11 and the second switch Q12 are switches that select any one of the digital data VDGDATA1 to VDGDATAm and the analog data voltages VANDATA1 to VANDATAm and output them to the respective data lines X1 to Xm, and are configured by N-channel FETs. ing. The first switch Q11 is turned on when the first control signal SG1 is input to the gate terminal from the control circuit 14, and outputs the digital data VDGDATA1 to VDGDATAm to the data lines X1 to Xm. The second switch Q12 is turned on when the second control signal SG2 is input to the gate terminal from the control circuit 14, and outputs the analog data voltages VANDATA1 to VANDATAm to the data lines X1 to Xm.

  The data lines X1 to Xm are supplied with a bias voltage (power supply voltage VOEL) when the digital data VDGDATA1 to VDGDATAm and the analog data voltages VANDATA1 to VANDATAm are not supplied.

  That is, when the scanning line driving circuit 12 outputs a scanning signal to one scanning line, in the digital gradation, the data line driving circuit 13 applies digital data VDGDATA1 to each pixel circuit 20 on the selected scanning line. Outputs VDGDATAm. In the analog gradation, the data line driving circuit 13 outputs analog data voltages VANDATA1 to VANDATAm to each pixel circuit 20 on the selected scanning line.

  A control circuit 14 serving as a control means, a binary data voltage generation circuit, or a multi-value data voltage generation circuit inputs image data D from an external device (not shown), and controls halftone based on the image data D. It is determined whether to perform in analog gradation or analog gradation. In this embodiment, when the image data D is image data as first display data for displaying a still image such as a character, halftone control is performed with digital gradation. When the image data D is image data as second display data for displaying a moving image such as an animation or movie, halftone control is performed with analog gradation. In other words, the control circuit 14 performs the digital gradation (time division gradation) when the display quality of the still image or the like is not particularly required, and performs the analog gradation when the display quality of the moving image or the like is necessary. In this manner, the scanning line driving circuit 12 and the data line driving circuit 13 are controlled.

  When the time division gray scale is executed, the control circuit 14 divides one frame into six to express the image data D of one frame on the organic EL display 10, and the six divided subframes SF1 are divided. Use SF6 to express one image with 64 gradations.

  The control circuit 14 supplies digital data VDGDATA1 for the image data D of one frame to be supplied to the pixel circuits 20 on the scanning lines Y1 to Yn for the first to sixth subframes SF1 to SF6 with respect to the data line driving circuit 13. ~ VDGDATAm is generated. At this time, the control circuit 14 uses the digital data VDGDATA1 to VDGDATAm for expressing the gradation of “1” in the first subframe SF1 and the digital data VDGDATA1 to VDGDATAm for expressing the gradation of “2” to the second subframe. Digital data VDGDATA1 to VDGDATAm for expressing the gradation of “4” are created in the third subframe SF3 in the frame SF2. Further, the control circuit 14 uses the digital data VDGDATA1 to VDGDATAm for expressing the gradation of “8” in the fourth subframe SF4 and the digital data VDGDATA1 to VDGDATAm for expressing the gradation of “16” in the fifth subframe. Created in SF5 respectively. Furthermore, the control circuit 14 creates digital data VDGDATA1 to VDGDATAm for expressing the gradation of “32” in the sixth subframe SF6.

  The digital data VDGDATA1 to VDGDATAm of the first to sixth subframes SF1 to SF6 are output to the digital data voltage output circuit 13a of the data line driving circuit 13 at a predetermined timing. At this time, the control circuit 14 outputs the first control signal SG1 to the first switch Q11 of the data line driving circuit 13.

  The control circuit 14 sequentially selects the scanning lines generated in the scanning line driving circuit 12 with respect to the scanning line driving circuit 12 in the digital gradation, and scan signals SCn (SCn1 to SCn3) for controlling the pixel circuit 20. Is controlled in order to output in order.

  Also, the timing for sequentially outputting the reset signals SREST1 to SRESTn for the scanning lines Y1 to Yn in the subframes SF1 to SF6 to the scanning line driving circuit 12 is controlled. Incidentally, in the first subframe SF1, the scanning line driving circuit 12 outputs the reset signals SREST1 to SRESTn after the scanning signals SC1 to SCn are output and the time TL1 has elapsed. Incidentally, in the second subframe SF2, the scanning signal SCn1 is output, and after the time TL2 (= 2 × TL1) has elapsed, the scanning signal SCn1 is output in the third subframe SF3 and TL3 (= 4 × TL1). In the fourth subframe SF4 after the lapse of time, the reset signals SREST1 to SRESTn are output after the scanning signal SCn1 is output and TL4 (= 8 × TL1) has elapsed. In the fifth subframe SF5, after the scanning signal SCn1 is output and TL5 (= 16 × TL1) has elapsed, the scanning signal SCn1 is output in the sixth subframe SF6 and TL6 (= 32 × TL1). After a lapse of time, reset signals SREST1 to SRESTn are output, respectively.

  On the other hand, when executing the analog gradation, the control circuit 14 displays the scanning line Y1 for each scanning line Y1 to Yn selected in order to represent the image data D of one frame on the organic EL display 10. The analog data voltages VANDATA1 to VANDATAm for the pixel circuits 20 connected to .about.Yn are generated based on the image data D of one frame. The control circuit 14 outputs the generated analog data voltages VANDATA1 to VANDATAm to the analog data voltage output circuit 13b of the data line driving circuit 13 at a predetermined timing. At this time, the control circuit 14 outputs the second control signal SG2 to the second switch Q12 of the data line driving circuit 13.

  The control circuit 14 sequentially selects the scanning lines generated in the scanning line driving circuit 12 with respect to the scanning line driving circuit 12 in the analog gradation, and controls each pixel circuit 20 on the selected scanning line. The timing at which the scanning signals SCn (SCn1 to SCn3) are sequentially output is controlled.

  Next, the operation of the organic EL display 10 configured as described above will be described.

  When the image data D is input from the external device, the control circuit 14 determines whether the image data D is still image data or moving image data. When the image data D is still image data, the digital gradation mode is set. When the image data D is moving image data, the analog gradation mode is set.

(Digital gradation mode)
First, the digital gradation mode will be described. The control circuit 14 supplies digital data VDGDATA1 for the image data D of one frame to be supplied to the pixel circuits 20 on the scanning lines Y1 to Yn for the first to sixth subframes SF1 to SF6 with respect to the data line driving circuit 13. ~ VDGDATAm is generated. The digital data VDGDATA1 to VDGDATAm of the first to sixth subframes SF1 to SF6 are output to the digital data voltage output circuit 13a of the data line driving circuit 13 at a predetermined timing. At this time, the control circuit 14 outputs the first control signal SG1 to the first switch Q11 of the data line driving circuit 13.

  Further, the control circuit 14 sequentially selects the scanning lines generated in the scanning line driving circuit 12 with respect to the scanning line driving circuit 12 and sequentially selects the scanning signals SCn (SCn1 to SCn3) for controlling the pixel circuit 20. Control the output timing. Further, the control circuit 14 controls the timing at which the scanning line driving circuit 12 sequentially outputs reset signals SREST1 to SRESTn for the scanning lines Y1 to Yn in the subframes SF1 to SF6.

  Then, the scanning line driving circuit 12 sequentially outputs the scanning signals SCn (SCn1 to SCn3) for the first subframe SF1 and sequentially selects the scanning lines Yn. Further, the scanning line driving circuit 12 outputs the scanning signal SCn and outputs the reset signal SRESTn after the TL1 time has elapsed.

  On the other hand, every time each scanning line Yn is selected, the data line driving circuit 13 sequentially outputs the digital data VDGDATA1 to VDGDATAm in the first subframe SF1 to each pixel circuit 20 on the selected scanning line. Accordingly, each pixel circuit 20 on the selected scanning line operates (turns on or off) based on the digital data VDGDATA1 to VDGDATAm. Each pixel circuit 20 is turned off in response to the reset signal SRESTn after the TL1 time has elapsed.

  When the supply of the digital data VDGDATA1 to VDGDATAm to the respective pixel circuits 20 on the last scanning lines Y1 to Yn of the first subframe SF1 is completed, the scanning line driving circuit 12 scans the scanning signal SCn (for the second subframe SF2). SCn1 to SCn3) are sequentially output to sequentially select the scanning lines Y1 to Yn. The scanning line driving circuit 12 outputs the scanning signal SCn and outputs reset signals SREST1 to SRESTn after TL2 (= 2 × TL1) time has elapsed.

  On the other hand, the data line driving circuit 13 sequentially outputs the digital data VDGDATA1 to VDGDATAm in the second subframe SF2 to each pixel circuit 20 on the selected scanning line in the same manner as described above. Each pixel circuit 20 on the selected scanning line operates (turns on or off) based on the digital data VDGDATA1 to VDGDATAm in the same manner as described above, and turns off in response to the reset signal SRESTn after the TL2 time has elapsed.

  Thereafter, the same operation is repeated for the third subframe SF3 to the sixth subframe SF6 to express one frame image. When the image display operation for one frame is completed, the image display operation for the next one frame is similarly performed.

(Analog gradation mode)
Next, the analog gradation mode will be described. The control circuit 14 outputs analog data voltages VANDATA1 to VANDATAm for the pixel circuits 20 connected to the scanning lines Y1 to Yn for each of the scanning lines Y1 to Yn that are sequentially selected based on the image data D of one frame. Generate. The control circuit 14 outputs the generated analog data voltages VANDATA1 to VANDATAm to the analog data voltage output circuit 13b of the data line driving circuit 13 at a predetermined timing. At this time, the control circuit 14 outputs the second control signal SG2 to the second switch Q12 of the data line driving circuit 13. Further, the control circuit 14 sequentially selects the scanning lines generated in the scanning line driving circuit 12 with respect to the scanning line driving circuit 12, and controls the scanning signal SCn for controlling each pixel circuit 20 on the selected scanning line. The timing for outputting (SCn1 to SCn3) in order is controlled.

  Then, the scanning line driving circuit 12 sequentially outputs the scanning signals SCn (SCn1 to SCn3) and sequentially selects the scanning lines Y1 to Yn. On the other hand, every time each scanning line Yn is selected, the data line driving circuit 13 sequentially outputs analog data voltages VANDATA1 to VANDATAm to each pixel circuit 20 on the selected scanning line. Accordingly, the organic EL element 21 of each pixel circuit 20 on the selected scanning line emits light with luminance corresponding to the analog data voltages VANDATA1 to VANDATAm.

  Next, the characteristics of the organic EL display 10 configured as described above will be described below.

  According to the present embodiment, the halftone is expressed by digital gradation in the case of a still image and analog gradation in the case of a moving image. Conversely, in still images, analog gradation can be used when display quality is required, and digital gradation can be used in the case of moving images. Further, digital gradation can be used when displaying characters, and analog gradation when displaying images. In other words, when the display quality is not so required, the halftone is expressed by digital gradation with low power consumption, and when the display quality is required, the halftone is expressed by analog gradation.

  Therefore, the organic EL display 10 can achieve both low power consumption and sufficient display quality.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment in the pixel circuit 20 as an electronic circuit or a unit circuit. Therefore, the difference will be described in detail.

  As shown in FIG. 6, unlike the first embodiment, the pixel circuit 20 of the present embodiment omits the compensation transistor Q4, the start transistor Q5, and the capacitor C2. That is, the drain of the driving transistor Q1 is connected to the anode of the organic EL element 21, and the cathode of the organic EL element 21 is grounded. The source of the driving transistor Q1 is connected to the power supply line L1 to which the power supply voltage VOEL is supplied. A holding capacitor C1 is connected between the gate of the driving transistor Q1 and the power supply line L1.

  Further, the gate of the driving transistor Q1 is connected to the data line Xm via the switching transistor Q2. The gate of the switching transistor Q2 is connected to the first sub-scan line Yn1 constituting the scan line Yn, and the first scan signal SCn1 is input from the first sub-scan line Yn1. The reset transistor Q3 is connected in parallel to the holding capacitor C1. The gate of the reset transistor Q3 is connected to the fourth sub-scanning line Yn4 constituting the scanning line Yn, and the reset signal SRESTn is input from the fourth sub-scanning line Yn4.

  Therefore, in this embodiment, the scanning line Yn is composed of the first sub-scanning line Yn1 and the fourth sub-scanning line Yn4, and the second sub-scanning line Yn2 and the third sub-scanning line Yn3 are omitted. Yes.

  In the pixel circuit 20, when digital gradation is performed, when the scanning signal SCn1 is output to the first sub-scanning line Yn1, the switching transistor Q2 is turned on. When the switching transistor Q2 is turned on, the amount of charge corresponding to the digital data VDGDATAm having a value of "L level" or "H level" from the digital data voltage output circuit 13a via the data line Xm is held. Accumulated in capacitor C1.

  The driving transistor Q1 is controlled to either an on state or an off state based on the contents of the stored digital data VDGDATAm. When the driving transistor Q1 is on, the organic EL element 21 is supplied with a driving current and emits light. On the other hand, when the driving transistor Q1 is in the OFF state, the organic EL element 21 stops supplying light and stops emitting light.

  Next, when the reset signal SRESTn is output to the fourth sub-scanning line Yn4, the reset transistor Q3 is turned from the off state to the on state. When the reset transistor Q3 is turned on, the power supply voltage VOEL is applied from the power supply line L1 to the holding capacitor C1 via the reset transistor Q3, and the previous digital data VDGDATAm is erased, and the gate of the drive transistor Q1 Is the potential of the power supply voltage VOEL. That is, the holding capacitor C1 is reset.

  Therefore, when performing time-division gradation similar to the above embodiment, the light emission periods TL1 to TL6 of the organic EL elements 21 of the pixel circuits 20 are from the output of the scanning signal SCn1 to the output of the reset signal SRESTn. The interval is the light emission period.

  On the other hand, in the pixel circuit 20, when performing analog gray scale driving with the gate-source voltage of the driving transistor Q 1 being the threshold voltage of the transistor Q 1, the reset transistor Q 3 is non-conductive based on the reset signal SRESTn. Kept in a state. Then, by outputting a first scanning signal SCn1 for controlling on / off of the switching transistor Q2 at a predetermined timing, a halftone by analog gradation is expressed.

  That is, when the scanning signal SCn1 is output to the first sub-scanning line Yn1, the switching transistor Q2 is turned on. When the switching transistor Q2 is turned on, a charge amount corresponding to the analog data voltage VANDATAm supplied from the analog data voltage output circuit 13b via the data line Xm is accumulated in the holding capacitor C1. The driving transistor Q1 becomes conductive according to the value of the analog data voltage VANDATAm stored in the holding capacitor C1. A driving current corresponding to the conduction state of the driving transistor Q1 is supplied to the organic EL element 21. The organic EL element 21 emits light with a luminance corresponding to the analog data voltage VANDATAm.

  Also in the pixel circuit 20 of the present embodiment, the halftone can be expressed by digital gradation in the case of a still image and analog gradation in the case of a moving image. Conversely, in still images, analog gradation can be used when display quality is required, and digital gradation can be used in the case of moving images. Further, digital gradation can be used when displaying characters, and analog gradation when displaying images. In other words, halftones can be expressed with digital gradations with low power consumption when display quality is not so required, and halftones can be expressed with analog gradation when display quality is required. Therefore, also in the organic EL display 10 configured by the pixel circuit 20 of the present embodiment, both low power consumption and sufficient display quality can be achieved.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment is different from the first embodiment in the pixel circuit 20 as an electronic circuit or a unit circuit. Therefore, the difference will be described in detail.

  As shown in FIG. 7, in the pixel circuit 20 of the present embodiment, the compensation transistor Q4 and the start transistor Q5 are omitted, unlike the first embodiment. That is, the drain of the driving transistor Q1 is connected to the anode of the organic EL element 21, and the cathode of the organic EL element 21 is grounded. The source of the driving transistor Q1 is connected to the power supply line L1 to which the power supply voltage VOEL is supplied. A holding capacitor C1 is connected between the gate of the driving transistor Q1 and the power supply line L1.

  The gate of the driving transistor Q1 is connected to the data line Xm through the switching transistor Q2. The gate of the switching transistor Q2 is connected to the first sub-scan line Yn1 constituting the scan line Yn, and the first scan signal SCn1 is input from the first sub-scan line Yn1.

  Further, the reset transistor Q3 has a source connected to the power supply line L1 and a gate connected to the fourth sub-scanning line Yn4 constituting the scanning line Yn. The drain of the reset transistor Q3 is connected to the source of a compensation transistor Q6 made of a P-channel transistor. The drain of the compensating transistor Q6 is connected to the gate of the driving transistor Q1. The compensation transistor Q6 has its gate and drain connected to each other, that is, diode-connected.

  In the pixel circuit 20, when digital gradation is performed, when the reset transistor Q3 is off and the H level scanning signal SCn1 is output to the first sub-scanning line Yn1, the switching transistor Q2 is turned on. Become. When the switching transistor Q2 is turned on, the amount of charge corresponding to the digital data VDGDATAm having a value of "L level" or "H level" from the digital data voltage output circuit 13a via the data line Xm is held. Accumulated in capacitor C1.

  The driving transistor Q1 is controlled to either an on state or an off state based on the contents of the stored digital data VDGDATAm. When the driving transistor Q1 is on, the organic EL element 21 is supplied with a driving current and emits light. On the other hand, when the driving transistor Q1 is in the OFF state, the organic EL element 21 stops supplying light and stops emitting light.

  Next, when the reset signal SRESTn is output to the fourth sub-scanning line Yn4, the reset transistor Q3 is turned from the off state to the on state. When the reset transistor Q3 is turned on, the power supply voltage VOEL is applied from the power supply line L1 to the compensation transistor Q6 via the reset transistor Q3, and the compensation transistor Q6 is turned on. When the compensation transistor Q6 is turned on, the gate voltage of the drive transistor Q1 becomes a voltage obtained by subtracting the threshold voltage of the compensation transistor Q6 from the power supply voltage VOEL. That is, when the driving transistor Q1 is turned on based on the contents of the digital data VDGDATAm and the organic EL element 21 is supplied with a driving current and emits light, the gate voltage of the driving transistor Q1 rises. That is, the holding capacitor C1 is reset, the driving transistor Q1 is turned off, and the organic EL element 21 stops emitting light.

  Therefore, when performing time-division gradation similar to the above embodiment, the light emission periods TL1 to TL6 of the organic EL elements 21 of the pixel circuits 20 are from the output of the scanning signal SCn1 to the output of the reset signal SRESTn. The interval is the light emission period.

  On the other hand, in the pixel circuit 20, when performing analog gradation of a driving method in which the gate-source voltage of the driving transistor Q 1 is set to the threshold voltage of the transistor Q 1, first, the scanning signal SCn 1 is applied to the first sub-scanning line Yn 1. Is output, the switching transistor Q2 is turned on. At this time, the bias voltage (= VOEL) applied to the data line Xm at this time is applied to the capacitor C2 via the switching transistor Q2.

  Subsequently, an H level reset signal SRESTn is output to the fourth sub-scanning line Yn4 to turn on the reset transistor Q3. When the reset transistor Q3 is turned on, the power supply voltage VOEL is applied to the compensation transistor Q6 via the reset transistor Q3. Thus, when the compensation transistor Q6 is turned on and the gate voltage of the drive transistor Q1 is pushed up to the threshold voltage (Vth) of the compensation transistor Q6, the drive transistor Q1 is turned off.

  Next, when the reset signal SRESTn disappears, the reset transistor Q3 is turned off. At this time, the voltage Vg (= VOEL−Vth) applied to the gate of the driving transistor Q1 is held.

  When the voltage Vg (= VOEL−Vth) is held at the gate of the driving transistor Q1, the analog data voltage VANDATAm (<VOEL) is supplied from the data line Xm. At this time, since the driving transistor Q1 and the resetting transistor Q3 are in an off state, the gate side of the driving transistor Q1 of the capacitor C2 is in a floating state. As a result, due to the capacitive coupling of the capacitor C2 and the holding capacitor C1, the voltage Vg at the gate of the driving transistor Q1 drops according to the analog data voltage VANDATAm.

  In this state, the scanning signal SCn1 of the first sub-scanning line Yn1 disappears and the switching transistor Q2 is turned off. When the switching transistor Q2 is turned off, the capacitor C2 is brought into a floating state, and the voltage Vg is held at the potential lowered at the gate of the driving transistor Q1 according to the analog data voltage VANDATAm.

  As a result, the driving transistor Q1 becomes conductive according to the value of the analog data voltage VANDATAm, and a driving current according to the analog data voltage VANDATAm is supplied to the organic EL element 21. The organic EL element 21 emits light with a luminance corresponding to the analog data voltage VANDATAm. The light is emitted until the next light emission operation.

  Also in the pixel circuit 20 of the present embodiment, the halftone can be expressed by digital gradation in the case of a still image and analog gradation in the case of a moving image. Conversely, in still images, analog gradation can be used when display quality is required, and digital gradation can be used in the case of moving images. Further, digital gradation can be used when displaying characters, and analog gradation when displaying images. In other words, halftones can be expressed with digital gradations with low power consumption when display quality is not so required, and halftones can be expressed with analog gradation when display quality is required. Therefore, also in the organic EL display 10 configured by the pixel circuit 20 of the present embodiment, both low power consumption and sufficient display quality can be achieved.

(Fourth embodiment)
Next, application of an electronic apparatus equipped with the organic EL display 10 as the electro-optical device described in the first embodiment will be described with reference to FIGS. The organic EL display 10 can be applied to various electronic devices such as a mobile personal computer, a mobile phone, and a digital camera.

  FIG. 8 is a perspective view showing the configuration of the mobile personal computer. In FIG. 8, a personal computer 60 includes a keyboard 61 and a main body 62 and a display unit 63 using the organic EL display 10. Even in this case, the display unit 63 using the organic EL display 10 exhibits the same effect as that of the above embodiment. As a result, the personal computer 60 can realize both low power consumption and sufficient display quality.

  FIG. 9 is a perspective view showing the configuration of the mobile phone. In FIG. 9, the mobile phone 70 includes a plurality of operation buttons 71, an earpiece 72, a mouthpiece 73, and a display unit 74 using the organic EL display 10. Even in this case, the display unit 74 using the organic EL display 10 exhibits the same effect as that of the above embodiment. As a result, the mobile phone 70 can realize both low power consumption and sufficient display quality.

  In addition, you may change embodiment of this invention as follows.

  In the first to third embodiments, as shown in FIGS. 1, 6 and 7, the digital data VDGDATAm and the analog data voltage VANDATAm are supplied to the holding capacitor C1 via the common switching transistor Q2. As shown in FIGS. 10, 11 and 12, the data line Xm is composed of a first sub data line Xm1 and a second sub data line Xm2. The first sub data line Xm1 connects the digital data voltage output circuit 13a via the first switch Q11. The second sub data line Xm2 connects the analog data voltage output circuit 13b via the second switch Q12. The first sub data line Xm1 is connected to the first switching transistor Q2a, and the second sub data line Xm2 is connected to the second switching transistor Q2b.

  With this configuration, the first switching transistor Q2a is turned on to supply the digital data VDGDATAm from the digital data voltage output circuit 13a to the holding capacitor C1. Also, the second switching transistor Q2b is turned on to supply the analog data voltage output circuit 13b to the holding capacitor C1.

  That is, the digital data VDGDATAm and the analog data voltage VANDATAm may be supplied to the holding capacitor C1 via the first switching transistor Q2a and the second switching transistor Q2b, respectively.

  In this case, the same effects as those of the first to third embodiments are obtained.

  In the first embodiment, a binary data voltage is written in the pixel circuit 20 corresponding to one scanning line sequentially selected for digital gradation, and at the same time, a current having a current level corresponding to the binary data voltage is applied to the organic EL. The supply to the element 21 was started, and the current was supplied to the organic EL element 21 after a predetermined time, and the time division gradation was performed. Instead of this, it may be implemented with time-division gradation using a simultaneous lighting method. Further, as one of the digital gradations, an area gradation may be used. That is, the pixel circuit 20 is used as a subpixel, and a plurality of subpixels are grouped. When digital gradation is performed, halftones may be expressed by controlling an appropriate number of sub-pixels belonging to the set to two states of non-light emission and light emission, respectively.

  In the first embodiment, the reset signal S RESTn is input to the gate of the reset transistor Q3 via the fourth sub-scanning line Yn4, and the binary data voltage VDGDATAm held in the holding capacitor C1 at the time-division gray scale. Was reset.

  For this, the fourth sub-scanning line Yn4 is omitted. Further, the reset transistor Q3 is changed from the N-channel FET to the P-channel FET, and the gate of the reset transistor Q3 changed to the P-channel FET is connected to the first sub-scanning line Yn1. Then, the first scanning signal SCn1 output to the first sub-scanning line Yn1 is converted into a ternary signal. That is, the first scanning signal SCn1 is a positive potential that turns on only the switching transistor Q2, a zero potential that turns off both the switching transistor Q2 and the reset transistor Q3, and only turns on the reset transistor Q3. This signal is a negative potential.

  Accordingly, in this case as well, the same effect as described above can be obtained, and the circuit scale can be reduced and the aperture ratio of the pixel circuit 20 can be increased by omitting the fourth sub-scanning line Yn4.

  In the first embodiment, resetting is performed after a predetermined time using the reset transistor Q3 in the time-division gradation. This may also be applied to the time division gradation method described below. That is, when the data voltage is written to all the pixel circuits 20, the reverse bias voltage is applied to the counter electrode (cathode) side of the organic EL element 21. After the data voltage has been written, a forward bias voltage is applied to the counter electrode side of the organic EL element 21 to supply a current having a current level corresponding to the data voltage. After a predetermined period, the reverse bias voltage is again applied to the counter electrode side of the organic EL element 21 to reset it.

  In the above embodiment, the pixel circuit 20 is embodied as an electronic circuit to obtain a suitable effect. However, the present invention may be embodied in an electronic circuit that drives a light emitting element such as an LED or FED other than the organic EL element 21.

In the above embodiment, the organic EL element 21 is embodied. However, the organic EL element 21 may be embodied in an inorganic EL element. That is, you may apply to the inorganic EL display which consists of an inorganic EL element.
(The invention's effect)

  According to the present invention, it is possible to achieve both low power consumption and sufficient display quality.

The block circuit diagram which shows the circuit structure of the organic electroluminescent display for demonstrating 1st Embodiment. Similarly, a circuit diagram for explaining internal circuit configurations of a pixel circuit and a data line driving circuit. Explanatory drawing for demonstrating the time division | segmentation gradation of this embodiment. The timing chart for demonstrating selection of the scanning line in a time division gradation. 6 is a timing chart for explaining selection of a scanning line in analog gradation. A circuit diagram for explaining a pixel circuit of a second embodiment. A circuit diagram for explaining a pixel circuit of a 3rd embodiment. The perspective view which shows the structure of the mobile type personal computer for describing 4th Embodiment. The perspective view which shows the structure of the mobile telephone for describing 4th Embodiment. FIG. 6 is a circuit diagram for explaining another example of the pixel circuit of the first embodiment. FIG. 6 is a circuit diagram for explaining another example of the pixel circuit of the second embodiment. A circuit diagram for explaining another example of a pixel circuit of a 3rd embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Organic EL display as electro-optical device 11 Display panel part 12 Data line drive circuit 13 Scan line drive circuit 14 Control circuit as control means 20 Pixel circuit as electronic circuit or unit circuit 21 Organic as electronic element or electro-optical element EL element 60 Personal computer as electronic device 70 Mobile phone as electronic device 13a Digital data voltage current output circuit as first output circuit 13b Analog data voltage output circuit as second output circuit Q1 As second transistor Driving transistor Q2 Switching transistor as a first transistor Q3 Reset transistor as a third transistor Q4 Compensating transistor as a fourth transistor Q5 Starting transistor as a fifth transistor Data capacitor SC1 Capacitance element Y1-Yn Scan line X1-Xm Data line SCn Scan signal VDGDATA1-VDGDATAm Digital data as binary data voltage VANDATA1-VANDATAm Analog data voltage as multi-value data voltage

Claims (17)

A first transistor;
A second transistor;
In the first mode in which the conduction state of the second transistor is set by the first data, the second transistor is controlled to be either an on state or an off state;
In the second mode in which the second data sets the conduction state of the second transistor, the second transistor is set to a conduction state according to the second data,
The second data is analog data;
An electronic circuit characterized by The electronic circuit according to claim 1.
The first data is digital data;
An electronic circuit characterized by The electronic circuit according to claim 1 or 2,
In addition, including a capacitive element,
The capacitive element holds the first data as a charge in the first mode, and holds the second data as a charge in the second mode;
An electronic circuit characterized by The electronic circuit according to claim 3.
A third transistor for resetting the charge held in the capacitive element to a predetermined state;
An electronic circuit characterized by The electronic circuit according to any one of claims 1 to 4,
Further comprising a fourth transistor disposed between the gate and drain of the second transistor;
An electronic circuit characterized by The electronic circuit according to any one of claims 1 to 5,
The first data and the second data are supplied as a digital data voltage and an analog data voltage, respectively;
An electronic circuit characterized by The electronic circuit according to any one of claims 1 to 6,
A threshold voltage of the second transistor is performed in the second mode;
An electronic circuit characterized by A plurality of scan lines;
Multiple data lines,
A plurality of unit circuits, and
Each of the plurality of unit circuits is
An electro-optic element;
A first transistor that conducts when one of the plurality of scan lines is selected;
A second transistor;
In a first mode in which the luminance of the electro-optic element is set by first data, the electro-optic element is set to either a lighting state or a non-lighting state,
In a second mode in which the luminance of the electro-optic element is set by second data, the luminance of the electro-optic element corresponds to the conduction state of the second transistor set by the second data. Being
An electro-optical device. The electro-optical device according to claim 8.
The first data and the second data are digital data and analog data, respectively;
An electro-optical device. The electro-optical device according to claim 8 or 9,
The plurality of data lines include a plurality of first data lines and a plurality of second data lines,
The first data is supplied to the plurality of unit circuits via the plurality of first data lines,
The second data is supplied to the plurality of unit circuits via the plurality of second data lines;
An electro-optical device. The electro-optical device according to claim 8,
Each of the plurality of unit circuits further includes a capacitive element,
The capacitive element holds the first data as a charge in the first mode, and holds the second data as a charge in the second mode;
An electro-optical device. The electro-optical device according to claim 8,
Each of the plurality of unit circuits further includes a fourth transistor disposed between a gate and a drain of the second transistor;
An electro-optical device. The electro-optical device according to any one of claims 8 to 12,
The electro-optic element is an EL element;
An electro-optical device. The electro-optical device according to claim 8,
A threshold voltage of the second transistor is performed in the second mode;
An electro-optical device. The electro-optical device according to any one of claims 8 to 14,
The number of gradations in the first mode is less than the number of gradations in the second mode;
An electro-optical device. An electronic apparatus comprising the electro-optical device according to claim 8. The electronic device according to claim 16, wherein
The electro-optical device is a display unit of the electronic device,
When giving priority to the display quality of the display unit, the second mode is used,
The first mode is used when priority is given to low power consumption of the display unit;
Electronic equipment characterized by

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