JP2006013908A - Digital camera and its control method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve starting while securing the reliability of a system of a digital camera. <P>SOLUTION: This digital camera for photographing an object and outputting image data has a system memory (18) for storing software necessary for the operation of the digital camera and storing data showing its initialized result, a power-on reset signal generation circuit (25) for providing information about the reliability of the data and an entire control CPU (8) for controlling the digital camera on the basis of the software and the data. The entire control CPU determines the reliability of the data on the basis of information from the power-on reset signal generation circuit at the time of starting, performs software initialization operation without using the data and performs hardware initialization operation to operate the digital camera when the reliability is low, and at least partially ignoring software initialization operation by using the data and performs hardware initialization operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a digital camera such as a digital still camera and a digital video camera and a control method thereof, and in particular, an MRAM or FRAM as a memory for storing an operating system (OS), a user program, data for executing the program, and the like. The present invention relates to a digital camera using a non-volatile memory that can be accessed at high speed as a system memory.

  A nonvolatile memory called a FLASH memory is used as a system memory of a digital camera that has been generally used. FIG. 21 shows an example of the configuration of a conventional digital camera using a FLASH memory. The interior is broadly divided into a camera control system for controlling camera blocks and a digital control system for managing image processing and connection with PC peripheral devices.

  In FIG. 21, a subject image incident through the image pickup optical system 3 and the shutter 2 is formed by the image pickup device 1 and output as a predetermined electric signal. The imaging optical system 3 is disposed so as to guide appropriate light to the imaging element 1 via a lens driving unit 10 for performing a predetermined zoom operation and focus operation according to an instruction from the camera control CPU 9.

  On the other hand, the shutter 2 is similarly driven and controlled via the shutter drive unit 11 in accordance with an instruction from the camera control CPU 9, and is configured to control the actual exposure to the image sensor 1.

  The image sensor 1 is based on a timing control signal (horizontal drive pulse and vertical drive pulse) from a timing generator (TG) 6 that operates based on a signal from a synchronization signal generator (SSG) 7 that outputs a constant synchronization signal. The image signal output is input to an AFE 4 (Analog Front End Processor), where an appropriate sampling operation and A / D conversion operation are performed to convert it into a digital signal, and then to a digital signal processing unit (DSP) 5. It is configured to input.

  The DSP 5 receives the digital signal from the AFE 4 and performs image processing for actually creating a picture on the image data, and performs image compression such as so-called JPEG compression on the image processing result. Assuming that the image processing cannot actually catch up with the input speed of the captured image data, the image data is temporarily captured and stored in the externally connected buffer memory 14. Memory control means is also built in.

  Therefore, in a normal operation, image data once taken is stored in the buffer memory 14, then the image data is read from the buffer memory 14, subjected to predetermined image processing, and then subjected to JPEG compression, and the result is again stored in the buffer memory 14. The operation of writing back is performed.

  The final image data stored in the buffer memory 14 is read by the overall control CPU 8 and stored in the card memory 16 via the card controller 15 while adding predetermined file information. The card controller 15 is for managing physical and logical control corresponding to card memories of various standards (for example, compact flash (registered trademark) card, SD card, etc.). Via the DSP 5 and the overall control CPU 8.

  The DSP 5 has a video control function for displaying a photographed image or the like on the TFT monitor 13 via the TFT controller 12, and a part of the image stored in the buffer memory 14 or the card memory 16 or a reduced image is obtained. Display using this video control function.

  The overall control CPU 8 is for controlling the overall digital signal processing. The CPU 8 executes operations based on the OS and user programs stored in the system memory 30 (FLASH memory) and ROM 26 (FLASH memory and mask ROM). To do.

  Further, the PC connection controller 17 arranged on the system bus exchanges data according to a predetermined protocol in order to establish a connection with the external PC 19, and transfers data in the buffer memory 14 and the card memory 16. Transfer control to the external PC 19 is performed via the PC connection controller 17.

  In this way, the camera control CPU 9 that controls the camera unit and the overall control CPU 8 that mainly controls the digital unit such as image processing and PC peripheral devices exchange timing and information with each other via predetermined communication means, and shoot the camera. It operates to perform appropriate processing according to the sequence operation.

  Further, in this system, there is a main power supply 20 for supplying power to the entire system and a backup power supply 21 for backup when there is no main power supply, and real-time through a backflow prevention circuit using a diode 22 and a diode 23. Power is supplied to the clock generation circuit 24.

  In this case, even when the main power supply 20 is not provided, the power supply to the real-time clock generation circuit 24 is always supplied from the backup power supply 21, and therefore it is possible to always grasp the time information at that time.

  On the other hand, the signal of the power-on reset signal generation circuit 25 that outputs a signal only when the main power supply 20 is turned on is input to both the camera control CPU 9 and the overall control CPU 8, and grasps the turn-on state of the main power supply 20. can do.

  As described above, in the start-up control operation of a digital camera using a FLASH memory as the system memory 30, the OS and user program stored in the FLASH memory are started up every time the camera is turned on. Initialization data in the execution process of the OS and the user program is set every time in a volatile memory such as an SRAM existing in the CPU or an SDRAM existing outside.

  In the start control operation of this camera, the internal module of the OS itself (which may be normally compressed) is first decompressed, initial parameters are set, and each resource is initialized. Initialization of each resource is performed by setting initial parameters for various middleware used in a user program that operates under the management of the OS.

  Further, following the above-described operation, an initialization operation regarding a so-called device driver for controlling hardware inside the CPU and peripheral devices connected to the outside of the CPU is performed.

JP 2003-189165 A

  However, in the case of the FLASH memory used in the above conventional example, the access speed is very slow, and when the program is directly executed from the FLASH memory, the operation speed of the CPU does not increase as expected. There is a point.

  A simple solution to this problem is to first transfer all instructions to be executed by the CPU, such as the OS and user program stored in the FLASH memory during camera motion control, from the FLASH memory to the SDRAM, and after the transfer is complete. A method in which the data on the SDRAM is executed by the CPU is generally used. In this case, the time for copying all the data from the FLASH memory to the SDRAM is from several hundreds msec to nearly one second. The time lag from the start of actual startup to the start of program execution becomes very long.

  Furthermore, after this operation, initialization of software components such as initialization of internal modules of the OS itself and initialization of user program middleware, etc., followed by device drivers for driving and controlling CPU internal circuits and peripheral devices, etc. Since the initialization operation of the hardware parts is also performed, the time is also several hundred mSEC.

  In the above case, if the result of the initialization operation of the OS or user program is written in the FLASH memory in advance, a part of this initialization operation can be omitted at the start of the next operation. Depending on the data, the value to be written may change each time, and in this case, the frequency of rewriting to a specific FLASH memory increases, so rewriting to the FLASH memory is performed for the number of times the power ON / OFF is assumed. Then, the reliability of the memory itself may be lost.

  First of all, as a method for solving the above problems, a nonvolatile memory such as MRAM (Magnetoresistive Random Access Memory) or FRAM (Ferroelectric Random Access Memory) having a higher access speed than the FLASH memory can be used instead of the FLASH memory. This is the method to use.

The memory such as MRAM and FRAM can use a new material such as a magnetic material or a dielectric material for the gate portion of the transistor, thereby enabling an access speed of the same level as that of SRAM or SDRAM, and the number of rewrites is 10 ¹⁰ times or more. It is said that it will be possible to achieve almost unlimited numbers such as 10 ¹⁵ times.

  However, since it is still necessary to improve the yield in the current process, a size that can replace all the memories (for example, buffer memory at the time of shooting) has not been put into practical use. It has only been realized for use in certain limited applications.

  In addition, the long-term storage reliability of MRAM and FRAM is not necessarily sufficient at present (for example, when left in a harsh environment for many years), or when an accident due to a system malfunction or the like is assumed (for example, data If the battery is removed at the time of rewriting), when the system is started up with the data initialized in the previous operation, the data itself is likely to be indefinite. There is a problem that it may stop working.

  The present invention has been made in view of the above problems, and an object thereof is to improve the startability while ensuring the reliability of a digital camera system.

  In order to achieve the above object, the digital camera of the present invention for photographing a subject and outputting image data stores software necessary for the operation of the digital camera and data indicating an initialization result of the software. Non-volatile memory means, information providing means for providing information on the reliability of the data, control means for controlling the digital camera based on the software and the data, and the digital When the camera is activated, the control means determines the reliability of the data based on information from the information providing means, and when the reliability is low, the data stored in the nonvolatile memory means is used. Execute the first mode that performs the software initialization operation and the hardware initialization operation for operating the digital camera. If the reliability is high, the second mode in which at least a part of the software initialization operation is omitted and the hardware initialization operation is performed by using the data stored in the nonvolatile memory means. Execute.

  In addition, non-volatile memory means for storing software necessary for the operation of the digital camera and data indicating an initialization result of the software, the digital camera based on the software and the data Control method of the present invention for a digital camera that captures a subject and outputs image data, an information providing step for providing information on the reliability of the data, and activation of the digital camera Sometimes, a determination step for determining the reliability of the data based on information from the information providing step, and if the determination step determines that the reliability is low, the initial software is used without using the data. And executing a first mode for performing an initialization operation and a hardware initialization operation for operating the digital camera. If it is determined that the reliability is high, the initialization step of executing the second mode in which at least a part of the software initialization operation is omitted using the data and the hardware initialization operation is performed. And have.

  According to the above configuration, the startability can be improved while ensuring the reliability of the system of the digital camera.

  The best mode for carrying out the present invention will be described below in detail with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing the overall configuration of a digital camera according to the first embodiment of the present invention. The configuration of the first embodiment shown in FIG. 1 is different from that of FIG. 21 in that a FLASH memory is used as the system memory but an MRAM or FRAM is used.

  Therefore, the overall control CPU 8 in the first embodiment is for controlling the entire digital signal processing, and this CPU 8 is stored in the system memory 18 (MRAM and FRAM) and the ROM 26 (FLASH memory and mask ROM). The operation is executed based on the OS and the user program.

  In the system shown in FIG. 1, the camera control CPU 9 and the overall control CPU 8 are mainly composed of two control blocks. However, the program size of the camera control CPU 9 is usually a capacity of several hundred kilobytes at most. In this case, the operation is performed by a built-in ROM (mask ROM or FLASH memory). On the other hand, since the program size of the overall control CPU 8 that controls the digital unit is several Mbytes when the OS is included, it is not practical to operate with the built-in ROM, as in the first embodiment. It is a practical method to connect an MRAM (or FRAM) as the ROM 26 such as a FLASH memory or the system memory 18 to the outside.

  FIG. 2 is a block diagram showing the internal configuration of the overall control CPU 8. Among these, the CPU core 50 that outputs control signals to the actual arithmetic processing and each peripheral circuit, and access to an external memory are avoided as much as possible. A cache 51 for operating the CPU core 50 at a high speed, and a memory controller 52 connected to the cache 51 and for controlling the timing and access of peripheral devices such as external memory devices and I / O devices are provided. The buffer controller 14, the card controller 15, the PC connection controller 17, the system memory 18, and the ROM 26 described in FIG. 1 are connected to the memory controller 52.

  The interrupt controller 53 has a function of selecting interrupt signals from internal and external devices and transmitting necessary signals to the CPU core 50. Internal signals include signals from the communication I / F 54 and timer 55. External signals include the DSP 5, the request signal from the camera control CPU 9, the signal from the TFT controller 12, the signal from the card controller 15, and the PC connection controller. A signal from 17 is input, and interrupt control is executed according to a predetermined priority and a predetermined mask function (interrupt disable function).

  The communication I / F 54 is mainly an I / F block for exchanging information and timing with the camera control CPU 9, an I / F block for setting data for the TG 6, and for setting data for the AFE 4. The I / F block includes an I / F block for setting data for the TFT controller 12.

  The timer 55 internally has six timers, timers A to F, each of which is a resource for which role a function is to be given in the initialization operation at the time of initial activation control. After assigning, operations are performed at any time.

  The above is the hardware configuration of the digital camera according to the first embodiment. The system memory 18 uses a nonvolatile memory such as MRAM or FRAM that can be accessed at high speed.

  Next, the initial operation of the overall control CPU 8 in FIG. 1 will be described with reference to FIGS.

  In FIG. 3, first, in step S100, the state of the power-on reset signal generated when the battery as the main power source 20 shown in FIG. 1 is replaced is detected from the output of the power-on reset signal generation circuit 25, and the power-on reset signal is detected. If NO is detected, the process directly proceeds to step S107 as a normal startup operation. However, if a power-on reset signal is detected, it is determined that the operation is the first operation after battery replacement, and an initialization operation for software after step S101 is performed. Execute.

  In step S101, an initialization operation for an interrupt resource in the CPU 8 is started. This operation will now be described with reference to the flowchart of the interrupt initialization sequence shown in FIG.

  First, in step S130, as an operation related to the interrupt controller 53 of FIG. 2, the resource allocation is performed so that the resources related to the internal interrupt 1 are directed to the signal from the DSP 5. Similarly, in step S131, the resources are arranged so that the resources related to the internal interrupt 2 are directed to the signal from the camera control CPU 9. Subsequently, in step S132, the resources related to the internal interrupt 3 are assigned from the timer 55 in the CPU. In step S133, resource allocation is performed so that the resources related to the internal interrupt 4 are allocated to the signal from the communication I / F in the CPU. In step S134, internal resource allocation is performed. The resource allocation is performed so that the resource related to the interrupt 5 is directed to the signal from the TFT controller 12, and in step S135, the resource allocation is performed so that the resource related to the internal interrupt 6 is allocated to the signal from the card controller 15, In step S136, an internal interrupt 7 The related resources performing resource allocation to divert the signals from the PC connection controller 17.

  As described above, for each interrupt resource, operation settings for securing resources are performed in the initialization sequence for each external device externally connected to the peripheral circuit in the CPU 8.

  In step S102, an initialization operation for the timer resource in the CPU is started. This operation will be described with reference to the flowchart of the timer resource initialization sequence shown in FIG.

  First, in step S150, the timer A of the timer 55 of FIG. 2 is allocated for overall management, that is, for setting the time for monitoring abnormal operations in the CPU 8, etc. Next, in step S151, the timer B is communicated. Resource allocation is performed as time setting means for management, that is, for communication monitoring of the communication I / F 54 inside the CPU 8, and in step S152, resource allocation is performed for timer C for time management of shooting control of the DSP 5, and in step S153 timer D Is allocated for managing the development time of the DSP 5, the timer E is allocated for managing the access time of the card controller 15 in step S 154, and the timer F is used for managing the connection time of the PC connection controller 17 in step S 155. Resource allocation as

  As described above, resource initialization is performed so that each of the six timers A to F in the timer 55 has a role for managing each peripheral device.

  In step S103, initialization of the communication manager using the communication I / F 54 in the CPU 8 is started. This operation will be described with reference to the flowchart of the communication manager initialization sequence shown in FIG.

  The communication manager is a control module for exchanging information with other devices when each communication I / F block is used. First, in step S170, the internal serial I / F block A is exchanged with the camera control CPU 9. Resource allocation is performed so as to operate as a camera serial communication module that performs communication. Subsequently, in step S171, resource allocation is performed so that the internal serial I / F block B operates as a serial communication module for internal setting of the TG 6, and step S172. In step S173, resources are arranged so that the internal serial communication I / F block C operates as a serial communication module for internal setting of the AFE 4. In step S173, the serial communication module for internal setting of the TFT controller 12 is set as the internal serial communication I / F block D. As motion Performs resource arranged to.

  As described above, each communication module in the overall control CPU 8 is initialized so that the internal block of the communication I / F 54 is used for communication with each peripheral device outside the CPU.

  In step S104, initialization of the memory manager using the memory controller 52 in the CPU 8 is started. This operation will be described with reference to the flowchart of the memory manager initialization sequence shown in FIG.

  This memory manager is mainly for controlling the use of the memory of the buffer memory 14 and the system memory 18. First, in step S190, initialization as a resource when using the cache 51 in the CPU 8 is performed, and what cache control is to be performed for which module is set. Subsequently, in step S191, the captured image is buffered. A resource arrangement relating to memory management in the case of temporarily storing in the memory 14 is performed. In step S192, a resource arrangement relating to the use of the buffer memory 14 in the case of developing a photographed image is performed. In step S193, the developing process is performed. When the completed image data is stored as a file in the card memory 16 or when the image file stored in the card memory 16 is read and expanded in the buffer memory 14, resource allocation is performed for memory management. In step S194, the captured image is displayed. TFT monitor 1 Regarding use as a VRAM in the case of displaying the performs resource allocation with respect to memory management of the buffer memory 14.

  As described above, the memory manager initialization operation for determining the memory management method is performed with respect to the usage of the buffer memory 14 and the system memory 18.

  In step S105, an initialization operation of a file manager for managing files inside the CPU 8 is performed. This method will be described with reference to the flowchart of the file manager initialization sequence shown in FIG.

  The file manager is related to all resources for managing the image and setting data stored in the buffer memory 14 and the system memory 18 as file information. First, in step S210, the file manager initializes the file system. In step S211, a file I / O initialization operation that actually serves as an entry / exit for file control is performed. Next, in step S212, a special thumbnail image or the like that actually displays a captured image on the TFT monitor 13 is displayed. Performs resource initialization when managing as file information.

  As described above, in order to actually control various data including image data as a series of files, various resources for controlling the file manager are initialized.

  In step S106, an initialization operation of a display manager that performs display management in the CPU 8 is performed. This method will be described with reference to the flowchart of the display manager initialization sequence shown in FIG.

  The display manager actually controls the display of the GUI and the photographed image using the TFT monitor 13, and first initializes various resources for controlling the GUI in step S230, and then in step S231 using the GUI. Various font information to be used is developed into a form that can be actually displayed on the monitor. In step S232, initialization for controlling various resources for controlling various windows on the TFT monitor 13 is performed. In step S233, the font is displayed. Perform bitmap development for display systems other than information.

  As described above, in the first power-on reset operation after the main power supply replacement, the internal operation of the CPU 8 is executed in steps S101 to S106, and the resource allocation and initial setting of each module for use in the middleware on the OS or user program are executed. The operation sequence is executed.

  Up to this point, the software component initialization operation has been completed. After completion, in step S107 and subsequent steps in FIG. 3, the circuit inside the CPU 8 executed by the normal camera activation operation and a device driver for driving and controlling peripheral devices are used. Starts hardware component initialization.

  In step S107, the CPU core 50 reads the initial setting information of the CPU 8 internal and external peripheral devices stored in the system memory 18, and starts the initialization operation of each device based on the information.

  FIG. 10 shows the internal map information of the system memory 18. From the top, the OS area, user program area, resource setting data area such as middleware used in the OS and user program, CPU 8 internal and external peripheral hardware Each individual adjustment data area as initialization data used in the driver portion of the wear and a common fixed data area.

  As an initialization operation of the device driver, first, an internal initialization operation of the DSP 5 is performed in step S108. This operation will be described with reference to the flowchart of the DSP initialization operation sequence shown in FIG.

  In FIG. 11, first, in step S300, an initialization operation is performed on a timing control block for actually capturing image data from the image sensor 1 in synchronization with a connection signal to the SSG 7, and then in step S301, the buffer memory 14 is initialized. In the case where the memory controller part for memory control for storing or reading out and developing the actual captured image is initialized, and the data from the image sensor 1 is actually captured in step S302 In step S303, various parameters are initially set when executing so-called development processing in which actual image processing is performed on the captured image data. In step S304, the captured image is captured. TFT controller 12 and TFT monitor Performing an initialization operation of the video controller portion that performs memory control in the case of actually displayed through 13.

  Next, in step S109, the hardware initial setting operation of the internal serial I / F blocks A to D in the communication I / F 54 of FIG. 2 is performed. The serial communication unit initialization sequence shown in FIG. This will be described with reference to the flowchart of FIG.

  First, regarding the internal serial I / F block A, resources are already allocated for serial communication with the camera control CPU. In step S320, the internal camera communication transmission buffer is cleared, and then in step S321 the camera is cleared. Clear the communication receive buffer.

  Next, in step S322, the communication rate for camera communication is set, and after waiting in step S323 until the READY signal from the camera control CPU 9 is detected, the camera communication interrupt flag is cleared in step S324. In step S325, serial communication interrupt permission is given. Subsequently, in step S326, the TG communication transmission buffer is cleared for the internal serial I / F block B to which resources are allocated for operation setting in the TG 6, and then in step S327, the communication rate is set for TG communication. Set. In step S328, the AFE communication transmission buffer is cleared for the internal serial I / F block C to which resources are assigned for setting the operation in the AFE4. Next, in step S329, the communication rate is set for AFE communication. To do. In step S330, the TFT controller communication transmission buffer is cleared for the internal serial I / F block D to which resources are assigned for operation setting in the TFT controller 12, and in step S331, communication is performed for TFT controller communication. Set the rate.

  In the flowchart of FIG. 3 again, an initialization operation of the photographing control system is performed in step S110. This operation will be described with reference to the flowchart of FIG.

  First, an initial value is set for the internal setting register of TG6. In step S340, an initial value is set for the transmission buffer for TG communication. In step S341, this data is set for TG6. TG communication is started. In step S342, it is determined whether or not the TG communication has been completed. When it is detected that the communication has been completed, it is determined in step S343 whether or not the communication of all data has been completed. Is not completed, the process returns to step S340 again, and all data communication is performed by repeating the above operation. When it is detected in step S343 that communication of all data has been completed, the process proceeds to step S344, where an initial value is set for the AFE communication transmission buffer in order to perform communication with the AFE 4.

  After actually starting communication in step S345 and determining whether or not communication to this AFE 4 is completed in step S346, when it is detected that communication has been completed, communication of all data is now performed in step S347. It is determined whether or not the communication has been completed. If communication of all data has not been completed, the process returns to step S344, and all the data communication is performed by repeating the above operation. When it is detected in step S347 that communication of all data has been completed, the initialization operation for all imaging control systems is completed.

  In FIG. 3 again, in step S111, the card controller 15 is initialized. This operation will be described with reference to the flowchart of FIG.

  First, in step S360, initial values are set for the internal registers of the card controller 15. Subsequently, in step S361, it is determined whether or not all data has been set, and when all data has been set, the process proceeds to step S362. Then, the internal initialization of the card controller 15 is started. In step S363, it is determined whether internal initialization is completed, and the above operation is completed when an internal initialization completion signal is detected.

  Returning to the flow of FIG. 3 again, this time, the initialization operation of the PC connection controller 17 is started in step S112. This operation will be described with reference to the flowchart of FIG.

  First, in step S380, initial values are set in the internal registers of the PC connection controller 17, and then in step S381, it is determined whether or not all data has been set. When all data has been set, step S382 is executed. The internal initialization of the PC connection controller 17 is started here. In step S383, it is determined whether internal initialization is completed, and the above operation is completed when an internal initialization completion signal is detected.

  Returning to the flow of FIG. 3 again, this time, the initialization operation of the TFT controller 12 is started in step S113. This operation will be described with reference to the flowchart of FIG.

  First, in step S400, an initial value is set in the communication transmission buffer of the TFT controller 12, and then communication with the TFT controller 12 is started in step S401. In step S402, it is determined whether or not communication with the TFT controller 12 has been completed, and when communication completion is detected, the process proceeds to step S403, where it is determined whether or not communication of all data has been completed. If communication of all data has not yet been completed, the process returns to step S400 and the above operation is repeated, but this operation is completed when communication of all data is completed.

  The above is the initialization operation of the device driver for controlling the hardware of the internal circuit of the overall control CPU 8 and external peripheral circuits.

  After each initialization operation of the device driver is completed, first, in step S114, the camera control CPU 9 determines whether or not the preparatory operation for photographing is completed, and the photographing preparatory operation is completed here. Is detected, the process proceeds to step S115 to determine whether or not the card memory 16 is actually installed via the card controller 15. If the card memory 16 is actually mounted, information such as an actual directory is searched via the FAT information of the card in step S116, the state of each file is detected, and the process proceeds to step S117. If the card memory 16 is not loaded in step S115, the process proceeds directly to step S117.

  In step S117, it is detected whether the PC 19 is actually connected via the PC connection controller 17. If the PC 19 is not connected, the process proceeds directly to step S119, but if it is detected that the PC 19 is connected, actual login processing is started in step S118.

  This log-in process determines a predetermined procedure in advance when the PC 19 and the camera body transmit / receive images through actual communication, or when the camera 19 remotely controls functions inside the camera. After logging in, the camera and the PC remain connected until the final logoff is performed.

  When this predetermined login process is completed, it is determined in step S119 whether or not all conditions for starting actual image capture, that is, shooting operation, are satisfied. Start shooting operation.

  As described above, in the first embodiment, when the photographer starts the actual photographing by operating the release button of the camera or the like, it is the first operation after the battery as the main power source is turned on. , By generating a power-on reset signal internally, the internal resources already set in the system memory configured with MRAM and FRAM are not used, but the OS or user actually stored in the ROM An initialization operation is performed on software such as middleware of the program, and the result is newly set in the system memory.

  In addition, after completing the initialization operation of this software, the device data is initialized by using this resource data to control the actual CPU internal circuit and external peripheral circuit hardware. The operation is performed every time the power is turned on as described above.

  As described above, according to the first embodiment, the OS and the user program for executing the operation of the CPU, the resource data performed in the initialization operation of the OS and the user program, and the CPU By storing at least a part or all of data for adjusting operation variations of internal circuits and peripheral devices connected to the outside in an MRAM or FRAM that is a nonvolatile memory used as a system memory, This eliminates the need to perform all initialization operations every time during start-up control of the camera, and eliminates the time loss required for the initialization operation at start-up, which was previously required. Can be improved.

  Also, initialization data when executing a series of programs, including data that is frequently rewritten systemically if it is the first operation after the camera battery is replaced and the camera battery is replaced With regard to the reliability of the system itself, the reliability of the system itself is questionable, and even if the MRAM or FRAM is used by performing all of the conventional startup control operations, the reliability of the system Sex can be secured.

<Second Embodiment>
A second embodiment of the present invention will be described.

  Since the power is supplied from the backup power supply 21 even when the main power supply 20 is turned off, the real-time clock generation circuit 24 in FIG. 1 can measure the time during which the main power supply 20 is turned off. Therefore, in the second embodiment, when the main power supply 20 is turned off for a long period, all of the conventional startup control operations are performed. When the period is short, it is used as the system memory 18. By using data stored in the MRAM or FRAM, a part of the initialization operation at the time of normal camera activation is not performed.

  FIG. 17 is a flowchart showing an initial operation of the overall control CPU 8 in the second embodiment. First, in step S500, the period Toff in which the main power source 20 is turned off is compared with a predetermined time Tth set in advance. If Toff is longer than the predetermined time Tth, the reliability of the data in the system memory 18 may be low. Therefore, the software resource initialization operation in steps S101 to S106 is performed, and then the process proceeds to step S107. If it is short, the process directly proceeds to step S107 without performing the processes in steps S101 to S106. Perform initialization. Note that the processing in steps S101 to S120 is the same as the processing described with reference to FIGS. 3 to 9 and FIGS. 11 to 16 in the first embodiment, and thus description thereof is omitted here. The predetermined time Tth is empirically set to a time shorter than the storage reliability of the MRAM or FRAM is lowered.

  As described above, in the second embodiment, when the photographer turns on the power of the camera, at least the initialization operation is performed using the internal resources already set in the system memory configured by the MRAM and the FRAM. If some parts are omitted and the main power is turned off for a long time, the internal resources already set in the system memory are not used, and the OS and user programs stored in the ROM are not used. By performing an initialization operation for software such as middleware and setting the result in a new system memory, the startability can be improved while ensuring the reliability of the system of the digital camera.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.

  FIG. 18 is a block diagram showing the overall configuration of the digital camera according to the third embodiment, and shows an example in which a system bus abnormality detection circuit 34 is installed instead of the real-time clock generation circuit 24 of FIG. is there.

  As shown in FIG. 19, the system bus abnormality detection circuit 34 includes a system bus monitor 550 that periodically monitors the state of the system bus, a timer 551 that measures time at a predetermined time interval, and when there is an abnormality in the system bus, An abnormal state storage circuit 552 for storing the state in an internal register, and a low voltage detection circuit 553 for detecting that the main power source is switched to the backup power source.

  Here, for example, when the main power supply 20 is turned off during access to the system memory 18, an abnormal operation has occurred during access to the system memory 18, so that data in the system memory 18 itself is destroyed. There is a possibility.

  Therefore, when the system bus monitor 550 detects the access state to the system memory 18, the timer 551 measures a predetermined time, and further, the system is based on the result when the low voltage detection circuit 553 detects the voltage drop. The abnormal state is stored in the abnormal state storage circuit 552.

  Next, when the main power supply 20 is turned on, as shown in the flowchart of FIG. 20, an abnormal state of the system is detected in step S600, and a signal that the system bus abnormality detection circuit 34 is abnormal is output. In this case, since the data stored in the system memory 18 is likely to be destroyed, the software resource initialization operation in steps S101 to S106 is performed, and then the process proceeds to step S107. If not output, the process proceeds directly to step S107 without performing the processes of steps S101 to S106, and the initialization operation of the hardware device driver is performed. Note that the processing in steps S101 to S120 is the same as the processing described with reference to FIGS. 3 to 9 and FIGS. 11 to 16 in the first embodiment, and thus description thereof is omitted here.

  As described above, in the third embodiment, when the photographer turns on the power of the camera, at least the initialization operation is performed using the internal resources already set in the system memory configured by the MRAM and the FRAM. If a part is omitted and the system is terminated in an abnormal state during the previous operation, the internal resources already set in the system memory are not used and the OS and user programs stored in the ROM are not used. By performing an initialization operation for software such as middleware and setting the result in a new system memory, the startability can be improved while ensuring the reliability of the system of the digital camera.

  In addition to the above-described method for determining the reliability of the data indicating the initialization result stored in the system memory 18 such as MRAM or FRAM, for example, the software initialization result is completely stored in the system memory at a plurality of locations. There is a method of storing the same value. In this case, when the main power is turned on, it is determined whether or not the data stored in the plurality of locations match. If they match, it is determined that the data is reliable, and if they are different, the data reliability is determined to be suspicious. .

  In addition, the checksum of the initialization data (simply add the initialized data numerically one by one and store the result in another area) is calculated again when the power is turned on. In this case, the reliability of the initialization data may be determined to be suspicious if they are different.

<Other embodiments>
An object of the present invention is to supply a storage medium (or recording medium) in which a program code of software for realizing the functions of the above-described embodiments is recorded to a system or apparatus, and a computer (or CPU or MPU) of the system or apparatus. Needless to say, this can also be achieved by reading and executing the program code stored in the storage medium. In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention. Further, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also an operating system (OS) running on the computer based on the instruction of the program code. It goes without saying that a case where the function of the above-described embodiment is realized by performing part or all of the actual processing and the processing is included. Examples of the storage medium for storing the program code include a flexible disk, hard disk, ROM, RAM, magnetic tape, nonvolatile memory card, CD-ROM, CD-R, DVD, optical disk, magneto-optical disk, MO, and the like. Can be considered. Also, a computer network such as a LAN (Local Area Network) or a WAN (Wide Area Network) can be used to supply the program code.

  Furthermore, after the program code read from the storage medium is written into a memory provided in a function expansion card inserted into the computer or a function expansion unit connected to the computer, the function is based on the instruction of the program code. It goes without saying that the CPU or the like provided in the expansion card or the function expansion unit performs part or all of the actual processing and the functions of the above-described embodiments are realized by the processing.

1 is a block diagram illustrating an overall configuration of a digital camera according to a first embodiment of the present invention. FIG. 2 is a block diagram showing an internal configuration of an overall control CPU shown in FIG. 1. It is a flowchart which shows the flow of the whole initial operation | movement of the whole control CPU in the 1st Embodiment of this invention. It is a flowchart which shows the initialization sequence of an interrupt resource. It is a flowchart which shows the initialization sequence of a timer resource. It is a flowchart which shows the initialization sequence of a communication manager. It is a flowchart which shows the initialization sequence of a memory manager. It is a flowchart which shows the initialization sequence of a file manager. It is a flowchart which shows the initialization sequence of a display manager. It is a memory map block diagram of system memory. It is a flowchart which shows the initialization sequence of DSP. It is a flowchart which shows the initialization sequence of a serial communication part. It is a flowchart which shows the initialization sequence of an imaging | photography control system. It is a flowchart which shows the initialization sequence of a card controller part. It is a flowchart which shows the initialization sequence of a PC connection controller part. It is a flowchart which shows the initialization sequence of a TFT controller part. It is a flowchart which shows the flow of the whole initial operation | movement of the whole control CPU in the 2nd Embodiment of this invention. It is a block diagram which shows the whole structure of the digital camera in the 3rd Embodiment of this invention. FIG. 19 is a block diagram showing an internal configuration of a system bus abnormality detection circuit shown in FIG. 18. It is a flowchart which shows the flow of the whole initial operation | movement of the whole control CPU in the 3rd Embodiment of this invention. It is a block diagram which shows the whole structure of the conventional digital camera.

Explanation of symbols

1 Imaging device 2 Shutter 3 Imaging optical system 4 AFE
5 Digital Signal Processing Unit 6 Timing Generator 7 Synchronization Signal Generation Unit 8 Overall Control CPU
9 Camera control CPU
DESCRIPTION OF SYMBOLS 10 Lens drive part 11 Shutter drive part 12 TFT controller 13 TFT monitor 14 Buffer memory 15 Card controller 16 Card memory 17 PC connection controller 18 System memory (MRAM, FRAM)
19 PC
20 Main power supply 21 Backup power supply 22, 23 Diode 24 Real-time clock generation circuit 25 Power-on reset signal generation circuit 26 ROM

Claims (16)

A digital camera that shoots a subject and outputs image data,
Non-volatile memory means for storing software necessary for the operation of the digital camera and storing data indicating an initialization result of the software;
Information providing means for providing information on the reliability of the data;
Control means for controlling the digital camera based on the software and the data;
When the digital camera is activated, the control means determines the reliability of the data based on information from the information providing means, and if the reliability is low, the control means stores the data stored in the nonvolatile memory means. The first mode for performing the initialization operation of the software and the initialization operation of the hardware for operating the digital camera without using them is executed, and when the reliability is high, it is stored in the nonvolatile memory means. A digital camera characterized in that by using the data, at least a part of the software initialization operation is omitted and the second mode in which the hardware initialization operation is performed is executed.   The information providing means provides the information when a battery used as a power source of the digital camera is replaced between a time when the power of the digital camera is turned off and a time when the power is turned on next. 2. The digital device according to claim 1, wherein the control unit executes the first mode when the battery is replaced, and executes the second mode when the battery is not replaced. 3. camera.   The information providing means is a time measuring means for measuring a time during which the power of the digital camera is turned off, and the control means is configured such that the time measured by the time measuring means is longer than a predetermined time. The digital camera according to claim 1, wherein the first mode is executed, and the second mode is executed when the mode is short.   The information providing unit is an abnormal state detecting unit that detects an abnormal state and stores the information, and the control unit is configured to perform the first mode when the information is provided from the abnormal state detecting unit. 2. The digital camera according to claim 1, wherein the second mode is executed if not provided.   The nonvolatile memory means stores data indicating an initialization result in a plurality of locations, the information providing means compares the data stored in the plurality of locations, and outputs information indicating whether or not they match. 2. The digital camera according to claim 1, wherein the control unit executes the first mode when the data do not match, and executes the second mode when the data matches.   The information providing means calculates a checksum of data indicating an initialization result and stores it in the nonvolatile memory means, calculates a checksum of the data when the digital camera is activated, and the control means The checksum calculated when the digital camera is activated is compared with the checksum stored in the non-volatile memory means, and if there is a mismatch, the first mode is executed. The digital camera according to claim 1, wherein the mode is executed.   7. The digital camera according to claim 1, wherein the nonvolatile memory means is MRAM or FRAM. Software necessary for the operation of the digital camera is stored, and data indicating an initialization result of the software is stored, and a non-volatile memory means, and the digital camera is controlled based on the software and the data And a control method of a digital camera that shoots a subject and outputs image data,
An information providing step for providing information on the reliability of the data;
A determination step of determining reliability of the data based on information from the information providing step when the digital camera is activated;
When it is determined that the reliability is low by the determination step, a first mode for performing an initialization operation of software and an initialization operation of hardware for operating the digital camera without using the data is set. And when the determination step determines that the reliability is high, a second mode in which at least a part of the software initialization operation is omitted using the data and the hardware initialization operation is performed. An initialization process for executing the control method.   In the information providing step, when the battery used as the power source of the digital camera is replaced between the time when the power of the digital camera is turned off and the time when the power is turned on next time, the information is provided. 9. The control method according to claim 8, wherein in the determination step, it is determined that the reliability is low when the battery is replaced, and the reliability is determined when the battery is not replaced.   In the information providing step, the time during which the digital camera is turned off is measured. In the determining step, if the measured time is longer than a predetermined time, it is determined that the reliability is low, and the time is short. The control method according to claim 8, wherein it is determined that the reliability is high.   In the information providing step, an abnormal state is detected and the information is stored. In the determining step, if the information is provided in the information providing step, it is determined that the reliability is low, and the information is not provided. The control method according to claim 8, wherein it is determined that the reliability is high. A step of storing data indicating an initialization result in a plurality of locations in the nonvolatile memory means;
The information providing step compares the data stored in the plurality of locations and outputs information indicating whether or not they match, and the determination step determines that the reliability is low when the data does not match. The control method according to claim 8, wherein if they match, it is determined that the reliability is high. Further comprising calculating a checksum of the data indicating the initialization result and storing it in the non-volatile memory means;
In the information providing step, a checksum of the data is calculated when the digital camera is activated, and in the determining step, a checksum calculated when the digital camera is activated and a checksum stored in the nonvolatile memory means The control method according to claim 8, wherein if it does not match, it is determined that the reliability is low, and if it matches, it is determined that the reliability is high.   14. The control method according to claim 8, wherein the nonvolatile memory means is MRAM or FRAM.   15. A program executable by an information processing apparatus, comprising program code for realizing the control method according to claim 8.   A storage medium readable by an information processing apparatus, wherein the program according to claim 15 is stored.

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