JP2006013773A - Image processor and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image processor capable of coping with various matrix sizes without the need for increasing the capacity of a memory in use and without decreasing an output gradation value, and to provide an image processing method. <P>SOLUTION: A structure comprising a pair of a "threshold value" and an "output gradation value corresponding to the threshold value" is adopted for a correction table in a multi-value dither system, and the address of the memory for storing the correction table and data adopting the configuration are controlled by the number of threshold values per pixel or the number of threshold values in each pixel on the matrix. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus and method for processing an image by changing a gradation value representing a change in shade of color of an image between an input image and an output image. The present invention relates to an image processing apparatus and method that can be configured to correspond to various matrix sizes without increasing the memory size and reducing the output gradation value by configuring with output gradation values set in advance corresponding to the above.

  In general, there is a multi-value dither method as a method for enhancing the reproducibility of the gradation value of the output image with respect to the gradation value of the input image when outputting the multi-value image data transmitted from the computer with a printing device or the like. In the dither method, gradation is expressed by arranging correction tables for correcting input gradation values to output gradation values in an m × n matrix.

  By expressing the gradation in the matrix unit by the multi-value dither method, the gradation that cannot be reproduced in the unit of one dot (pixel) can be expressed in the matrix unit. That is, continuous gradations can be reproduced with a small matrix size by using multiple gradations of about 3 to 16 gradations.

  Since the optimum matrix size of the correction table differs depending on the type and color of input image data, the multi-value dither circuit requires a large-capacity memory element to support a plurality of matrix sizes.

  A large-capacity memory device increases the circuit scale, makes mounting more difficult, increases costs, and cannot satisfy productivity.

In the prior art disclosed in Patent Document 1, when a dither matrix is used for gradation value conversion, a control signal, an address bus, and a data bus for a memory element used as a dither matrix table according to an output gradation value of output data By providing a control means, the memory element capacity required by the gradation conversion circuit corresponding to various output gradation values can be minimized, and the area of the dither matrix at low gradation values can be increased. It is possible to improve the quality of the output image in the gradation value.
JP2000-032264

  However, in the prior art disclosed in Patent Document 1, the correction table is a threshold value table corresponding to the gradation value of the image output apparatus, thereby reducing the memory capacity and changing the matrix size according to the image output apparatus. However, there are problems that the correction table that can be mounted is limited and that the matrix size cannot be increased unless the gradation value of the image output apparatus is reduced.

  Therefore, the present invention controls the storage address and data in the memory storing the correction table composed of the threshold value and the output gradation value corresponding to the threshold value by the threshold number per pixel or the threshold number of each pixel on the matrix. Accordingly, an object of the present invention is to provide an image processing apparatus and method which can cope with various matrix sizes without increasing the memory capacity and without reducing the output gradation value.

  In order to achieve the above object, an invention according to claim 1 is an image processing apparatus for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of the output image in a matrix unit of a predetermined size. A matrix counter that counts in the main scanning direction and the sub-scanning direction of the input image corresponding to the size of the matrix and outputs position information indicating the position of the pixel of the input image in the matrix; and the output Address generating means for generating a selection signal and an address for selecting the output gradation value based on the threshold number per pixel of the image and the position information output from the matrix counter, and the output gradation value of each address A pair of threshold values and output gradation values corresponding to the number of threshold values per pixel is stored, and the address generation unit specifies the address generated by the address generation unit. A correction table for reading the value and the output gradation value, a comparison means for comparing the threshold value read from the correction table with the input gradation value of the input image, and a threshold value per pixel of the output gradation value Output control means for selecting an output gradation value read from the correction table based on the number, the selection signal, and the output of the comparison means.

  According to a second aspect of the present invention, in the image processing apparatus for correcting the input gradation value of each pixel of the input image to the output gradation value of each pixel of the output image in a matrix unit of a predetermined size, the matrix size is adjusted. Correspondingly, a matrix counter that counts in the main scanning direction and sub-scanning direction of the input image and outputs position information indicating the position of the pixel of the input image in the matrix, and output from the matrix counter A basic address generation unit that outputs a threshold number per pixel of the output image on the matrix set in advance based on the position information and outputs a basic address, and a basic address output from the basic address generation unit Address generation means for generating an address based on the output gradation value threshold value and output gradation value for each address A correction table that stores a pair and reads the threshold value and the output gradation value by designating an address generated by the address generation means; and the threshold value and the output gradation value read from the correction table are the basic address Reordering means for reordering according to the basic address generated by the generating means; comparing means for comparing the threshold value reordered by the reordering means with an input gradation value of the input image; and the basic address generating means Output control means for selecting the output gradation values rearranged by the rearrangement means based on the threshold number output from the output and the output of the comparison means.

  According to a third aspect of the present invention, there is provided an image processing apparatus for performing image processing for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of the output image in a matrix unit of a predetermined size. In accordance with the size of the input image, counting is performed in the main scanning direction and the sub-scanning direction of the input image, and position information indicating the position of the pixel of the input image in the matrix is output by the matrix counter, and the output image Based on the threshold number per pixel and the position information output from the matrix counter, a selection signal and an address for selecting the output gradation value are generated by address generation means, and one pixel of the output gradation value is assigned to each address. A pair of threshold values and output gradation values corresponding to the number of threshold values per unit is stored, and the threshold value is specified by designating an address generated by the address generating unit. And the output gradation value is read from the correction table, the threshold value read from the correction table is compared with the input gradation value of the input image by the comparison means, and the number of threshold values per pixel of the output gradation value The output gradation value read from the correction table is selected based on the selection signal and the output of the comparison means.

  According to a fourth aspect of the present invention, there is provided an image processing method for performing image processing for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of the output image in a matrix unit of a predetermined size. Corresponding to the size of the input image and counting in the main scanning direction and sub-scanning direction of the input image, the position information indicating the position of the pixel of the input image in the matrix is output by the matrix counter, from the matrix counter The threshold value per pixel of the output image on the matrix set in advance based on the output position information is output, and the basic address is output by the basic address generating means, and is output from the basic address generating means An address is generated by the address generation means based on the basic address, and the output gradation value is assigned to each address. A pair of a value and an output gradation value is stored, the threshold value and the output gradation value are read out by a correction table by designating an address generated by the address generation unit, and the threshold value read from the correction table and the threshold value The output gradation value is rearranged by the rearrangement unit according to the basic address generated by the basic address generation unit, and the threshold value rearranged by the rearrangement unit and the input gradation value of the input image are compared by the comparison unit. The comparison is performed, and the output gradation value rearranged by the rearrangement unit is selected based on the threshold number output from the basic address generation unit and the output of the comparison unit.

  According to the present invention, the correction table arranged in a matrix in the multi-value dither method for calculating the output gradation value for the input gradation value of the input image data and outputting the image by using the output gradation value is provided. The threshold value and the output gradation value corresponding to the threshold value are set, and the storage address and data in the memory storing the correction table are controlled by the threshold number per pixel of the input image or the threshold number of each pixel on the matrix. Since it is configured, it is possible to deal with various matrix sizes without increasing the memory size and without reducing the output gradation value.

  Hereinafter, an embodiment of an image processing apparatus and method according to the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a block diagram of an apparatus configured by applying an image processing apparatus and method according to the present invention.

  When outputting multi-value image data transmitted from a computer (hereinafter referred to as “PC”), there is a multi-value dither method for outputting at a gradation closer to the input multi-value image data. This multi-value dither method There is a correction table for correcting the input gradation value of the input multi-valued image data to the output gradation value. The correction table is arranged in an m × n matrix so that gradation can be expressed in matrix units.

  1, the configuration diagram of the image processing apparatus includes a matrix counter 101, an address generation unit 102, a memory 103, a data comparison unit 104, and an output control unit 105.

  The matrix counter 101 performs processing by the multi-value dither method by sequentially counting in both the main scanning direction and the sub-scanning direction according to a preset m × n matrix size (m ≠ n or m = n). A matrix ID indicating the location of the input image data on the matrix is output.

  The address generation unit 102 converts an address and a select signal based on the matrix ID output from the matrix counter 101 and the number of threshold values set per pixel (hereinafter referred to as “threshold number”), and outputs the converted address. .

  The memory 103 outputs a correction table composed of threshold values and output gradation values stored in the addresses output from the address generation unit 102 as threshold data 0 to 15 and output gradation value data 0 to 15 It is.

  Threshold data 0, threshold data 1,..., Threshold data 15 at this time are specific numbers such as “12” and “20”, and output gradation value data 0, output gradation value data 1,. Each of the output gradation value data 15 is also a specific number similarly.

For example, threshold data and output gradation value data in the first row and first column of the correction table are stored as “8” and “16”, respectively. (Hereafter, the same description)
The data comparison unit 104 compares the input image data to be subjected to the multi-value dither processing with the threshold data output from the memory 103, and outputs the comparison result for the number of threshold data to be compared.

  The output control unit 105 outputs the output gradation value data output from the memory 103 based on the threshold number per pixel input to the address generation unit 102, the select signal output from the address generation unit 102, and the comparison result of the data comparison unit 104. Select and output.

  Next, the processing content by the said structure is demonstrated.

  Here, the gradation value of the image data input from the PC is 256 gradations (8 bits), the gradation value of the image data output from the image output device such as a printer is 16 gradations (4 bits), one pixel. When the threshold number per pixel is 16, the maximum matrix size is 64 pixels. When the threshold number per pixel is 2, the maximum matrix size is 512 pixels.

  At this time, the capacity of the memory is “64 pixels × ((8 bits + 4 bits) × 16 pairs)” and “12288 bits”.

  When 256-gradation image data is input, the matrix counter 101 counts in the main scanning and sub-scanning directions according to the size of the matrix, and indicates a matrix ID indicating the position of the input image data on the matrix. Is output. Since the value changes from 0 to “matrix size−1”, it is output as data of 9 bits in total.

  The matrix ID output from the matrix counter 101 is converted into an address and a select signal according to the threshold number per pixel by the address generation unit 102 and output.

  For example, in the case where the threshold number per pixel is “16” as described above, bits 5 to 0 of the matrix ID bits 8 to 0 are addresses, and when the threshold number per pixel is “8” , Matrix ID bits 6 to 1 are addresses and bit 0 is a select signal. When the threshold number per pixel is “4”, bits 7 to 2 of the matrix ID are addresses, and bit 1 and bit 0 are select signals. When the threshold number per pixel is “2”, the matrix ID Bits 8 to 3 are addresses, and bits 2 to 0 are select signals.

  According to the address converted by the address generation unit 102, a correction table constituted by a pair of threshold value and output tone value which is a tone value when outputting an image in the memory 103 is represented by threshold data 0 to 15, output tone Output as value data 0-15. The configuration of the correction table at this time is shown in FIG.

  The data comparison unit 104 receives the output threshold data 0 to 15 and the input image data. Both received data are compared, and the result is output as comparison results 0-15.

  The output control unit 105 receives the select signal from the address generation unit 102, the output gradation value data 0 to 15 from the memory 103, and the comparison results 0 to 15 from the data comparison unit 104. Output as output image data in consideration of the threshold number.

  In the example shown above, when the number of thresholds per pixel is “16”, the select signal does not exist (invalid state). The output image is controlled based on the output gradation value data 0 to 15 output from.

  FIG. 2 is a diagram showing the internal structure of the address generation unit 102 of the image processing apparatus according to the present invention.

  FIG. 2 includes a matrix ID 10, a threshold number 11 per pixel, a select signal 12, an address 13, selectors (14 -A to 14 -F), and an encoder 15.

  The matrix ID 10 is an ID indicating an arrangement location on the matrix output by the matrix counter 101 shown in FIG.

  A preset threshold value is input as the threshold value 11 per pixel.

  The select signal 12 is a signal output as one of the results processed by the address generation unit 103.

  Address 13 is a combination of the five output data output by the selectors (14-A to 14-F).

  The selectors (14-A to 14-F) receive and select the matrix ID and the signal from the encoder 15, and output an address signal.

  The encoder 15 receives an input of a threshold number per pixel and performs encoding based on an encoding value for a preset threshold number.

  Here, when the value set in FIG. 1 is used, the input matrix ID 10 value is changed from 0 to “matrix size−1”, so that it is output from the matrix counter 101 as “9 bits”. This is represented as [8: 0]. That is, bit 8, bit 7, bit 6,..., Bit 1, bit 0.

  Furthermore, when the threshold number per pixel is “2”, the bit 2 to bit 0 of the matrix ID is the select signal and the bits 8 to 3 are the address from the above, so the select signal 12 is expressed as [2: 0]. As the select signal 12 at this time, bits 2 to 0 of the matrix ID are output.

  Thus, the address generation unit 102 can generate a select signal and an address using the matrix ID and the threshold number per pixel as input values.

  FIG. 3 is a diagram showing the internal structure of the output control unit 105 of the image processing apparatus according to the present invention.

  FIG. 3 shows a processing structure from when the threshold number 21 per pixel and the select signal 22 are input until the output gradation value data 23 is output. The decoder 24, the AND circuit A (25-A). 25-P), an AND circuit B (26-A to 26-O), a mask (27-A to 27-P), and an OR circuit 28.

  The decoder 24 performs decoding based on the function table shown in FIG. 4 using the threshold value per pixel and the select signal as input data. For example, when the threshold number per pixel is “16” and the select signal is “XXX”, all “1” is output as the output data (Y0 to Y15) of the decoder. When the threshold number per pixel is “2” and the select signal is “000”, the decoder output data Y0 and Y1 are both “1”, and the other output data (Y2 to Y15) are “0” is output. “X” means that any value of “0” or “1” is ignored.

  The logical product circuit A (25-A to 25-P) performs a logical product operation using the result of comparison between the output of the decoder 24 and the data comparison unit 104 as input data.

  The logical product circuit B (26-A to 26-O) performs a negative operation and a logical product operation using two adjacent data among the output data of the logical product circuit A as input data.

  For example, the AND circuit B (26-A) receives the output data Y0 of the decoder 24 and the bit 0 data of the comparison result as inputs, and outputs the output data of the AND circuit A (25-A) and the decoder 24. Output data Y1 and bit 1 data of the comparison result are input, and data obtained by performing a logical AND operation on the output result of the logical product circuit A (25-B) obtained by performing a logical AND operation is output.

  The masks (27-A to 27-P) perform an operation based on the function table shown in FIG. 5 using the output gradation value data from the memory 103 and the output data of the AND circuit B as input data.

  For example, when the output gradation value data is “D” and the output data of the AND circuit B is “1”, “D” is output as the mask output data. That is, the input output gradation value data as it is is used as mask output data.

  The OR circuit 28 performs an OR operation using the data output from the masks (27-A to 27-P) as input data.

  Thus, output gradation value data, that is, output image data converted into 16 gradations can be output.

  FIG. 4 is a function table of the decoder 304 in the output control unit 105.

  4 is a functional table of the decoder 24 in the internal structure of the output control unit 105 shown in FIG. 3. The threshold value per pixel is “A”, and the select signal 23 in FIG. 3 is “B [2: 0]”. The data (Y0 to Y15) output from the decoder 24 is shown in the list.

  For example, all the data (Y0 to Y15) output from the decoder 24 when “A” is “16” and “B [2: 0]” is “XXX” as the record shown at the top of the function table. Is “1”.

  FIG. 5 is a function table of the masks (307-A to 307-P) in the output control unit 105.

  FIG. 5 shows a function table of the masks (27-A to 27-P) shown in FIG.

  For example, the output gradation value data input to the masks (27-A to 27-P) is “D”, the data output from the AND circuit B is “EN”, and the operation result is “Y”. When the “EN” value is “0 (zero)”, the calculation result “Y” is also “0 (zero)”, and when the “EN” value is “1”, the calculation result “Y” is output. It indicates that the gradation value is “D”.

  That is, when the data “EN” output from the AND circuit B is “1”, the output gradation value data is used as output data of the mask (27-A to 27-P) as it is. Yes.

  FIG. 6 shows the contents of the memory 103 according to the present invention.

  FIG. 6 shows a case where the threshold value and the output gradation value with respect to the threshold value are paired as stored data in the memory.

  For example, when the threshold number per pixel is “16” and the matrix ID is n (n: 0 to 63), the correction table is “threshold value: 16n to 16n + 15” and “output gradation value: 16n to 16n + 15”. When the threshold number is “8” and the matrix ID is n (n: 0 to 127), the correction table is “threshold value: 8n to 8n + 7” and “output gradation value: 8n to 8n + 7”. When the threshold number is “4” and the matrix ID is n (n: 0 to 255), the correction table is “threshold: 4n to 4n + 3” and “output gradation value: 4n to 4n + 3”, and the matrix ID is When n (n: 0 to 511), the correction table is “threshold value: 2n to 2n + 1” and “output gradation value: 2n to 2n + 1”.

  In other words, it is possible to set a correction table that requires the same output tone value even for non-continuous input tone values by having a pair of threshold values and output tone values for the threshold values.

  FIG. 7 is a diagram graphically showing an example when the input gradation values are not continuous.

  When the input tone values as shown in FIG. 7 are not continuous, if the correction table is configured with only threshold values, only one specific threshold value can be set for one output tone value.

  With such non-continuous input tone values, it is not possible to set a correction table when the same output tone value is required for the input tone value.

  FIG. 8 is a diagram that quantitatively represents an example when the input tone values are not continuous.

  FIG. 8 quantitatively represents the output tone value with respect to the threshold when the data of the non-continuous input tone value shown in FIG. 7 is input.

  For example, when the threshold value is “80”, the output gradation value is “6”. When the threshold value is “112”, the output gradation value is “6”. Show. This indicates that the output gradation values are not continuous with respect to the threshold value. In this case, the correction table is composed of the threshold value and the output gradation value with respect to the threshold value in this case as well. On the other hand, a correction table that requires the same output gradation value can be set.

  FIG. 9 and FIG. 10 are diagrams showing the bias of the output image threshold in a general multi-value dither method.

  FIG. 9 shows a graph in the case where many threshold values are required in the low density region of the input gradation value, whereas almost no threshold value is required in the medium and high density regions.

  FIG. 10 shows a graph in the case where many threshold values are required in the high density region of the input gradation value, whereas in contrast, in the low and medium density regions, almost no threshold value is required.

  With the configuration and processing of the first embodiment described above, in the image processing apparatus of the present invention, even when the input tone values of the input image data as shown in FIG. Therefore, it is possible to set a correction table that requires the same output gradation value.

  Furthermore, since the dither matrix size is determined by the number of thresholds per pixel and the number of thresholds per pixel is set to “reciprocal of (2 to the power of n)”, the output gradation value is reduced. Without this, the dither matrix size can be increased to (2 to the power of n).

  FIG. 11 is a block diagram of an apparatus configured by applying the image processing apparatus and method according to the second embodiment of the present invention.

  11 includes a matrix counter 201, a basic address generation unit 202, an address generation unit 203, a memory 204, a data rearrangement unit 205, a data comparison unit 206, and an output control unit 207.

  The matrix counter 201 is a matrix indicating an arrangement location on the matrix of input image data to be processed by the multi-value dither method by sequentially counting in both the main scanning direction and the sub-scanning direction according to a preset matrix size. ID is output.

  The basic address generation unit 202 holds the threshold number in each pixel on the matrix in advance, and outputs threshold number data and a basic address according to the matrix ID output by the matrix counter 201.

  The address generation unit 203 divides the address generated by the basic address generation unit 202 into upper bits and lower bits, and outputs the addresses according to the lower bits.

  The memory 204 outputs a threshold value and an output gradation value stored in advance at each address output by the address generation unit 203.

  The data rearrangement unit 205 rearranges the threshold value and the output gradation value for each address output from the memory 204 according to the basic address generated by the basic address generation unit, and the rearranged threshold value data and output gradation value data. Are output respectively.

  The data comparison unit 206 compares the input image data with the threshold value data rearranged by the data rearrangement unit 205, and outputs each comparison result.

  The output control unit 207 receives the result of comparison by the data comparison unit 206 with the output gradation value data after the data rearrangement unit 205 performs the rearrangement, controls the output data, and outputs the output image data. Output.

  Next, processing contents of the configuration in the second embodiment will be described.

  In the second embodiment, the gradation value of the input image data is 256 gradations, the gradation value of the output data is 16 gradations, the maximum value of the threshold number in each pixel on the dither matrix is 16, and the minimum value is 2. Further, the maximum matrix size when the threshold number of all pixels is 16 is 64 pixels, and the maximum matrix size when the threshold number of all pixels is 2 is 512 pixels.

  At this time, the memory capacity is “64 pixels × ((8 bits + 4 bits) × 16 pairs)” and “12288 bits”.

  When 256-gradation image data is input, the matrix counter 201 counts in the main scanning and sub-scanning directions according to the matrix size, and a matrix ID and matrix indicating the position of the input image data on the matrix. Output a control signal. Since the matrix ID at this time becomes “matrix ID-1” from 0, it is output as 9-bit data.

  Upon receiving the output matrix ID, the basic address generation unit 202 generates a basic address according to the threshold number of each pixel on the matrix held in advance, and outputs threshold number data and the basic address.

  The output threshold data is the threshold number of pixels indicated by the matrix ID. The basic address is “0 (zero)” when the matrix ID is “0 (zero)”, and the matrix ID is M (M is 1 or more). Outputs the total number of threshold values of each pixel of “0 to M−1”. The matrix ID M at this time is in the range of 1 to 511 because the maximum matrix size is 512 pixels when the threshold number is 2.

  As a result, the total maximum number of threshold values is “1024 (2 to the 10th power)” of “threshold number 16 × 64 pixels”, and the basic address is 10 bits. An example of the correction table at this time is shown in FIG.

  The address of the basic address generation unit 202 in the correction table shown in FIG. 20 will be described.

The basic address generation unit 202
(1) When the matrix ID is “0”, the basic address is “0” and the threshold number data is “12”.
(2) When the matrix ID is “1”, the basic address is “12” and the threshold number data is “9”.
(3) When the matrix ID is “2”, the basic address is “21” and the threshold number data is “14”.
(4) When the matrix ID is “3”, the basic address is “35” and the threshold number data is “16”.
Is output. That is, the basic address indicates the start address of the correction table for each pixel in the basic address section, and the threshold number data indicates the effective range from the start address.

  Of the basic address and threshold value data output by the basic address generation unit 202, the address generation unit 203 performs processing on the basic address. The address generation unit 203 processes the upper 6 bits of 64 pixels (2 to the sixth power) of the basic address 10 bits based on the lower 4 bits of the threshold number 16 (2 to the fourth power) to generate an address.

  For example, when all the lower 4 bits of the basic address are 0 (zero), the generated address is the upper 6 bits of the basic address, and when the lower 4 bits of the basic address is N (N: 1 to 15), it is generated. Addresses N to 15 are output with the upper 6 bits of the basic address plus addresses 0 to N-1 plus the upper 6 bits of the basic address.

  In the memory 204, a correction table composed of threshold values and output gradation values stored based on the addresses (0 to N-1, N to 15) generated by the address generation unit 203 is output for each address. To do.

  The threshold values output from the memory 204 and the numerical values (data) of the output gradation values are rearranged according to the lower 4 bits of the basic address generated by the basic address generation unit 202, and the threshold values after the rearrangement are performed. Are output to the data comparison unit 206, and each output gradation value is output to the output control unit 207.

  For example, when the lower 4 bits of the basic address are 0, the threshold value and the output gradation value are output without being rearranged. On the other hand, when the lower 4 bits of the basic address are N (N: 1 to 15), the threshold data N to 15 are rearranged to the threshold data 0 to 15-N, and the threshold data 0 to N-1 are changed to the threshold data N to N. The output gradation value data N to 15 are rearranged to the output gradation value data 0 to 15-N, and the output gradation value data 0 to N-1 are changed to the output gradation value data N to 15. Sort. FIG. 21 shows an example of the correction table when the correction table in the basic address space at this time is converted into the memory address space.

  The threshold data 0 to 15 and the input image data output from the data rearrangement unit 205 are received, the data comparison unit 206 compares both, and outputs the result to the output control unit 207.

  The comparison result in the data comparison unit 206, the output gradation value data from the data rearrangement unit 205, and the threshold number data from the basic address generation unit 202 are received, and the output gradation value data is received by the comparison result and the threshold number data. Select and output as output image data.

  That is, when the threshold number data is L (L: 2 to 16), the correction table is the rearranged threshold data 0 to L-1, and the output gradation value data 0 to L-1, so that the comparison result 0 Output image data is selected from output gradation value data 0 to L-1 after rearrangement according to .about.L-1.

  With the configuration in which the dither matrix size is determined by the total number of thresholds of each pixel on the matrix as described above, the output gradation value remains constant, and an image output device such as a printer that outputs an image is input. Various dither matrices can be constructed according to the incoming image data.

  FIG. 12 is a diagram showing the internal structure of the basic address generation unit 202 according to the second embodiment of the present invention.

  12 includes a threshold number setting register 30, an adder 31, a basic address selector 32-A, and a threshold number data selector 32-B.

  The threshold number setting register 30 outputs threshold number data set (held) in advance based on the matrix ID indicating the arrangement location of the input image data on the matrix by the matrix counter 201.

  The adder 31 adds threshold number data in order.

  In the example shown in FIG. 12, first, the threshold number data 0 is the leading data of the threshold number data, and is input as D1 to the basic address selector 32-A without adding other data. Next, a value obtained by adding the threshold number data 0 which is the initial data to the threshold number data 1 is input to the basic address selector 32-A as D2. Similarly, processing is performed up to the threshold number data 510.

  The basic address selector 32-A selects the basic address based on the matrix ID using the data output from the threshold value setting register 30 and added by the adder 31 and the matrix ID as input data.

  The threshold number data selector 32-B receives the value output from the threshold number setting register 30 and the matrix ID as input data, and selects threshold number data based on the matrix ID.

  Thus, the basic address generation unit can generate threshold number data and basic addresses.

  FIG. 13 is a function table in the basic address generator of the second embodiment according to the present invention.

  FIG. 13 is a table of threshold number data or basic address data to be selected based on the matrix ID.

  FIG. 14 is a diagram showing the internal structure of the address generation unit 203 according to the second embodiment of the present invention.

  FIG. 14 includes a decoder 40 and an adder 41.

  The decoder 40 receives the basic address [3: 0] among the generated basic addresses, decodes it based on the function table shown in FIG. 15, and outputs it.

  The adder 41 adds the data decoded by the decoder 40 and the basic address [9: 4] among the generated basic addresses, and outputs an address [5: 0] for six basic addresses. is there.

  Thereby, an address is generated.

  FIG. 15 is a function table in the decoder 40 of the address generation unit 203 according to the second embodiment of the present invention.

  FIG. 15 shows values (Y0 to Y15) decoded for the lower 4 bits of the basic address (basic address [3: 0]). For example, when the lower 4 bits of the base address are “12” in decimal, the values to be decoded indicate that Y0 to Y11 are decoded to “1” and Y12 to Y15 are decoded to “0”. .

16 is a diagram showing the internal structure of the output control unit 207 according to the second embodiment of the present invention, and FIG. 17 is a function table in the decoder 50 of the output control unit 207 according to the second embodiment of the present invention. 16 includes a decoder 50, an AND circuit C (51-A to 51-P), an AND circuit D (51-A to 51-O), a mask 53, and an OR circuit 54.

  The decoder 50 performs decoding based on the function table shown in FIG. 17 using the threshold value per pixel as input data.

  For example, when the threshold number per pixel is “8”, “1” is output to the decoder output data (Y0 to Y7), and “0” is output to the output data (Y8 to Y15).

  The logical product circuit A (51-A to 51-P) performs a logical product operation using the result of comparison between the output of the decoder 50 and the data comparison unit 206 as input data.

  The logical product circuit B (52-A to 52-O) performs a negative operation and a logical product operation using two adjacent data of the output data of the logical product circuit A as input data.

  For example, the AND circuit B (52-A) receives the output data Y0 of the decoder 50 and the bit 0 data of the comparison result as inputs and outputs the output data of the AND circuit A (51-A) and the decoder 50. Output data Y1 and the bit 1 data of the comparison result are input, and the output result of the logical product circuit A (51-B) obtained by performing a logical product operation is negated and the logical product of the output result is output.

  The masks (53-A to 53-P) perform calculations based on the function table shown in FIG. 5 using the output gradation value data after the rearrangement from the memory 204 and the output data of the AND circuit B as input data.

  For example, when the output gradation value data is “D” and the output data of the AND circuit B is “1”, “D” is output as the mask output data.

  The OR circuit 54 performs OR operation using the data output from the masks (53-A to 53-P) as input data.

  Thus, output gradation value data, that is, output image data converted into 16 gradations can be output.

  FIG. 18 is a function table of the threshold value data of the data rearrangement unit 205 according to the second embodiment of the present invention. FIG. 19 is a table of output tone value data of the data rearrangement unit 205 according to the second embodiment of the present invention. It is a function table.

  Threshold data or output gradation value data after rearrangement is shown for the lower 4 bits (0 to 15) of the basic address.

  20 and 21 are diagrams showing examples of correction tables that can be set in the configurations shown in FIGS.

  FIGS. 20 and 21 show examples of correction tables for non-consecutive input tone values when output tone values are set in the configuration shown in FIGS. 11 to 19 of the second embodiment.

In FIG. 20, the matrix size is 4 pixels, and the setting of each pixel on the matrix is
(1) Matrix ID: 0, number of thresholds: 12, threshold: threshold 0-1 to threshold 0-12, output gradation value: output gradation value 0-1 to output gradation value 0-12
(2) Matrix ID: 1, threshold number: 9, threshold value: threshold value 1-1 to threshold value 1-9, output gradation value: output gradation value 1-1 to output gradation value 1-9
(3) Matrix ID: 2, Number of threshold values: 14, Threshold value: Threshold value 2-1 to Threshold value 2-14, Output gradation value: Output gradation value 2-1 to Output gradation value 2-14
(4) Matrix ID: 3, threshold number: 16, threshold value: threshold value 3-1 to threshold value 3-16, output gradation value: output gradation value 3-1 to output gradation value 3-16
The structure of the correction table is shown.

  For example, all the high-order 6 bits of address 0 are output. In other words, the lower 4 bits of values from 0 to 15 are output, and processing is performed with the threshold number (= 12) of “matrix ID: 0” being valid.

  As a result, the memory can be used in a state in which the threshold value and the output gradation value are packed.

  FIG. 21 is a diagram showing a correction table in the address space of the memory according to the second embodiment of the present invention.

  In FIG. 21, when the matrix ID is “0”, that is, when the basic address is “0”, the address generation unit 203 outputs “0” to all the addresses 0 to 15 and the memories 4 to 19 store the threshold data 0 to Threshold values 0-1 to 0-12 and 1-1 to 1-4 are output to 15, and output gradation values 0-1 to 0-12 and 1-1 to 1-4 are output to output gradation value data 0-15. Is output. The data rearrangement unit 205 outputs the threshold values 0-1 to 0-12 and 1-1 to 1-4 as they are to the threshold data 0 to 15, and outputs the output gradation values 0 to 15 as they are to the output gradation value data 0 to 15, respectively. 12 and 1-1 to 1-4 are output.

  When the matrix ID is “1”, that is, when the basic address is “12”, the address generation unit 203 outputs “0” to the addresses 12 to 15 and “1” to the addresses 0 to 11. The memories 4 to 19 sequentially output threshold values 1-5 to 1-9, 2-1 to 2-7, 1-1 to 1-4 to the threshold data 0 to 15, and output to the output gradation value data 0 to 15 The gradation values 1-5 to 1-9, 2-1 to 2-7, and 1-1 to 1-4 are output in order. The data rearrangement unit 205 rearranges the threshold data 12 to 15 into the threshold data 0 to 3, rearranges the threshold data 0 to 11 into the threshold data 4 to 15, and converts the output gradation value data 12 to 15 to the output gradation value. The data is rearranged to data 0 to 3, and the output gradation value data 0 to 11 are rearranged to output gradation value data 4 to 15.

  Then, the threshold values 1-1 to 1-9 and 2-1 to 2-7 are output to the threshold data 0 to 15 after the rearrangement, and the output gradation value data 0 after the rearrangement is performed. Output gradation values 1-1 to 1-9 and 2-1 to 2-7.

  When the matrix ID is “2”, that is, when the basic address is “21”, the address generation unit 203 outputs “1” to the addresses 5 to 15 and “2” to the addresses 0 to 4. The memories 4 to 19 sequentially output threshold values 2-12 to 2-14, 3-1 to 3-2, and 2-1 to 2-11 to the threshold data 0 to 15, respectively, and output gradation value data 0 to 15 are output. Output gradation values 2-12 to 2-14, 3-1 to 3-2, and 2-1 to 2-11 are output in order. At this time, the data rearrangement unit 205 rearranges the threshold data 5 to 15 into the threshold data 0 to 10, rearranges the threshold data 0 to 4 into the threshold data 11 to 15, and outputs the output gradation value data 5 to 15 as the output level. Rearranged to key value data 0-10.

  Then, the threshold values 2-1 to 2-14 and 3-1 to 3-2 are output as the threshold data 0 to 15 after the rearrangement, and the output gradation value data 0 after the rearrangement is performed. Output gradation values 2-1 to 2-14 and 3-1 to 3-2.

  When the matrix ID is “3”, that is, when the basic address is “35”, the address generation unit 203 outputs “2” to the addresses 3 to 15 and “3” to the addresses 0 to 2. The memories 4 to 19 sequentially output threshold values 3-14 to 3-16 and 3-1 to 3-13 to threshold data 0 to 15, and output gradation values 3-14 to output gradation value data 0 to 15, respectively. 3-16 and 3-1 to 3-13 are sequentially output. At this time, the data rearrangement unit 205 rearranges the threshold data 3 to 15 into the threshold data 0 to 12, and rearranges the threshold data 0 to 2 into the threshold data 13 to 15.

  Then, the threshold values 3-1 to 3-16 are output to the threshold data 0 to 15 after the rearrangement is performed, and the output gradation value 3 is output to the output gradation value data 0 to 15 after the rearrangement is performed. -1 to 3-16 are output.

  With a configuration in which output is performed by performing such rearrangement, the threshold data 0-15 after the rearrangement and the output gradation value data 0-15 after the rearrangement include a matrix. A correction table corresponding to each upper pixel can be output.

  With the configuration and processing of the second embodiment described above, the image processing apparatus of the present invention can set a correction table that requires the same output tone value for non-continuous input tone values. Furthermore, the threshold number can be set for each pixel on the matrix.

  Thus, it is possible to set the threshold number corresponding to a wide range of input image data without increasing the memory capacity.

  Therefore, by applying the present invention, it can be expected that various dither matrices can be constructed according to the type of image output device and the type of input image data input.

  The processing shown in the flowchart can also be realized by an image processing program that can be executed by a computer.

  The present invention is not limited to the embodiments described above and shown in the drawings, and can be implemented with appropriate modifications within the scope not changing the gist thereof.

  The present invention can be applied to an image processing apparatus that performs image processing on multi-valued image data transmitted from a computer using a multi-value dither method. In particular, a threshold value and an output level corresponding to the threshold value are applied to a multi-value dither method correction table. Since the gradation value is provided, it is useful for dealing with matrix sizes in all multi-value dither methods without increasing the capacity of the memory mounted in the apparatus and without lowering the output gradation value.

The figure which shows the structure of the image processing apparatus concerning this invention. 2 is a diagram showing an internal structure of an address generation unit 102 of the image processing apparatus according to the present invention. FIG. The figure which shows the internal structure of the output control part 105 of the image processing apparatus concerning this invention. 6 is a function table of a decoder in the output control unit 105 of the image processing apparatus according to the present invention. 4 is a mask function table in the output control unit 105 of the image processing apparatus according to the present invention. The figure which shows the content of the memory 103 of the image processing apparatus concerning this invention. The figure which shows the example in case an input gradation value is not continuous graphically. The figure which expressed quantitatively the example in case an input gradation value is not continuous. The figure which shows the bias | deviation of the threshold value of the output image in a normal multi-value dither system. The figure which shows the bias | deviation of the threshold value of the output image in a normal multi-value dither system. The block diagram of the apparatus comprised by applying the image processing apparatus in Example 2 concerning this invention. The figure which shows the internal structure of the basic address generation part 202 of Example 2 concerning this invention. The function table | surface in the basic address generation part 202 of Example 2 concerning this invention. The figure which shows the internal structure of the address generation part 203 of Example 2 concerning this invention. The function table in the decoder of the address generation part 203 of Example 2 concerning this invention. The figure which shows the internal structure of the output control part 207 of Example 2 concerning this invention. The function table in the decoder of the output control part 207 of Example 2 concerning this invention. The function table in the threshold value of the data rearrangement part 205 of Example 2 concerning this invention. The function table in the output gradation value of the data rearrangement part 205 of Example 2 concerning this invention. The figure which shows the correction table in the basic address space of Example 2 concerning this invention. The figure which shows the correction table in the address space of the memory of Example 2 concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Matrix counter 102 Address generation part 103 Memory 104 Data comparison part 105 Output control part 201 Matrix counter 202 Basic address generation part 203 Address generation part 204 Memory 205 Data rearrangement part 206 Data comparison part 207 Output control part

Claims (4)

In an image processing apparatus for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of the output image in a matrix unit of a predetermined size,
A matrix counter that counts in the main scanning direction and sub-scanning direction of the input image corresponding to the size of the matrix and outputs position information indicating the position of the pixel of the input image in the matrix;
Address generating means for generating a selection signal and an address for selecting the output gradation value based on the threshold number per pixel of the output image and the position information output from the matrix counter;
A pair of threshold values and output gradation values corresponding to the number of threshold values per pixel of the output gradation value is stored in each address, and the threshold value and the output are designated by designation of the address generated by the address generation means. A correction table for reading out gradation values;
Comparison means for comparing the threshold value read from the correction table with the input gradation value of the input image;
Output control means for selecting an output gradation value read from the correction table based on the threshold value per pixel of the output gradation value, the selection signal, and the output of the comparison means, An image processing apparatus. In an image processing apparatus for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of the output image in a matrix unit of a predetermined size,
A matrix counter that counts in the main scanning direction and sub-scanning direction of the input image corresponding to the size of the matrix and outputs position information indicating the position of the pixel of the input image in the matrix;
Basic address generation means for outputting a basic address and outputting a threshold number of each pixel of the output image on the matrix set in advance based on the position information output from the matrix counter;
Address generating means for generating an address based on the basic address output from the basic address generating means;
A correction table that stores a pair of a threshold value of the output gradation value and an output gradation value at each address, and reads out the threshold value and the output gradation value by designation of the address generated by the address generation unit;
Reordering means for reordering the threshold value read from the correction table and the output gradation value according to the basic address generated by the basic address generating means;
A comparison means for comparing the threshold value rearranged by the rearrangement means with an input gradation value of the input image;
Output control means for selecting the output gradation values rearranged by the rearrangement means based on the threshold number output from the basic address generation means and the output of the comparison means. apparatus. In an image processing apparatus that performs image processing for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of the output image in a matrix unit of a predetermined size,
Counting in the main scanning direction and sub-scanning direction of the input image corresponding to the size of the matrix, and outputting by the matrix counter position information indicating the position of the pixel of the input image in the matrix,
The address generation means generates a selection signal and an address for selecting the output gradation value based on the threshold number per pixel of the output image and the position information output from the matrix counter,
A pair of threshold values and output gradation values corresponding to the number of threshold values per pixel of the output gradation value is stored in each address, and the threshold value and the output are designated by designation of the address generated by the address generation means. Read the gradation value from the correction table,
The threshold value read from the correction table and the input tone value of the input image are compared by a comparison unit,
An image processing method comprising: selecting an output gradation value read from the correction table based on a threshold number per pixel of the output gradation value, the selection signal, and an output of the comparison unit. In an image processing method for performing image processing for correcting an input gradation value of each pixel of an input image to an output gradation value of each pixel of an output image in a matrix unit of a predetermined size,
Counting in the main scanning direction and sub-scanning direction of the input image corresponding to the size of the matrix, and outputting by the matrix counter position information indicating the position of the pixel of the input image in the matrix,
Output a threshold number of each pixel of the output image on the matrix set in advance based on the position information output from the matrix counter, and output a basic address by basic address generation means,
Based on the basic address output from the basic address generating means, an address is generated by the address generating means,
A pair of the output gradation value threshold value and the output gradation value is stored in each address, and the threshold value and the output gradation value are read out from the correction table by designating the address generated by the address generation unit,
The threshold value read from the correction table and the output gradation value are rearranged by the rearrangement unit according to the basic address generated by the basic address generation unit,
The threshold value rearranged by the rearranging means and the input gradation value of the input image are compared by a comparing means,
An image processing method comprising: selecting the output gradation values rearranged by the rearrangement unit based on the threshold number output from the basic address generation unit and the output of the comparison unit.

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