JP2006013319A - Semiconductor device and ferrodielectric memory, manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can allow a leak current even when it is of a stack type and is reduced in size up to the necessary size. <P>SOLUTION: A capacitor 102 is formed of a lower electrode 111 provided over the SiO2 layer 119 on an impurity layer 117 provided to a substrate 100, a ferroelectric layer 109 provided on the lower electrode 111, and an upper electrode 107 provided on the ferroelectric layer 109. Moreover, the capacitor is provided with the SiO2 layer 118 for electrically insulating the upper electrode 107 and a wiring 105, a contact hole 103a for a W-plug 113 to electrically connect the impurity layer 117 and lower electrode 111, and a contact hole 103b for electrically connecting the lower electrode 111 and the wiring 105. The contact hole 103a and contact hole 103b are opened at the position away from the center of the capacitor 102 in the plane. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, a ferroelectric memory, and a method for manufacturing a semiconductor device.

  It is known that a memory using a ferroelectric (ferroelectric memory) is more advantageous than a memory using an insulating material in terms of low power consumption. Further miniaturization and higher integration are desired for ferroelectric memory cells. However, the leakage current of a ferroelectric memory cell generally increases as the size of the cell decreases. For this reason, in the development of a ferroelectric memory, if priority is given to miniaturization, there is a risk of losing the advantage of low power consumption of the ferroelectric memory. Therefore, it is necessary to consider the size of the cell together with the allowable range of the leakage current and the request for the size of the cell.

  The cell structure of the ferroelectric memory includes a stack type and a planar type. 6A and 6B are diagrams showing a stack type memory cell structure, where FIG. 6A shows a top surface and FIG. 6B shows a cross section. The memory cell shown in FIG. 6 has a lower electrode 11, a dielectric layer 9, and an upper electrode 7. A plug 13 is formed under the lower electrode 11 to make electrical contact between an impurity layer (not shown) and the lower electrode 11. An insulating film 15 such as SiO 2 is provided on the upper electrode 7, and a wiring layer 5 is formed on the insulating film 15. The plug 13 is formed by embedding a metal such as tungsten in the contact hole 3a. Further, the wiring layer 5 and the upper electrode 7 are in electrical contact via the contact hole 3b.

In the stacked cell, a contact hole 3b is formed immediately above the contact hole 3a. For this reason, the stack type cell has a square shape in which the top surface a and the side b in the figure are equal.
The illustrated configuration of the stack type cell is advantageous in reducing the occupied area of the cell as compared with the planar type in which the two contact holes are formed at positions apart from each other. For this reason, it is desirable to adopt a stack type cell for a product from the viewpoint of cell miniaturization. However, the stack type cell has a structure in which the leakage current is larger than that of the planar type cell, and if it is miniaturized to a desired size, the power consumption becomes a value unsuitable for practical use.

For this reason, in the prior art, it has been considered to reduce the size of the planar cell that is advantageous in terms of power consumption. As such a conventional technique, for example, the conventional technique described in Patent Document 1 can be cited. Japanese Patent Application Laid-Open No. H10-228707 describes a technique for reducing the area occupied by a cell by adjusting the contact hole position of a planar cell to increase the degree of integration. In addition, as in Patent Document 2, a technique has been proposed in which the upper electrode and the lower electrode are configured to have different sizes to further reduce the leakage current of the planar type cell.
JP-A-10-229168 JP-A-10-65113

  However, all of the above-described conventional techniques adopt a planar cell and attempt to improve this. For this reason, it is difficult to miniaturize the cell to the same size as that obtained when the stack type cell is employed. The present invention has been made in view of the above points, and provides a semiconductor device, a ferroelectric memory, and a method of manufacturing a semiconductor device that can allow a leak current even when miniaturized to a required size while being a stack type. The purpose is to do.

  In order to solve the above problems, a semiconductor device of the present invention includes a first electrode provided on a first insulating member, a power storage member provided on the first electrode, and a second electrode provided on the power storage member. A stack type capacitor portion including an electrode; a second insulating member provided on the second electrode; electrically insulating the second electrode and the wiring member; and opening on the first insulating member; A first contact hole in which a conductive member for electrically connecting the local conductive layer under the insulating member and the first electrode is embedded; and an opening on the second insulating member; the second electrode and the wiring member; The first contact hole and the second contact hole are opened at positions where the center of the opening surface is deviated from the center of the stacked capacitor portion in plan view. It is characterized by .

  According to such an invention, a stack type capacitor unit can be formed by providing the first electrode on the insulating member, providing the power storage member on the first electrode, and further providing the second electrode. Also, a first contact hole is opened in the insulating member under the first electrode, and a plug is formed by filling with a conductive member, and the first electrode and the conductive layer under the insulating member are electrically connected via the plug. Can be connected. Further, a second contact hole is opened in the insulating member on the second electrode, and the second electrode and the wiring member are electrically connected. Then, the first contact hole and the second contact hole can be opened at a position deviated from the center of the stacked capacitor portion in plan view.

  The power storage member is damaged by the formed plug. In addition, it is damaged when a contact hole for making contact with the wiring is formed. However, in the present invention, the portion that is strongly damaged by plug formation and the portion that is strongly damaged by contact hole formation are both shifted from the center of the power storage member. For this reason, it is possible to sufficiently secure a region functioning normally as a memory and to reduce the leakage current flowing in the power storage member. The present invention as described above can provide a semiconductor device that can tolerate a leakage current even when it is miniaturized to a required size while being a stack type.

In the semiconductor device of the present invention, the stacked capacitor portion has a rectangular shape in plan view, and the first contact hole and the second contact hole are located at positions where the center of the opening surface is deviated from the center point of the rectangular shape. It is characterized by being opened.
According to such an invention, it is possible to effectively shift the area that receives damage from the area near the center of the power storage member.

The semiconductor device of the present invention is characterized in that the stacked capacitor section is rectangular in plan view.
According to such an invention, the leakage current can be further reduced by preventing damage to the other square region in which the contact hole is shifted to the square side that divides the rectangular power storage member into two.

The semiconductor device according to the present invention is characterized in that the first contact hole and the second contact hole are positioned so that the centers of the opening surfaces are aligned with each other. Thus, the leakage current can be further reduced by minimizing the region that receives the leakage.
Further, in the semiconductor device of the present invention, the first contact hole and the second contact hole are outside a predetermined range including the center of the stacked capacitor unit in a plan view of the stacked capacitor unit, and The opening is made in an opening range that is a predetermined distance or more away from the outer periphery of the stacked capacitor unit.

According to such an invention, the first contact hole and the second contact hole can be opened while being displaced to an appropriate position from the viewpoint of reducing leakage current and process margin.
The semiconductor device of the present invention is characterized in that a plurality of the first contact holes and the second contact holes are opened in the opening range.

According to such an invention, the contact resistance can be reduced by opening a plurality of contact holes. As a result, it is possible to suppress an increase in contact resistance as the contact hole diameter is reduced due to miniaturization.
The ferroelectric memory according to the present invention includes any one of the semiconductor devices described above.

According to such an invention, a ferroelectric memory provided with any one of the semiconductor devices of the present invention described above can be provided.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, the step of forming a first contact hole in a first insulating member, the step of filling the first contact hole with a conductive member to form a conductive plug, Forming a first electrode layer thereon, providing a power storage member on an upper surface of the first electrode layer, providing a second electrode layer on an upper surface of the power storage member layer, the first electrode layer, The power storage member and the second electrode layer are processed by a single photolithography process, and the center of the planar shape is deviated from the center of the opening surface of the first contact hole in the planar shape of the first electrode after processing. Forming a stack type capacitor part, forming a second insulating member on the stack type capacitor part, and on the second insulating member, the stack type capacitor part In the surface view, characterized in that it comprises a step of opening a second contact hole so that an opening surface center at a position offset from the center of the stacked capacitor portion is located, the.

  According to such an invention, a stack type capacitor unit can be formed by providing the first electrode on the insulating member, providing the power storage member on the first electrode, and further providing the second electrode. Also, a first contact hole is opened in the insulating member under the first electrode, and a plug is formed by filling with a conductive member, and the first electrode and the conductive layer under the insulating member are electrically connected via the plug. Can be connected. Further, a second contact hole is opened in the insulating member on the second electrode, and the second electrode and the wiring member are electrically connected. Then, the first contact hole and the second contact hole can be opened at a position deviated from the center of the stacked capacitor portion in plan view.

  The power storage member is damaged by the formed plug. In addition, it is damaged when a contact hole for making contact with the wiring is formed. However, in the present invention, the portion that is strongly damaged by plug formation and the portion that is strongly damaged by contact hole formation are both shifted from the center of the power storage member. For this reason, it is possible to sufficiently secure a region functioning normally as a memory and to reduce the leakage current flowing in the power storage member. The present invention as described above can provide a method for manufacturing a semiconductor device capable of allowing a leakage current even if it is a stack type, even if it is miniaturized to a required size.

Embodiments of a ferroelectric memory according to the present invention will be described below with reference to the drawings. 1A and 1B are diagrams for explaining a semiconductor device according to an embodiment of the present invention. FIG. 1A is a top view of a capacitor portion 102 of a cell 101, and FIG. In the present specification, the top view shown in FIG. 1A shows a plan view of a stack type capacitor section described later.
The semiconductor device of this embodiment is configured as a ferroelectric memory. In the semiconductor device, an impurity layer 117 into which impurities are implanted is provided as a local conductive layer on a substrate, and is formed on a SiO 2 layer 119 that is a first insulating member on the impurity layer 117. Then, a lower electrode 111 that is a first electrode provided on the SiO 2 layer 119, a ferroelectric layer 109 that is a power storage member provided on the lower electrode 111, and a second electrode provided on the ferroelectric layer 109 The upper electrode 107 is provided.

  Furthermore, the semiconductor device of this embodiment has a wiring 105 provided on the upper electrode 107. The wiring 105 includes an SiO 2 layer 118 that is a second insulating member that electrically insulates the upper electrode 107 and the wiring 105 from each other. In the SiO2 layer 119, for example, tungsten is embedded as a conductive member for electrically connecting the impurity layer 117 and the lower electrode 111, and a contact hole 103a for forming the W plug 113 is opened. In addition, a contact hole 103 b for electrically connecting the upper electrode 107 and the wiring 105 is opened in the SiO 2 layer 118.

  In this embodiment, for example, a composite electrode of Ir / IrOx / Pt is used for the lower electrode 111, and a composite electrode of Pt / IrOx / Ir is used for the upper electrode 107. For example, a TiAlN film (not shown) is formed for the purpose of preventing tungsten oxidation before the lower electrode 111 is formed. The ferroelectric layer 109 is made of a PZT-based or PZTN-based material.

  Further, for example, Ti / TiN or aluminum can be used for the wiring 105, and the impurity layer 117 is a source or a drain of the transistor 120 over the substrate 100. Further, a configuration including the lower electrode 111, the ferroelectric layer 109, and the upper electrode 107 is referred to as a stack type capacitor portion 102 in the present embodiment. In the present embodiment, the capacitor unit 102 is covered with a barrier film 115 such as an alumina film.

In the present embodiment, the contact hole 103a is a first contact hole, and the contact hole 103b is a second contact hole. Note that in the contact hole 103a, a surface from which the impurity layer 117 is exposed is an opening surface 104a. In the contact hole 103b, the surface from which the upper electrode 107 is exposed is defined as an opening surface 104b.
In the present embodiment, the contact hole 103a and the contact hole 103b are opened at a position where the center of the opening surface is deviated from the center in plan view of the capacitor unit 102 shown in FIG.

  That is, the capacitor part 102 is formed in a rectangular shape in plan view. In the present embodiment, a straight line connecting two opposing vertices (vertex a-c and vertex b-d) among the four rectangular vertices a, b, c, d intersects the center of the rectangular capacitor portion 102. It is assumed that the intersection C1. Then, the contact holes 103a and 103b are opened at positions where the centers of the opening surfaces 104a and 104b are deviated from the intersection C1.

Note that the center of the opening surface of the contact hole (the center of the opening surface) may be an intersection C2 of straight lines connecting the opposing vertices of the rectangle in the rectangular contact hole shown in FIG. In the case of a circular contact hole, the center of the opening surface may be the center of the circle of the opening surface.
In the present embodiment, the occupation area of the cell 101 is reduced by adopting a stack type in which the positions of the contact holes 103a and 103b are closer to the planar type. Then, the center of the opening surface of the contact holes 103a and 103b is deviated from the center of the stack type capacitor portion in plan view. With this configuration, the region in which the ferroelectric layer 109 is affected by contact hole or plug formation is reduced to reduce leakage current.

  In view of this object, in the present embodiment, it is desirable to open the contact hole 103a and the contact hole 103b so that the center of the opening surface is located on one straight line L. By making the centers of the opening surfaces of the contact holes 103a and 103b in a straight line, the damaged region is biased on the dielectric layer 109, and a region that functions normally as a memory can be sufficiently secured.

In addition, it is desirable that the capacitor portion 102 is formed in a rectangular shape in plan view, and a region that is not affected by contact hole or plug formation is sufficiently secured. In this case, it is desirable that the cell 101 is formed so that the long side of the rectangular capacitor unit 102 is about twice as long as the short side due to the conditions of the cell occupation area and the leakage current.
Further, in order to ensure a sufficient area not affected by contact hole and plug formation, it is desirable to provide the contact holes 103a and 103b outside a predetermined range including the center of the stacked capacitor portion. Furthermore, from the viewpoint of alignment margin, process characteristics, and the like, it is desirable that the contact holes 103a and 103b be opened in a range separated by a predetermined distance or more from the outer periphery of the stacked capacitor unit.

In view of the above, in this embodiment, the contact holes 103a and 103b are outside the area A1 including the intersection C1 and separated from the outer peripheral edge by a predetermined distance D as shown in FIG. It shall be provided in A2. Note that the value of D may be the minimum value of the design rule in the memory to which the present embodiment is applied, for example.
2A to 2C and FIGS. 3A to 3C are process diagrams for explaining a method of manufacturing the semiconductor device shown in FIG. The semiconductor device of this embodiment is manufactured by the method described below. First, in this embodiment, the SiO2 layer 119 contact hole 103a on the impurity layer 117 is opened. At this time, as described above, the contact hole 103a is opened at a position where the center of the opening surface is deviated from the center of the capacitor unit 102 in plan view.

Next, in the manufacturing method of the present embodiment, tungsten is embedded in the contact hole 103a, and the W plug 113 is formed. In forming the W plug 113, the upper surface 113a of the buried tungsten is sufficiently flattened by a technique such as CMP (Chemical Mechanical Polishing) (FIG. 2A).
Next, an Ir / IrOx / Pt composite film 111a is formed on the SiO2 layer 119 on which the W plug 113 is formed by a technique such as sputtering. In this embodiment, when forming the Ir / IrOx / Pt composite film 111a, a TiAlN film (not shown) is formed in advance to prevent tungsten oxidation.

  Next, a ferroelectric film 109a is formed on the Ir / IrOx / Pt composite film 111a by coating or the like, and further a Pt / IrOx / Ir composite film 107a is formed on the ferroelectric film 109a by sputtering or the like (FIG. 2 (b)). Then, a resist is applied onto the Pt / IrOx / Ir composite film 107a, and a resist mask that matches the shape of the cell is formed by photolithography. By dry etching from above the resist mask, the Ir / IrOx / Pt composite film 111a, the ferroelectric film 109a, and the Pt / IrOx / Ir composite film 107a are processed at a time to form the capacitor portion 102 (FIG. 2). (C)).

  Further, in the present embodiment, as shown in FIG. 3, the capacitor portion 102 is covered with a barrier film 115 (FIG. 3A), and a contact hole 103b is opened after providing a SiO 2 layer 118 (FIG. 3B). )). At this time, in this embodiment, the contact hole 103b is opened at a position where the center of the opening surface of the contact hole 103b coincides with the center of the opening surface of the contact hole 103a.

Further, the wiring 101 is formed by patterning a Ti / TiN film or an aluminum film generated by sputtering or the like on the contact hole 103b, whereby the cell 101 is completed.
FIG. 5 is a diagram for explaining the effect of the present embodiment described above, in which the horizontal axis indicates the value of the leakage current, and the vertical axis indicates the ratio of elements having each value of leakage current as a percentage. Distribution Z is shown. The leak current is a value when a voltage of 3 V is applied to the electrode.

Data d1 in FIG. 5 is data obtained by the ferroelectric memory of this embodiment shown in FIG. Data d2 is data obtained by the conventional stack type ferroelectric memory shown in FIG. The cell pattern shape of the ferroelectric memory of this embodiment is 2 μm on both the long side and the short side.
According to FIG. 5, 50% of the ferroelectric memory of the present embodiment has a leakage current of 2.2 μA / cm ² (indicated by I 1 in the figure) or less. On the other hand, in the conventional configuration, it can be seen that 50% of the ferroelectric memory has a leakage current of 2.8 μA / cm ² (indicated by I 2 in the figure) or less. Therefore, in this embodiment, it can be said that the leakage current of the 50% ferroelectric memory is reduced by nearly 30% compared to the conventional configuration.

  The present embodiment described above can provide a semiconductor device, a ferroelectric memory, and a method for manufacturing the semiconductor device that can reduce leakage current compared to a conventional stack type cell memory while being a stack type. According to the present embodiment, a semiconductor device, a ferroelectric memory, and a method of manufacturing a semiconductor device, which are miniaturized within an allowable range of leakage current, are finer than a conventional semiconductor device, and consume less current. Can be provided.

It is a figure for demonstrating the semiconductor device of one Embodiment of this invention. FIG. 6 is a process diagram for describing the manufacturing method of the semiconductor device shown in FIG. 1. FIG. 7 is another process diagram for explaining the method for manufacturing the semiconductor device shown in FIG. 1. It is the figure which illustrated other composition of the semiconductor device of one embodiment of the present invention. It is a figure for demonstrating the effect of one Embodiment of this invention. It is the figure which showed the memory of the conventional stack type cell.

Explanation of symbols

100 substrate, 101 cell, 102 capacitor part,
103a, 103b contact holes, 104a top surface, 104b bottom surface,
105 wiring, 107 upper electrode, 109 ferroelectric layer, 111 lower electrode,
113 W plug, 115 barrier film, 117 impurity layer, 118, 119 SiO2 layer 120 transistor.

Claims (8)

A stack type capacitor unit including a first electrode provided on the first insulating member, a power storage member provided on the first electrode, a second electrode provided on the power storage member;
A second insulating member provided on the second electrode and electrically insulating the second electrode and the wiring member;
A first contact hole that is opened on the first insulating member and in which a conductive member for electrically connecting the local conductive layer under the first insulating member and the first electrode is embedded;
A second contact hole that is opened on the second insulating member and electrically connects the second electrode and the wiring member;
The semiconductor device according to claim 1, wherein the first contact hole and the second contact hole are opened at a position where the center of the opening surface is deviated from the center of the stack type capacitor portion in plan view.   The stacked capacitor unit has a rectangular shape in plan view, and the first contact hole and the second contact hole are opened at a position where an opening surface center is deviated from a center point of the rectangular shape. The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein the stacked capacitor unit is rectangular in a plan view.   4. The semiconductor device according to claim 1, wherein the first contact hole and the second contact hole are arranged such that the centers of the opening surfaces thereof are aligned with each other. 5.   The first contact hole and the second contact hole are outside a predetermined range including the center of the stack type capacitor unit in plan view of the stack type capacitor unit, and are predetermined from the outer periphery of the stack type capacitor unit. 5. The semiconductor device according to claim 1, wherein the semiconductor device is opened in an opening range that is a range separated by a distance greater than or equal to a distance between the semiconductor device and the semiconductor device.   6. The semiconductor device according to claim 5, wherein a plurality of the first contact holes and the second contact holes are opened in the opening range.   A ferroelectric memory comprising the semiconductor device according to any one of claims 1 to 6. Forming a first contact hole in the first insulating member;
Filling the first contact hole with a conductive member to form a conductive plug;
Forming a first electrode layer on the conductive plug;
Providing a power storage member on an upper surface of the first electrode layer;
Providing a second electrode layer on the upper surface of the power storage member layer;
The first electrode layer, the power storage member, and the second electrode layer are processed by a single photolithography process. In the shape of the first electrode after processing, the center of the planar shape is the center of the first contact hole. Forming a stacked capacitor portion so as to deviate from the center of the opening surface;
Forming a second insulating member on the stacked capacitor unit;
Opening the second contact hole on the second insulating member so that the center of the opening surface is located at a position deviated from the center of the stack type capacitor unit in plan view of the stack type capacitor unit; ,
A method for manufacturing a semiconductor device, comprising:

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