JP2006011987A - Debugging system and debugging method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a secure debugging system capable of suppressing browsing of data within a processor by a third party other than a designer by controlling the communication of debugging information by authentication while realizing an easy debugging environment, and a debugging method thereof. <P>SOLUTION: This debugging system comprises an image processing device including a software debugging means debugging software and an emulation interface and mounted with at least one or more programmable processors; and a debugging information control terminal controlling the software debugging means so as to be operable only when the authentication with a processor is recognized. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a debugging system and a debugging method for an image forming apparatus such as a laser printer or an intelligent copying machine.

  Conventionally, in a general image forming apparatus such as a laser printer or an intelligent copying machine, a serviceman has upgraded the control program of the CPU in the apparatus by exchanging the ROM of the internal control board. However, the upgrade of the serviceman by exchanging ROM has a problem that the work is complicated. In particular, in recent years, it has been desired to simplify and facilitate version upgrade work by shortening the development of new products, shortening the life cycle of products, and diversifying the functions of devices.

  Therefore, Patent Document 1 uses an external storage means or an external computer using a rewritable nonvolatile storage means as a medium for storing a controller, an engine of an image forming apparatus, a CPU control program in an operation panel unit, and internal circuit information. A technique for facilitating version upgrade is disclosed.

Japanese Patent Laid-Open No. 2004-228867 discloses a connection between a host computer of a firmware debugging device that debugs a program of a digital signal control device (Digital Signal Processor (DSP)) having a programmable processor and a DSP that debugs a program. A technology related to data input / output is disclosed.
JP-A-6-314202 JP-A-7-262045

  However, in the technique disclosed in Patent Document 2 described above, in order to debug a program downloaded to a DSP, anyone who has a debugging device can freely access a third person other than the designer. There was a problem that the program could be leaked to the people.

  In view of the above problems, the present invention suppresses data browsing inside the processor by a third party other than the designer by controlling communication of debug information by authentication while realizing an easy debugging environment. It is an object of the present invention to provide a secure debugging system and a debugging method thereof.

  According to the first aspect of the present invention, there is provided an image processing apparatus including software debugging means for debugging software and an emulation interface, and at least one programmable processor, and the software debugging means is the processor. The debug system of the image processing apparatus is provided with a debug information control terminal that performs control for debugging software executed by.

  According to a second aspect of the present invention, the software debug means is stored in the hardware debug information, which is signal information inside the processor, and a program and data storage area inside the processor via the emulation interface. The debug system according to claim 1, wherein software for controlling software debug information is installed.

  According to a third aspect of the present invention, the software for controlling the hardware debug information and the software debug information is operable only when authentication with the processor is permitted. A debug system for the image processing apparatus described above is provided.

  The debugging information control terminal for debugging software executed by at least one or more programmable processors provided in the image processing apparatus includes an emulation interface provided in the image processing apparatus. And a debugging method for a debugging system of the image processing apparatus, wherein the software debugging means provided in the image processing apparatus includes a step of performing control for debugging the software executed by the processor. And

  According to a fifth aspect of the present invention, the debug information processing terminal is configured to control the software installed in the software debug means via the emulation interface, so that the hardware debug that is the processor internal signal information is controlled. 5. The debugging method for a debugging system of an image processing apparatus according to claim 4, further comprising a step of controlling information and software debugging information stored in a program and data storage area in the processor.

  The invention described in claim 6 comprises the step of enabling the software for controlling the hardware debug information and the software debug information to be operable only when authentication with the processor is permitted. The debugging method of the debugging system of the image processing apparatus according to 4 or 5 is characterized.

  According to the present invention, while realizing an easy debugging environment, it is possible to suppress the browsing of data inside the processor by a third party other than the designer by controlling the communication of debug information by authentication. Debugging system and debugging method thereof can be realized.

  In the best mode for carrying out the present invention, an image processing apparatus including at least one programmable processor provided with software debugging means for debugging software and an emulation interface, and authentication of the processor are provided. A debugging system is constituted by a debugging information control terminal that controls software debugging means that can operate only when it is approved.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the examples described below are preferred specific examples of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the following description. Unless otherwise described, the present invention is not limited to these examples.

  First, the outline of the debugging system of the present embodiment will be briefly described with reference to FIG. FIG. 1 is a diagram illustrating a debugging system according to the present embodiment. As shown in FIG. 1, the debug system according to the present exemplary embodiment includes an image processing apparatus 201 including an image processing board 202 and a debug information processing terminal 203. The image processing apparatus 201 is provided with an emulation interface, and the image processing board 202 is provided with one image processing processor of the present embodiment to be debugged and executed by the image processing processor. Software debugging means are provided for debugging the software to be executed.

Also, the debug information processing terminal 203 receives the software executed by the image processing processor mounted on the image processing board 202 via the emulation interface provided in the image processing apparatus 201 as the software debugging means. Control for debugging is performed.
Further, as will be described in detail later, in this embodiment, when debugging the software executed by the image processing processor using the debug information processing terminal 203, a third party other than the designer inside the processor. For the purpose of suppressing data browsing and providing a secure debugging system, the debugging system is such that a debugging operation is executed only when the user is authenticated.

  Next, the internal configuration and operation contents of the image processor in the image processing apparatus to which the present invention is applied will be described in detail with reference to FIG. FIG. 2 is a block diagram showing the configuration of the image processor according to this embodiment. As shown in FIG. 2, the image processor 101 of this embodiment includes a bus switch / local memory group (first storage unit) 102, a memory control unit 103, a processor array unit 104, a program RAM 105, and a data RAM 106. A host buffer 107 and an emulator interface 108.

  The image processor 1 of this embodiment includes a bus switch / local memory group (first storage unit) 102 so as to be connected to an input / output port, and a memory area to be used and a path of a data path are determined. Control is performed by the memory control unit 103. The input data and the data for output are assigned to the bus switch / local memory group 102 as a buffer memory, stored respectively, and controlled via an external interface.

The processor array unit (image processing unit) 104 performs various types of processing on the image data stored in the bus switch / local memory group 102, and outputs the output result (processed image data) again to the bus switch / Store in the local memory group 102. The processing means in the processor array unit 104, parameters for processing, and the like are between the program RAM 105 and the data RAM (second storage unit) 106 that can be referred to by the means for controlling the data processing of the processor array unit 104. Communicate with.
The contents of the program RAM 105 and the data RAM 106 are downloaded from the process controller to the host buffer (third storage unit) 107 via the serial I / F, and updated after timing control is performed from the host buffer 107.

The process controller reads the contents of the data RAM 106 read by the host buffer 107 under timing control, and monitors the progress of the processing.
In general, when the contents of processing are changed or the processing form required by the system is changed, the contents of the program RAM 105 and the data RAM 106 referred to by the processor array unit 104 are updated. Hardware debug information such as the state of the bus switch and the contents of the local memory, software debug information which is the contents of the program RAM 105 and the data RAM 106 which are changed as necessary and executed by the processor array unit 104, etc. Most information inside the processor can be monitored / controlled by the external emulator control unit 109 via the emulation interface 108.

  Next, a schematic configuration and functions of an image processing apparatus to which the present invention is applied will be described below with reference to FIG. FIG. 3 is a configuration block diagram functionally showing the configuration of the image processing apparatus in the present embodiment. As shown in FIG. 3, the image processing apparatus according to the present embodiment includes an image data control unit 121, an image reading unit 122 that reads image data, and an image memory that stores and stores image data. The memory control unit 123 includes an image processing unit 124 that performs image processing such as processing / editing on the image data, and an image writing unit 125 that writes the image data on a transfer sheet or the like.

Each of the units is configured with an image data control unit 121 as the center, and the image reading unit 122, the image memory control unit 123, the image processing unit 124, and the image writing unit 125 are all included in the image data control unit 121. It is connected.
The processing performed by the image data control unit 121 includes the following. Data compression processing (primary compression) to improve data bus transfer efficiency, primary compressed data transfer processing to image data, image composition processing (compositing image data from multiple units), image shift processing (main scanning) And image shift in the sub-scanning direction), image area expansion processing (addition of an arbitrary amount of images in the main scanning and sub-scanning directions), parallel bus interface processing, serial bus interface processing, parallel data and serial data formats Conversion processing, interface processing with the image reading unit, interface processing of the image processing unit, and the like.

The processes performed by the image reading unit 122 include the following.
Document reflected light reading process by optical system, conversion process to electric signal by CCD (Charge Coupled Device), digitization process by A / D converter, shading correction process (irradiance distribution unevenness of light source is reduced) Correction processing), scanner γ correction processing (processing for correcting density characteristics of the reading system), and the like.

  The processing performed by the image memory control unit 123 includes the following. Interface control processing with system controller, parallel bus control processing, jet work control processing, serial bus control processing (control processing for multiple external serial ports), internal bus interface control processing (command control processing with operation unit), local bus Control processing (ROM / RAM font data access control to activate the system controller), memory module operation control processing (memory module write / read control processing, etc.), memory module operation control processing (from multiple units) Processing for arbitrating memory access requests), data compression / decompression processing, image editing processing (rotation of image data, image composition processing on memory, etc.), and the like.

The processes performed by the image processing unit 124 include the following.
Shading correction processing (processing for correcting illuminance distribution unevenness of the light source), scanner γ correction processing (processing for correcting density characteristics of the reading system), MTF correction processing, smoothing processing, arbitrary scaling processing in the main scanning direction, density Conversion (γ conversion processing), simple multi-value processing, simple binarization processing, error diffusion processing, dither processing, dot placement phase control processing, isolated point removal processing, image area separation processing (color determination, attribute determination, adaptive processing) ), Density conversion processing, and the like.
The processing performed by the image writing unit 125 includes the following.
These include edge smoothing processing (jaggy correction processing), dot rearrangement correction processing, image signal pulse control processing, parallel data and serial data format conversion processing, and the like.

  Next, a hardware configuration when the image processing apparatus according to the present embodiment constitutes a digital copying machine will be described. FIG. 4 is a block diagram illustrating the hardware configuration of the image processing apparatus according to the present exemplary embodiment. As shown in FIG. 4, the image processing apparatus of this embodiment includes a reading unit 131, a sensor board unit 132, an image data control unit 133, an image processing processor 134, a video data control unit 135, and an image forming unit (engine). 136. Furthermore, as shown in FIG. 4, the image processing apparatus according to the present exemplary embodiment includes a process controller 138, a RAM 139, and a ROM 140 via a serial bus 137.

  Among the above-described configurations, the image processor 134 is a programmable image processing unit that can process a plurality of image forming operations by processing image data, which is a digital signal created based on an image, so as to be output as a visible image. . The image data control unit 133 is an image data transmission management unit that collectively manages transmission of image data between a data bus for transmitting image data and a processing unit used for image processing by the image processor 134. .

  As shown in FIG. 4, the image processing apparatus according to the present embodiment includes an image memory / access control unit 143 and a facsimile control unit 141 via a parallel bus 144, and further includes an image memory / access control unit 143. A memory module 142, an operation panel 145, a ROM 146, a RAM 147, and a system controller 148 are provided. In such a configuration, the memory module 142 and the image memory access control unit 143 are image data storage management units that collectively manage access of image data to the ROM 146 and the RAM 147.

  Here, the relationship between each component in the image processing apparatus of this embodiment shown in FIG. 4 and each unit in the image processing apparatus of this embodiment shown in FIG. 3 will be described. The functions of the image reading unit 122 shown in FIG. 3 are realized by the reading unit 131 and the sensor board unit 132 shown in FIG. Similarly, the function of the image data control unit 121 shown in FIG. 3 is realized by the image data control unit 133 shown in FIG. Similarly, the function of the image processing unit 124 shown in FIG. 3 is realized by the image processor 134 shown in FIG. Similarly, the video data control unit 135 and the image forming unit (engine) 136 shown in FIG. 4 implement the functions of the image writing unit 125 shown in FIG. Similarly, the function of the image memory control unit 123 shown in FIG. 3 is realized by the image memory / access control unit 143 and the memory module 142 shown in FIG.

  Next, the operation content of each component in the image processing apparatus of this embodiment shown in FIG. 4 will be described in detail. A reading unit 131 that optically reads an original shown in FIG. 4 includes a lamp, a mirror, and a lens, and collects reflected light of lamp irradiation on the original with a light receiving element using the mirror and the lens. A light receiving element, for example, a CCD is mounted on the sensor board unit 132, and image data converted into an electric signal in the CCD is converted into a digital signal and then output from the sensor board unit 132. The image data output from the sensor board unit 132 is input to the image data control unit 133. The image data control unit 133 controls all image data transmission between the functional device (processing unit) and the data bus.

The image data control unit 133 shown in FIG. 4 is responsible for overall control of the process controller 138 and the image processing apparatus for image data, data transfer between the sensor board unit 132, the parallel bus 144, and the image processor 134 with respect to the image data. Communication with the system controller 148 is performed.
4 is used as a work area for the process controller 138, and the ROM 140 shown in FIG. 4 stores a boot program for the process controller 138 and the like. The image data output from the sensor board unit 132 is transferred to the image processor 134 via the image data control unit 133, and signal deterioration due to quantization into an optical system and a digital signal (scanner signal deterioration). ) Is corrected and output to the image data control unit 133 again.

  The image memory access control unit 143 shown in FIG. 4 controls writing / reading of image data to / from the memory module 142. Also, the operation of each component connected to the parallel bus 144 is controlled. 4 stores a boot program of the system controller 148 and the like. An operation panel 145 shown in FIG. 4 inputs processing to be performed by the image processing apparatus. For example, the processing type (copying, facsimile transmission, image reading, printing, etc.), the number of processings, and the like are input. Thereby, the image data control information can be input. The contents of the facsimile control unit 141 will be described later.

  Next, the read image data includes a job that is stored in the memory module 142 and reused, and a job that is not stored in the memory module 142. Each case will be described. As an example of accumulating in the memory module 142, when a plurality of sheets are copied for one original, the reading unit 131 shown in FIG. 4 is operated only once, and image data read by the reading unit 131 is stored in the memory module 142. There is a method of accumulating and reading the accumulated image data a plurality of times.

  Further, as an example in which the memory module 142 shown in FIG. 4 is not used, when only one original is copied, the read image data may be reproduced as it is, so that the memory module 142 is controlled by the image memory access control. There is no need to access. When the memory module 142 is not used, the data transferred from the image processor 134 shown in FIG. 4 to the image data controller 133 is returned from the image data controller 133 to the image processor 134 again. The image processor 134 performs image quality processing for converting luminance data from the CCD in the sensor board unit 132 into area gradation. The image data after the image quality processing is transferred from the image processor 134 to the video data control unit 135. Post processing relating to dot arrangement and pulse control for reproducing the dots are performed on the signal changed to the area gradation, and then a reproduced image is formed on the transfer paper in the image forming unit 136.

  Next, the flow of image data in the case where additional processing, for example, rotation in the image direction, image composition, etc., is performed when reading out the image stored in the memory module 142 will be described with reference to FIG. The image data transferred from the image processor 134 shown in FIG. 4 to the image data control unit 133 is sent from the image data control unit 133 to the image memory access control unit 143 via the parallel bus 144. Here, based on the control of the system controller 148, the access control of the image data and the memory module 142, the expansion of the print data of the external PC (personal / computer) 149, the compression / image data for effective use of the memory module 142 Perform stretching.

  The image data sent to the image memory access control unit 143 is stored in the memory module 142 after data compression, and the stored image data is read out as necessary. The read image data is expanded, returned to the original image data, and returned from the image memory access control unit 143 to the image data control unit 133 via the parallel bus 144. After transfer from the image data control unit 133 to the image processing processor 134, image quality processing and pulse control in the video data control unit 135 are performed, and a reconstructed image is formed on the transfer paper in the image forming unit 136.

  In the flow of image data, the functions of the digital copying machine are realized by bus control in the parallel bus 144 and the image data control unit 133. In the facsimile transmission function, the read image data is subjected to image processing by the image processor 134 and transferred to the facsimile control unit 141 via the image data control unit 133 and the parallel bus 144. The facsimile control unit 141 performs data conversion to a communication network and transmits the data to the public line (PN) 50 as facsimile data.

  On the other hand, in the transmitted facsimile data, line data from the public line (PN) 50 shown in FIG. 4 is converted into image data by the facsimile control unit 141, and the image data is transmitted via the parallel bus 144 and the image data control unit 133. Transferred to the processor 134. In this case, no special image processing is performed, the video data control unit 135 performs dot rearrangement and pulse control, and the image forming unit 136 forms a reproduced image on the transfer paper. In a situation where a plurality of jobs, for example, a copy function, a facsimile transmission / reception function, and a printer output function operate in parallel, the system controller allocates the right to use the reading unit 131, the image forming unit 136, and the parallel bus 144 shown in FIG. 148 and process controller 138.

The process controller 138 shown in FIG. 4 controls the flow of image data, and the system controller 148 controls the entire system and manages the activation of each resource. The function selection of the digital multi-function peripheral is selected and input on the operation panel (operation unit) 145, and processing contents such as a copy function and a facsimile function are set.
The system controller 148 and the process controller 138 communicate with each other via the parallel bus 144, the image data control unit 133, and the serial bus 137. Specifically, communication between the system controller 148 and the process controller 138 is performed by performing data format conversion for the data interface between the parallel bus 144 and the serial bus 137 in the image data control unit 133.

  By the way, as described above, the debugging system according to the present embodiment uses the debugging information processing terminal 203 to debug software executed by the image processor when the user is authenticated. The system is configured such that only the debugging operation is executed. The operation and contents of the authentication method will be described below with reference to FIGS.

First, the contents of the startup operation of the image processor (image processing apparatus) of this embodiment and the authentication code storage method will be described below with reference to FIG. FIG. 5 is a flowchart for explaining the authentication code storing method by the image processor of this embodiment.
As shown in FIG. 5, when the power of the image processing apparatus is turned on in step 101, the image processing processor enters a boot standby state (step 102).
Next, the process controller downloads the boot program to the program RAM via the image processor host interface (step 103), and then the process controller loads the image processor host interface. Then, the authentication code input by the user is written (step 104).

As described above, in this embodiment, the authentication code for a predetermined address is stored in the boot program used for starting the image processing processor in step 104. If the authentication code is stored in the boot program in advance as described above, the authentication code can be provided inside the processor after the boot of the processor is completed.
Subsequently, in step 105, when an image processor activation trigger is applied, the image processor starts operation according to the downloaded boot program (step 106). The boot program mainly includes initial settings of hardware such as bus switch settings, allocation of local memory groups to buffer memories, programs for monitoring received data, and startup thereof.

Subsequently, in step 107, when the booting operation of the processor is completed, the program / data is downloaded to the program RAM and data RAM in the processor by the process controller as necessary, and various image processing operations are performed. Realize the function. For example, when a copy operation is selected by the user in the image processing apparatus, a series of image processing such as black correction → shading correction → scanner γ processing → magnification processing → filter processing → printer γ processing → tone processing is realized. Download each program and data.
Alternatively, program downloading, data reading, and writing are performed without using a process controller from control software installed in a debug information control terminal (PC) connected to the emulation interface.

Next, the authentication method of the present embodiment will be described mainly using FIG. FIG. 6 is a flowchart showing the authentication operation of the image processor and control software of this embodiment.
In this embodiment, after the boot operation of the processor, as shown in FIG. 6, when the control software installed in the debug information control terminal (PC) is started (step 201), the authentication code is sent to the user. Input is performed (steps 202 to 203). In step 104 shown in FIG. 5 described above, the authentication code in the processor read through the emulation interface is collated with the authentication code input by the user in step 203 by user input. Only when they match, communication with the image processor is continued and control from the control software is enabled (steps 204 to 205). If they do not match, the communication with the image processor is interrupted and the control software is terminated (step 204, step 206, step 207).

Control of the processor via the emulation interface is mainly for debugging purposes, such as function confirmation when a new function is added by a program designer or a person in charge of debugging, and operation confirmation whether downloading to a desired address is performed correctly. Used. However, other than the program designer or the person in charge of debugging, all persons who own the debug information control terminal can monitor / control all the information inside the processor, so the malicious third party wrote the information inside the processor. There is a possibility that information such as an image processing algorithm may be leaked by analyzing the program.
However, by performing authentication as in the above-described embodiment, access to the inside of the processor can be suppressed. Further, since the designer can arbitrarily update the authentication code, higher reliability can be obtained by changing the authentication code depending on the model to be debugged or each version.

  Next, the configuration and function of the image forming apparatus to which this embodiment is applied will be described below with reference to FIG. As shown in FIG. 7, the image forming apparatus is supplied from an external device via a copying function for copying a document image, a facsimile function for transmitting / receiving image data via a communication line, and an external I / F, for example. An image forming apparatus having a printer function for printing based on image data, that is, a composite digital image forming apparatus (hereinafter abbreviated as an image forming apparatus) is configured.

  FIG. 7 is a sectional view schematically showing the internal structure of the image forming apparatus. As shown in FIG. 7, an image forming apparatus to which the present embodiment is applied, for example, an electrophotographic digital image forming apparatus 50, includes an image reading unit that functions as a reading unit that reads a document image and generates image data. That is, it has a scanner unit 50a and an image forming unit that functions as an image forming unit that forms an image based on image data, that is, a printer unit 50b. Further, the image forming apparatus 50 includes an automatic document feeder 51 as a conveying unit above the scanner unit 50a. The image forming apparatus 50 is formed so as to be openable and closable with respect to a later-described document table or document table of the scanner unit 50a. The document D as an object is fed one by one toward the document table, and functions as a document pressing unit for bringing the document D placed on the document table into close contact with the document table.

  The scanner unit 50 a is disposed at the top of the document table 52 made of transparent glass, facing the automatic document feeder 51 in a closed state and on which the document D is set, and one end of the document table 52. A document scale 53 indicating the position where the document D should be set on the document table 52 is also provided.

  Below the document table 52, an exposure lamp 54 that illuminates the document D placed on the document table 52, an auxiliary reflector 58 for condensing the light beam from the exposure lamp 54 on the document D, and the document D A first mirror 56 that bends the reflected beam from the left side in the figure is arranged. The exposure lamp 54, the auxiliary reflecting plate 58, and the first mirror 56 are fixed to the first carriage 57, and are arranged to be movable in parallel with the document table 52 as the first carriage 57 moves. The first carriage 57 is moved in parallel along the document table 52 by receiving a driving force of a pulse motor (not shown) via a toothed belt (not shown).

  A second carriage 59 is disposed on the left side of the document table 52 in the drawing, that is, in the direction in which the reflected beam reflected by the first mirror 56 is guided. In the second carriage 59, a second mirror 60 for bending the reflected beam from the document D guided by the first mirror 56 downward and a third mirror 61 for bending rightward in the drawing are arranged at right angles to each other. The second carriage 59 is driven by the first carriage 57 by a toothed belt (not shown) that drives the first carriage 57 and parallel to the first carriage 57 along the document table 52 at a speed of 1/2. Moved to.

  An imaging lens that forms an image of the reflected beam from the second carriage 59 at a predetermined magnification in a plane below the first carriage 57 and including the optical axis of the beam folded back through the second carriage 59. 62, and a line sensor 63 including a plurality of CCD image sensors for converting the reflected beam, which is focused by the imaging lens 62, into an electrical signal, that is, image data.

  Here, the direction in which the plurality of CCD image sensors in the line sensor 63 are arranged is the main scanning direction, and the direction in which the first carriage 57 and the second carriage 59 move is the sub-scanning direction. In the present embodiment, the reading device portion is a sheet-through type image reading system in which the scanner unit 50a is fixed and the automatic document feeder 51 reads an image while conveying the document.

  Next, the printer unit 50b will be described. The printer unit 50 b includes a photosensitive drum 12, a charging charger 13, developing units 14 and 15, a static elimination lamp (PTL) 17, a transfer charger 18, a separation charger 19, an eraser 20, a cleaning unit 21, It has a polygon mirror (laser light generator) 22 and an optical system (lens) 23, and performs image formation and output of image data stored in an image memory.

  That is, at the same time as the photosensitive drum 12 is rotated in the direction of the arrow, the residual toner and non-uniform potential adhering to the photosensitive drum 12 do not reach the charging charger 13 and the developing units 14 and 15, so QL) 16, a pre-transfer static elimination lamp (PTL) 17, a transfer charger 18, a separation charger 19, an eraser 20, and a cleaning unit 21, and the surface potential of the photosensitive drum 12 after passing through the static elimination lamp 16 is substantially equal. Try to be zero.

  Thereafter, the surface of the photosensitive drum 12 is uniformly charged by the charging charger 13, the image data stored in the image memory is read, and a laser beam is emitted from a semiconductor laser (not shown) accordingly. Laser light emitted from the semiconductor laser is incident on a polygon mirror (laser light generator) 22 that is condensed and rotated by a cylinder lens (not shown), and reflected light passes through an optical system (lens) 23 and a mirror 24. The surface of the photosensitive drum 12 is irradiated to form an electrostatic latent image.

  Next, the latent image formed on the photoconductive drum 12 is subjected to black developing unit 14 or a color developing unit that develops the black toner after removing the charges of the non-image part (unnecessary part protruding from the image forming area) by the eraser 20. The color developing unit 15 that performs development with toner attaches toner to form a visible image. At this time, the density of the image can be adjusted by changing the developing bias potential.

  On the other hand, one of the calling roller 25 and the three paper supply rollers 26 is driven by turning on a paper supply clutch that can selectively take out the drive of a main motor (not shown) to a preselected paper supply stage (described later). The set recording paper is fed toward the stopped registration roller pair 27. A registration sensor 28 is disposed in front of the registration roller pair 27. The registration sensor 28 is, for example, a reflection type photosensor, and is turned on when the leading edge of the recording paper reaches the opposite position. Then, after a predetermined time has elapsed, the paper feeding clutch is returned to the OFF state, and the recording paper being conveyed is stopped.

  The timing for turning off the paper feed clutch is set longer than the time during which the recording paper is conveyed between the registration sensor 28 and the registration roller pair 27. Accordingly, the leading edge of the recording paper is abutted against the pair of registration rollers 27, and the recording paper stands by in a state where the leading edge is bent to prevent skew and the like. Thereafter, the registration clutch is turned ON at a timing in accordance with the leading edge of the image on the photosensitive drum 12, and the registration roller pair 27 is driven to rotate, whereby the standby recording paper is conveyed again toward the transfer unit. .

  When the recording paper reaches the transfer portion, the toner image on the photosensitive drum 12 is transferred onto the paper surface by the action of the transfer charger 18, and then on the paper surface by the action of the separation charger 19 held integrally with the transfer charger 18. Then, the recording paper is separated from the surface of the photosensitive member by the separation claw 29.

  Next, the recording paper is fed to the fixing unit by the conveying belt 30 stretched by two rollers, and the toner image is thermally fixed by the fixing roller 31. After that, if the single-side mode is selected as the copy mode, the switching claw 32 By switching, the sheet is fed into the lower sheet refeeding conveyance path 33.

  The residual toner on the photosensitive drum 12 after the image transfer is removed by the cleaning brush 21a and the cleaning blade 21b constituting the cleaning unit 21 and recovered in the toner recovery tank 21c. The surface is exposed to the front by the charge eliminating lamp 16.

  By the way, this copying machine is detachably equipped with three paper feed cassettes 34 to 36 in which recording papers of different sizes are set as ordinary paper feed cassettes capable of storing only recording papers of a specific size. Also provided is a manual feed table (manual feed tray) 37 on which recording paper that is not stored in any paper feed cassette, that is, recording paper of an unspecified size can be set.

  When copying using recording paper stored in any of the paper cassettes 34 to 36, the cassette size is selected by a size selection key on an operation panel (not shown), and then the copy start key is pressed. Thus, the recording paper is fed from the paper feed cassette.

  Reference numerals 38a to 38c denote size detection sensors for detecting the size of each storage sheet in each of the paper feed cassettes 34 to 36. For example, five photo interrupters are used. In addition, a light-shielding plate for size identification (not shown) is attached to the front end of each of the paper feed cassettes 34 to 36. The light shielding plate has a notch that varies depending on the size of the recording paper to be stored in the cassette.

  When the paper feed cassettes 34 to 36 are mounted, the size detection sensors 38a to 38c are configured so that only the photo interrupter sandwiching the light shielding portion of the light shielding plate blocks the optical path. Can be output. The control unit is a CPU or the like. On the other hand, when copying using recording paper of an unspecified size, the manual feed table 37 is opened from the closed state indicated by the phantom line in the direction indicated by arrow A to the use state indicated by the solid line, and then the desired surface is displayed on the upper surface. By setting the recording paper and pressing the copy start key, the recording paper is fed from the manual feed table 37.

  When the manual feed table 37 is rotated in the opening direction, the bottom plate raising arm 39 that has lifted the recording paper placement bottom plate provided in the first paper feed cassette 34 is lowered in conjunction therewith. An open / close detection sensor (not shown) for detecting opening / closing of the manual feed table 37 is installed at a position facing the manual feed table 37 of the copying machine.

It is the figure which showed the debugging system of a present Example. It is a block diagram of the configuration of the image processor of the present embodiment. 1 is a configuration block diagram of an image processing apparatus according to an embodiment. It is a hardware configuration block diagram of the image processing apparatus of the present embodiment. It is a flowchart for demonstrating the authentication code storage method by the image processor of a present Example. It is a flowchart which shows the authentication operation | movement of the image processor and control software of a present Example. 1 is a configuration cross-sectional view of an image processing apparatus to which the present invention is applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Image processor 102 Bus switch local memory group 103 Memory control part 104 Processor array part 105 Program RAM
106 Data RAM
107 Host Buffer 108 Emulator Interface 109 External Emulator Control Unit 121 Image Data Control Unit 122 Image Reading Unit 123 Image Memory Control Unit 124 Image Processing Unit 125 Image Writing Unit 131 Reading Unit 132 Sensor Board Unit 133 Image Data Control Unit 134 Image Processing Processor 135 Video data control unit 136 Image forming unit (engine)
137 Serial bus 138 Process controller 139 RAM
140 ROM
141 Facsimile Control Unit 142 Memory Module 143 Image Memory Access Control Unit 144 Parallel Bus 145 Operation Panel 146 ROM
147 RAM
148 System Controller 149 PC
150 Public Line 201 Image Processing Device 202 Image Processing Board 203 Debug Information Processing Terminal

Claims (6)

An image processing apparatus including software debugging means for debugging software and an emulation interface, and at least one programmable processor mounted thereon;
A debug information control terminal for controlling the software debug means to debug software executed by the processor;
A debugging system for an image processing apparatus, comprising: The software debugging means includes:
Software for controlling hardware debug information, which is signal information inside the processor, and software debug information stored in a program and data storage area inside the processor, is implemented via the emulation interface. The debugging system according to claim 1.   3. The image according to claim 1, wherein the software for controlling the hardware debug information and the software debug information is operable only when authentication with the processor is permitted. Debugging system for processing equipment.   A debug information control terminal for debugging software executed by at least one programmable processor provided in the image processing apparatus is connected to the image processing apparatus via an emulation interface provided in the image processing apparatus. A debugging method for a debugging system of an image processing apparatus, comprising: a step in which a provided software debugging means performs control for debugging software executed by the processor.   The debug information processing terminal controls the software installed in the software debug means via the emulation interface, thereby enabling hardware debug information which is signal information inside the processor and a program inside the processor. 5. The debugging method for a debugging system of an image processing apparatus according to claim 4, further comprising a step of controlling software debugging information stored in the data storage area.   6. The software for controlling the hardware debug information and the software debug information comprises a step of enabling operation only when authentication with the processor is permitted. A debugging method of a debugging system for an image processing apparatus according to claim 1.

Images