JP2006011095A - Driver means for display panel and image display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent luminance unevenness and to save space in an image display apparatus. <P>SOLUTION: The apparatus comprises; a display panel 10 in which pixel circuits 10G1(1) to 10Gk(s) having an organic EL element, are arranged in a matrix form; power lines p(1) and p(2) which are connected to the pixel circuits 10G1(1) to 10Gk(s) respectively and in which signals for power supply and for light emitting control are transmitted; a first control line x1(1), a second control line x2(1) and a third control line x3(1) which are connected to the pixel circuits 10G1(1) to 10Gk(s) respectively and in which a signal for controlling light emitting is transmitted; and a pair of gate drivers 30R1 and 30L1 which are provided at both sides of the display panel 10 and which are connected to both power lines p(1) and p(2) and also, connected to the first control line x1(1), the second control line x2(1) and the third control line x3(1) by allocation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display panel driver means and an image display device using, for example, an organic EL (Electronic Luminescent) element, and in particular, for a display panel capable of preventing uneven brightness and saving space. The present invention relates to driver means and an image display device.

  As mobile computing has become popular, demand for flat display devices has increased. Conventionally, a liquid crystal display device is generally used as a flat display device. However, the liquid crystal display device has problems such as a narrow viewing angle and poor response characteristics.

  On the other hand, in recent years, an image display device using an organic EL element has attracted attention as a flat-type image display device having a wide viewing angle and good response characteristics. This organic EL element has a function of generating light by recombination of holes and electrons injected into the light emitting layer.

  Such an image display device includes, for example, a plurality of pixel circuits arranged in a matrix, a signal line driving circuit that supplies a luminance signal described later to the plurality of pixel circuits via a plurality of signal lines, and a pixel circuit On the other hand, a scanning line driving circuit that supplies a scanning signal for selecting a pixel circuit that supplies a luminance signal via a plurality of scanning lines is provided.

  FIG. 8 is a block diagram showing a configuration of a conventional image display apparatus. The image display apparatus shown in FIG. 1 includes an organic EL panel 1, a controller 2, a gate driver 3, a drain driver 4, and a common driver 5. The pixel circuit in the organic EL panel 1 is composed of an organic EL element 6, a driving transistor 7, a selection transistor 8, and a capacitor Cp as shown in the equivalent circuit diagram of FIG. It is arranged.

  The organic EL element 6 is a light emitting element that emits light when a voltage equal to or higher than a threshold is applied between the anode and the cathode. When a voltage equal to or higher than the threshold value is applied between the anode and the cathode of the organic EL element 6, a current flows through the organic EL layer, and the organic EL element 6 emits light. The anode of the organic EL element 6 is connected to a common line CL provided for each row (the horizontal direction in the figure) of the organic EL panel 1.

  The driving transistor 7 is composed of an n-channel TFT (thin film transistor). The gate of the driving transistor 7 is connected to the source of the selection transistor 8. The drain of the driving transistor 7 is connected to the cathode electrode of the organic EL element 6. The source of the driving transistor 7 is grounded (0 V).

  The driving transistor 7 is used as a switch for turning on / off the power supplied to the organic EL element 6. The gate of the driving transistor 7 holds a driving signal supplied from a drain driver 4 described later.

  When a common signal is applied to the organic EL element 6 from the common driver 5 described later, the driving transistor 7 has an on-resistance that is sufficiently smaller than the resistance of the organic EL element 6 (for example, 1/10 or less), and the off-resistance Is sufficiently larger than the resistance of the organic EL element 6 (for example, 10 times or more). For this reason, when the driving transistor 7 is on, most of the voltage output from the common driver 5 is divided into the organic EL element 6, and the organic EL element regardless of variations in characteristics of the driving transistor 7. 6 emits substantially the same amount of light.

  On the other hand, when the driving transistor 7 is off, most of the voltage output from the common driver 5 is divided between the source and drain of the driving transistor 7 and a voltage equal to or higher than the threshold is applied to the organic EL element 6. The organic EL element 6 does not emit light.

  The selection transistor 8 is composed of an n-channel TFT. The selection transistor 8 has a gate line GL provided for each row (the horizontal direction in the figure) of the organic EL panel 1, and a drain line provided for each column (the vertical direction in the figure) of the organic EL panel 1. Connected to DL. The source is connected to the gate of the driving transistor 7. The selection transistor 8 is used as a switch for turning on / off the supply of a drive signal from a drain driver 4 described later to the gate of the drive transistor 7.

  The capacitor Cp holds a drive signal supplied from a drain driver 4 described later for at least one subfield period. The drive signal held by the capacitor Cp is used to turn the drive transistor 7 on and off, and the capacitor Cp and the drive transistor 7 form a switch for causing the organic EL element 6 to emit light.

  The gate driver 3 outputs selection signals X1 to Xn according to the gate control signal GCONT supplied from the controller 2. Only one of the selection signals X1 to Xn becomes active at the same timing, and any one of the gate lines GL of the organic EL panel 1 is selected. As a result, the selection signals X1 to Xn are applied to the gate of the selection transistor 8 connected to the selected gate line GL, and the selection transistor 8 is turned on.

  The drain driver 4 includes a shift register, a latch circuit, and a level conversion circuit. In the shift register, 1 (high level signal) is set to the first bit by the start signal in the drain control signal DCONT supplied from the controller 2, and every time the shift signal in the drain control signal DCONT is supplied, a bit shift is performed. I will do it.

  The latch circuit is composed of a number of latch circuits corresponding to the number of bits of the shift register, and latches the light emission signal IMG supplied from the controller 2 in the latch circuit corresponding to the bit which is 1 of the shift register. When the light emission signal IMG for one row in one subfield is latched by the latch circuit, the light emission signal IMG is latched by the latch circuit at the next stage according to the switching signal in the drain control signal DCONT. The latch circuit latches the light emission signal IMG in the next row.

  The level conversion circuit applies drive signals Y1 to Yn of a predetermined voltage level to the drain line DL of the organic EL panel 1 according to the light emission signal IMG latched in the latch circuit based on the output enable signal in the drain control signal DCONT. Output. The drive signals Y1 to Yn output from the level conversion circuit are accumulated in the gate of the drive transistor 7, and turn on the drive transistor 7.

  The common driver 5 generates common signals Z1 to Zn to be applied to the anode electrode of the organic EL element 6 based on the common control signal CCONT supplied from the controller 2. These common signals Z1 to Zn are on / off binary values, and are applied to the anode electrode of the organic EL element 6 for each row via the common line CL. This applied ON voltage is sufficiently larger than the threshold voltage of the organic EL element 6.

  Here, the common signals Z1 to Zn are power supply voltages supplied to the organic EL element 6, and have a higher voltage level than the selection signals X1 to Xn and the drive signals Y1 to Yn described above. Therefore, when the line is determined by the voltage level, it can be said that the common line CL is a power supply line, whereas the gate line GL and the drain line DL are control lines.

  When the driving transistor 7 is turned on, a voltage at which the light emission luminance of the organic EL element 6 is saturated is applied between the anode electrode and the cathode electrode of the organic EL element 6. On the other hand, as for the voltage applied between the anode electrode and the cathode electrode of the organic EL element 6 when the driving transistor 7 is turned off, most of the voltages of the common signals Z1 to Zn are divided by the driving transistor 7. Therefore, it becomes smaller than the threshold voltage of the organic EL element 6.

  Here, each of the gate driver 3, the drain driver 4, and the common driver 5 is provided with a plurality of pads (corresponding to terminals) corresponding to the gate line GL, the drain line DL, and the common line CL. Each pad is electrically connected to the corresponding gate line GL, drain line DL, and common line CL.

  Also, a larger current flows through the common line CL as the power supply line than the gate line GL and the drain line DL as the control lines. Thus, the pad of the common driver 5 (to which the power supply line is connected) has a larger area than the pads of the gate driver 3 and the drain driver 4 (to which the control line is connected) in order to reduce the influence of a large current. It needs to be bigger.

Japanese Patent Laid-Open No. 10-333641

  By the way, in the conventional image display apparatus, as the organic EL panel 1 is increased in size, each wiring such as the common line CL, the gate line GL, and the drain line DL becomes longer, and the wiring resistance increases. In particular, in the case of the common line CL as the power supply line, the voltage level of the common signals Z1 to Zn is high, so that the voltage drop is larger than that of the gate line GL and the drain line DL as the control lines. Therefore, in the conventional image display device, the variation in the voltage (voltage level of the common signal) supplied to each organic EL element 6 increases due to the difference in the length (voltage drop) of the common line CL from the common driver 5. There was a problem of uneven brightness.

  That is, in the case of the organic EL element 6 close to the common driver 5, since the common line CL from the common driver 5 to the organic EL element 6 is short, the voltage drop is small, a predetermined voltage is supplied, and a predetermined luminance is generated at the time of light emission. Is obtained. On the other hand, in the case of the organic EL element 6 far from the common driver 5, since the common line CL from the common driver 5 to the organic EL element 6 is long, the voltage drop is large and only a low voltage is supplied. A decrease in luminance occurs.

  Further, in the conventional image display device, there are as many as three drivers, that is, the gate driver 3 and the drain driver 4 related to the control lines (gate line GL, drain line DL) and the common driver 5 related to the power supply line (common line CL). Since these are arranged independently, there is also a problem that the need for space saving cannot be met.

  The present invention has been made in view of the above, and an object of the present invention is to provide a display panel driver unit and an image display device that can prevent luminance unevenness and save space.

  In order to solve the above-described problems and achieve the object, according to the present invention, a display panel driver means for driving a display panel having a light emitting element transmits a control signal for light emission control of the light emitting element. A control pad electrically connected to the control line, and a power pad electrically connected to a power line for supplying power to the light emitting element and having a larger area than the control pad, The control pads and the power supply pads are mixed and arranged in a line, and the arrangement order of the control pads and the power supply pads is symmetric in the arrangement direction of the pads. And

  The present invention also provides a control pad electrically connected to a control line through which a control signal for light emission control of the light emitting element is transmitted, in a display panel driver means for driving a display panel having a light emitting element. A preliminary control pad having the same shape as the control pad, a power supply pad electrically connected to a power supply line for supplying power to the light emitting element, and having a larger area than the control pad, The control pad, the preliminary control pad, and the power supply pad are mixed and arranged in a line, and the control pad and the preliminary control pad are regarded as the same type of pads. In some cases, the arrangement order of the control pads and the power supply pads is symmetric with respect to the arrangement direction of the pads.

  In addition, the present invention provides a display panel in which a plurality of pixel circuits each having a light emitting element that emits light by current injection are arranged in a matrix, and a power source for power supply and light emission control connected to the plurality of pixel circuits, respectively. A power supply line to which a control signal is transmitted; a plurality of control lines connected to the plurality of pixel circuits, respectively, to which a control signal for light emission control is transmitted; and provided on both sides of the display panel; And a pair of driver means for driving the plurality of pixel circuits by the power supply control signal and the control signal.

  According to the present invention, the control pads and the power supply pads are mixed and arranged in a line, and the arrangement order of the control pads and the power supply pads is symmetrical in the arrangement direction of the pads. Therefore, a pair of display driver means can be arranged on both sides of the display panel, and the power supply line can be connected to the power supply pads on both sides, reducing the voltage drop in the power supply line, preventing uneven brightness and saving space. There is an effect that can be achieved.

  Further, according to the present invention, the control pad, the preliminary control pad, and the power supply pad are mixedly arranged in a line, and the control pad and the preliminary control pad are regarded as the same type of pads. Sometimes, the arrangement order of these control pads and power supply pads is symmetrical with respect to the arrangement direction of the pads, so that a pair of display driver means are arranged on both sides of the display panel, and the power supply lines are arranged on both sides. Since it can be connected to the power supply pad, a voltage drop in the power supply line is reduced, luminance unevenness can be prevented, and space can be saved.

  Further, according to the present invention, a pair of driver means are provided on both sides of the display panel, the pair of driver means are both connected to the power line and connected to the plurality of control lines, the power control signal and the control Since the plurality of pixel circuits are driven by the signal, the voltage drop in the power supply line is reduced, the occurrence of uneven brightness can be prevented, and the space can be saved.

  Embodiments of a display panel driver and an image display device according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

  FIG. 1 is a block diagram showing a configuration of an image display apparatus according to Embodiment 1 of the present invention. The image display apparatus shown in the figure includes a display panel 10, a controller 20, a gate driver 30R1, a gate driver 30R2,..., A gate driver 30L1, a gate driver 30L2,. .

  The display panel 10 includes pixel circuits 10G1 (1),..., Pixel circuits 10G1 (s), pixel circuits 10G2 (1),..., Pixel circuits 10G2 (s), pixel circuits arranged in a matrix. 10Gk (1),..., And pixel circuit 10Gk (s),.

  Here, in the display panel 10, four lines (for example, a first control line x1 (1), a second control line x2 (1), and a third control line x3 (1) are provided for each row (horizontal direction in the figure). ), And a plurality of sets of four lines are provided with the power supply line p (1)) as one set.

  Specifically, in the first row corresponding to the pixel circuit 10G1 (1),..., The pixel circuit 10G1 (s) of the display panel 10, the first control line x1 (1) and the second control line x2 are provided. (1), four lines of the third control line x3 (1) and the power supply line p (1) are provided.

  In the second row corresponding to the pixel circuit 10G2 (1),..., The pixel circuit 10G2 (s) of the display panel 10, the first control line x1 (2) and the second control line x2 (2) are provided. In addition, four lines of the third control line x3 (2) and the power supply line p (2) are provided.

  Similarly, in the k-th row corresponding to the pixel circuits 10Gk (1),..., Pixel circuit 10Gk (s) of the display panel 10, the first control line x1 (k) and the second control line x2 are arranged. (K), four lines of a third control line x3 (k) and a power supply line p (k) are provided.

  In the display panel 10, s data lines y (1),..., Data line y (s) are provided for each column (vertical direction in the figure).

  The pixel circuit 10G1 (1) includes the organic EL element 11 and the control circuit 12 as shown in FIG. The organic EL element 11 is a light emitting element that emits light when a voltage equal to or higher than a threshold is applied between the anode and the cathode. The cathode of the organic EL element 11 is connected to the power supply line p (1). Depending on the circuit configuration, the connection state of the anode and cathode of the organic EL element 11 may be reversed.

  The control circuit 12 includes a driving transistor, a selection transistor, a capacitor, and the like similar to the driving transistor 7, the selection transistor 8, the capacitor Cp, and the like (see FIG. 8), and emits light from the organic EL element 11. Control.

  The control circuit 12 is connected to a first control line x1 (1), a second control line x2 (1), a third control line x3 (1), and a data line y (1). Here, the first control line x1 (1), the second control line x2 (1), and the third control line x3 (1) are the above-described gate line GL, drain line DL (see FIG. 8), etc., and row selection. This corresponds to a scanning line to which a select signal for transmission is transmitted, a control line to which a reset signal for resetting charges accumulated in the capacitance and the light emitting element is transmitted, and the like.

  The other first control lines x1 (2), second control lines x2 (2), third control lines x3 (2), data lines y (2), etc. shown in FIG. It corresponds to GL, drain line DL (see FIG. 8), and the like.

  Further, in the display panel 10 shown in FIG. 1, the other pixel circuits have the same configuration as the pixel circuit 10G1 (1) described above.

  The controller 20 is connected to the gate driver 30R1, the gate driver 30R2, ..., the gate driver 30L1, the gate driver 30L2, ..., and the data driver 40, and controls image display on the display panel 10.

  Further, the gate driver 30R1, the gate driver 30R2,..., And the gate driver 30L1, the gate driver 30L2,. That is, on the left side of the display panel 10, a gate driver 30R1, a gate driver 30R2,. On the other hand, a gate driver 30L1, a gate driver 30L2,... Are provided on the right side of the display panel 10.

  In practice, the gate driver 30R1, the gate driver 30R2,... Are provided in the vicinity of the display panel 10 in the same manner as the gate driver 30L1, the gate driver 30L2,.

  These gate driver 30R1, gate driver 30R2,..., And gate driver 30L1, gate driver 30L2,... Halve a plurality of control lines in the display panel 10 (when the number of control lines is an even number) or Each is responsible for approximately half (when the number of control lines is an odd number).

  Here, a generalized configuration of the above-described gate driver 30R1, gate driver 30R2,..., Gate driver 30L1, gate driver 30L2,. In the drawing, the gate driver 30R1 is shown as an example.

  The gate driver 30R1 is provided with a first to k-th sets and a plurality of spare pads (hatched squares). That is, the first set is a control pad C1 (1), a control pad C2 (1),..., A control pad Cm (1) and a power supply pad P (1). The second set is a control pad C1 (2), a control pad C1 (2),..., A control pad Cm (2) and a power supply pad P (2). Similarly, the k-th group includes a control pad C1 (k), a control pad C2 (k),..., A control pad Cm (k), and a power supply pad P (k).

  The spares are spare pads C1 (k + 1), spare pads C2 (k + 1),..., Spare pads Cm (k + 1). These spare pads C1 (k + 1), spare pads C2 (k + 1),..., Spare pads Cm (k + 1) can be regarded as pads of the same type with the same area as the control pads C1 (1). it can.

  The gate driver 30R1 includes an input pad SI / O1 to an input pad SI / On (where n ≧ m), an input pad MODE, an output pad SO / I1 to an output pad SO / In. Is provided. Among these pads, a large current flows through the power supply pad P (1), the power supply pad P (2), the power supply pad P (k),..., And the power supply pad P (k + 1). The area is larger than pads (control pad C1 (1) to control pad C1 (k + 1), etc.).

  Thus, in the gate driver 30R1, the large area pads and the small area pads are mixed and arranged in a row. Further, the arrangement order (or arrangement position) of the power supply pads P (1) and the like and the control pads C1 (1) and the like is symmetrical in the arrangement direction of the pads. Further, the number of control pads C1 (1) and the like is equal to or greater than the number of power supply pads P (1) and the like. Here, in FIG. 3, the pixel circuit 10G1 (1) has j control lines, and is illustrated by a first control line x1 (1) to a first control line x1 (j).

  When j is an odd number, “m” in the control pad Cm (1), the control pad Cm (2),..., the control pad Cm (k) and the control pad Cm (k + 1) is [j / 2] +1. However, [] is a Gaussian symbol. On the other hand, when j is an even number, “m” in the control pad Cm (1), the control pad Cm (2),..., The control pad Cm (k) and the control pad Cm (k + 1) is (J / 2).

  In the case of the gate driver 30R1 shown in FIG. 1, j is 3, m is 2, and n is 4, and the gate driver shown in FIG. 2 is applied. The gate driver 30L1 also has the same circuit design as the gate driver 30R1, and the set corresponding to the first set of the gate driver 30R1 includes a control pad C2 (k + 1), a control pad C1 (k + 1), and a power supply pad. P (k).

  A pair corresponding to the second group of the gate driver 30R1 is a control pad C2 (k), a control pad C1 (k), and a power supply pad P (k-1). Similarly, the set corresponding to the k-th set of the gate driver 30R1 is the control pad C2 (2), the control pad C1 (2), and the power supply pad P (1). The spares in the gate driver 30L1 are the control pad C2 (1) and the control pad C1 (1).

  Here, in the first control line x1 (1), the second control line x2 (1), the third control line x3 (1), and the power supply line p (1) corresponding to the first set, the power supply line p (1). Are connected to the power supply pad P (1) of the gate driver 30R1 and the right end is connected to the power supply pad P (k) of the gate driver 30L1 so that the voltage level of the transmitted signal is high and the voltage drop is reduced. It is connected to the.

  In contrast, the left ends of the first control line x1 (1) and the second control line x2 (1) are connected to the control pad C1 (1) and the control pad C2 (1) of the gate driver 30R1. . Note that the right end of the first control line x1 (1) and the second control line x2 (1) has a low voltage level of the signal to be transmitted and the influence of the voltage drop can be ignored, so any control pad of the gate driver 30L1 Also not connected.

  The right end of the third control line x3 (1) is connected to the control pad C1 (k + 1) of the gate driver 30L1. Note that the left end of the third control line x3 (1) is not connected to any control pad of the gate driver 30R1 because the voltage level of the signal to be transmitted is low and the influence of the voltage drop can be ignored.

  Thus, in the first set, the power supply line p (1) is assigned to both the gate driver 30R1 and the gate driver 30L1 in order to reduce the voltage drop. On the other hand, the first control line x1 (1) and the second control line x2 (1) are assigned to the gate driver 30R1. The third control line x3 (1) is assigned to the gate driver 30L1. Hereinafter, the same applies to other groups.

  The gate driver 30R1, the gate driver 30R2,... Are connected in series. Similarly, the gate driver 30L1, the gate driver 30L2,... Are also connected in series.

  The data driver 40 outputs selection signals to the data lines y (1) to y (s) according to the gate control signal supplied from the controller 20, respectively. Only one of the selection signals is active at the same timing, and is a signal for selecting any one column in the display panel 10.

  FIG. 4 is a diagram showing a configuration of the gate driver 30R1 shown in FIG. In the figure, parts corresponding to the parts in FIG. The gate driver 30R1 includes a shift register 31 and a shift register 32.

  The shift register 31 is composed of a plurality of flip-flop circuits and logic circuits. As shown in FIG. 5, each flip-flop 31 is set at the rising timing of the clock signal CLK based on a signal supplied from the controller 20. The signals held in the circuit are shifted and output to the control pads C1 (1), C1 (2),... (Control pads C2 (1), C2 (2).

  On the other hand, the shift register 32 shown in FIG. 4 also includes a plurality of flip-flop circuits, a logic circuit, and a selector circuit. As shown in FIG. 5, the clock signal is based on a signal supplied from the controller 20. At the timing of rising of CLK, the signal held in each flip-flop circuit is shifted and output to the power supply pad P (1), the power supply pad P (2),.

  Here, signals are also output from the power supply pad P (k), the power supply pad P (k−1),... Of the gate driver 30L1 shown in FIG. These signals are supplied to each organic EL element 11 (see FIG. 2), and function as a power supply voltage for causing the organic EL element 11 to emit light together with a control signal (ON / OFF).

  Accordingly, in the first embodiment, since the signal is supplied from the gate driver 30L1 and the gate driver 30R1 on both sides to the power supply line p (1), the signal transmission path is compared with the case of the conventional gate driver on one side. The length is significantly shortened and the voltage drop is reduced.

  As described above, based on the control of the controller 20, the signals from the gate driver 30R1, the gate driver 30L1, and the like, and the data driver 40 are supplied to the display panel 10, whereby the light emission of the organic EL element 11 is controlled and the display is performed. An image is displayed on the panel 10.

  As described above, according to the first embodiment, a pair of driver 30R1 and gate driver 30L1 are provided on both sides of the display panel 10, and the driver 30R1 and gate driver 30L1 are connected to the power supply line p (1) and the power supply line. p (2),... are both connected to and connected to a plurality of first control lines x1 (1), first control lines x1 (2),... ) -10 Gk (s) is driven, voltage drop in the power supply line p (1), power supply line p (2),... Is reduced, luminance unevenness is prevented, and space saving is achieved. be able to.

  In the first embodiment, the area of each pad (control pad C1 (1), power supply pad P (1), etc.) arranged in the driver means (gate driver 30R1, gate driver 30L1, etc.) is different. If the arrangement of the pads is not devised, the wiring structure of the power supply lines and control lines on the display panel 10 becomes complicated when the same driver means is arranged on both sides of the display panel 10.

  Therefore, in the first embodiment, even if the driver means are arranged on both sides of the display panel 10 by devising the arrangement of the pads of the driver means (such as the arrangement of the preliminary control pads and the symmetrical arrangement described above), Complicating the wiring structure of the display panel 10 can be satisfactorily suppressed. The pads may be arranged in a symmetrical order (the order is symmetrical, but it is assumed that the spacing between the pads is not vertically symmetrical but is different vertically), but the arranged positions are symmetrical. In addition, the wiring structure of the display panel can be simplified.

  In the above-described first embodiment, as shown in FIG. 3, the configuration example in the case of one power supply line p (1) per set has been described. It is good also as an example of composition which makes it. Hereinafter, this configuration example will be described as a second embodiment.

  FIG. 6 is a diagram illustrating the configuration of the gate driver 50R1, the pixel circuit 10G1 (1) ′, and the like applied to the second embodiment of the invention. In this figure, parts corresponding to those in FIG.

  In the pixel circuit 10G1 (1) ′ shown in the figure, j first control lines x1 (1),..., Jth control line xj (1) and two first power supply lines p1 ( 1) and the second power supply line p2 (1) are provided in the row direction.

  The gate driver 50R1 is provided with a plurality of pads of first to kth sets. That is, the first set includes the control pad C1 (1), the control pad Cq (1), the control pad Cq + 1 (1), the control pad Cl (1), the control pad Cl + 1 (1), and the control pad. Cm (1), power supply pad P1 (1), and power supply pad P2 (1).

  The second set includes a control pad C1 (2), a control pad Cq (2), a control pad Cq + 1 (2), a control pad Cl (2), a control pad Cl + 1 (2), and a control pad Cm ( 2) a power supply pad P1 (2) and a power supply pad P2 (2).

  Similarly, the k-th group includes a control pad C1 (k), a control pad Cq (k), a control pad Cq + 1 (k), a control pad Cl (k), a control pad Cl + 1 (k), A control pad Cm (k), a power supply pad P1 (k), and a power supply pad P2 (k).

  Also, the pixel circuit 10G1 (1) 'has j control lines, and is illustrated by a first control line x1 (1) to a jth control line xj (1). Further, the power supply lines of the pixel circuit 10G1 (1) 'are illustrated by a first power supply line p1 (1) and a second power supply line p2 (1).

  When j is an odd number, in the same manner as in the first embodiment, “m” in the control pad Cm (1), the control pad Cm (2),. / 2] +1. On the other hand, when j is an even number, “m” in the control pad Cm (1), the control pad Cm (2),..., The control pad Cm (k) is represented by (j / 2). The

  In the second embodiment, a gate driver (not shown) having a circuit design similar to that of the gate driver 50R1 shown in FIG. 6 is provided at a position corresponding to the gate driver 30L1 shown in FIG.

  Here, the first control line x1 (1), the second control line x2 (1),..., The jth control line xj (1), the first power supply line p1 (1) and the first control line corresponding to the first set. In the two power supply lines p2 (1), the first power supply line p1 (1) and the second power supply line p2 (1) have the voltage level of the signal to be transmitted high, and the left end is the power supply of the gate driver 50R1 in order to reduce the voltage drop. Connected to the power supply pad P1 (1) and the power supply pad P2 (1), and the right end is also connected to two power supply pads (not shown) of the gate driver (not shown) having the same circuit design as the gate driver 50R1. It is connected.

  On the other hand, the first control line x1 (1), the second control line x2 (1),..., The jth control line xj (1) are the first set of control pads of the left gate driver 50R1. And a control pad of the right gate driver (not shown).

  Thus, in the first set, the first power supply line p1 (1) and the second power supply line p2 (1) are provided with the left gate driver 50R1 and the right gate driver (not shown) in order to reduce the voltage drop. It is in charge of both sides. Hereinafter, the same applies to other groups.

  FIG. 7 is a diagram showing a configuration of the gate driver 50R1 shown in FIG. In the figure, parts corresponding to the parts in FIG. The gate driver 50R1 includes a shift register 51 and a shift register 52.

  The shift register 51 includes a plurality of flip-flop circuits and logic circuits, and is held in each flip-flop circuit at the rising timing of the clock signal CLK based on a signal supplied from a controller (not shown). The signal is shifted and output to the control pads C1 (1), C1 (2),... (Control pads C2 (1), C2 (2).

  On the other hand, the shift register 52 is also composed of a plurality of flip-flop circuits, logic circuits, and selector circuits, and each flip-flop is synchronized with the rising timing of the clock signal CLK based on a signal supplied from a controller (not shown). The signal held in the circuit is shifted and output to the power supply pad P1 (1) (power supply pad P2 (1)), the power supply pad P1 (2) (power supply pad P2 (2)),. .

  Here, signals are also output from the respective power supply pads (not shown) of the right gate driver (not shown) corresponding to the left gate driver 50R1 at the same timing as the gate driver 50R1. These signals are supplied to each organic EL element 11 (see FIG. 6), and function as a power supply voltage for causing the organic EL element 11 to emit light together with a control signal (ON / OFF).

  Therefore, in the second embodiment, as in the first embodiment, signals are supplied from the gate driver 50R1 and the gate driver (not shown) on both sides to the first power supply line p1 (1) and the second power supply line p2 (1). Therefore, the signal transmission path length is significantly shortened and the voltage drop is reduced as compared with the conventional gate driver on one side.

  As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained.

  As described above, the display panel driver means and the image display apparatus according to the present invention are useful for improvement of luminance unevenness and space saving.

1 is a block diagram illustrating a configuration of an image display device according to a first embodiment of the present invention. It is a figure which shows the structure of gate driver 30R1 and pixel circuit 10G1 (1) shown in FIG. FIG. 3 is a diagram showing a generalized configuration of a gate driver 30R1 and a pixel circuit 10G1 (1) shown in FIG. It is a figure which shows the structure of the gate driver 30R1 shown in FIG. 3 is a timing chart for explaining the operation of the gate driver 30R1 shown in FIG. It is a figure which shows the structure of the gate driver 50R1, the pixel circuit 10G1 (1) ', etc. which are applied to Example 2 concerning this invention. It is a figure which shows the structure of the gate driver 50R1 shown in FIG. It is a figure which shows the structure of the conventional image display apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Display panel 10G1 (1) -10Gk (s) Pixel circuit 20 Controller 30R1, 30R2, 30L1, 30L2 Gate driver x1 (1) 1st control line x2 (1) 2nd control line x3 (1) 3rd control line p (1) Power line 40 Data driver 50R1 Gate driver p1 (1) First power line p2 (1) Second power line

Claims (12)

In a display panel driver means for driving a display panel having a light emitting element,
A control pad electrically connected to a control line through which a control signal for light emission control of the light emitting element is transmitted;
A power supply pad electrically connected to a power supply line for supplying power to the light emitting element and having a larger area than the control pad;
The control pads and the power supply pads are mixed and arranged in a row, and the arrangement order of the control pads and the power supply pads is symmetric in the arrangement direction of the pads,
A display panel driver means.   2. The display panel driver means according to claim 1, wherein the arrangement positions of the control pads and the power supply pads are symmetrical with respect to the arrangement direction of the pads. In a display panel driver means for driving a display panel having a light emitting element,
A control pad electrically connected to a control line through which a control signal for light emission control of the light emitting element is transmitted;
A preliminary control pad having the same shape as the control pad;
A power supply pad electrically connected to a power supply line for supplying power to the light emitting element and having a larger area than the control pad;
When the control pad, the preliminary control pad, the power supply pad are mixed and arranged in a row, and the control pad and the preliminary control pad are regarded as the same type of pads, The display panel driver means, wherein the arrangement order of the control pads and the power supply pads is symmetrical with respect to the arrangement direction of the pads.   When the control pads and the preliminary control pads are regarded as the same type of pads, the arrangement positions of the control pads and the power supply pads are symmetric in the arrangement direction of the pads. Item 4. The display panel driver means according to Item 3.   5. The display panel driver means according to claim 1, wherein the number of the control pads is equal to or greater than the number of the power supply pads.   6. The control pad and the preliminary control pad have a flip-flop circuit corresponding to each pad, and the flip-flop circuits are connected in series. The display panel driver means according to claim 1. A display panel in which a plurality of pixel circuits each having a light emitting element that emits light by current injection are arranged in a matrix;
A power supply line connected to each of the plurality of pixel circuits and transmitting a power supply control signal for power supply and light emission control;
A plurality of control lines connected to the plurality of pixel circuits, respectively, through which a control signal for light emission control is transmitted;
A pair of both sides of the display panel, connected to the power line and connected to the plurality of control lines, and driving the plurality of pixel circuits by the power control signal and the control signal. Driver means;
An image display device comprising:   The image display apparatus according to claim 7, wherein the pair of driver means is the display panel driver means according to claim 1.   9. The image display device according to claim 7, wherein the control signal for light emission control includes either a select signal or a reset signal.   The image display according to any one of claims 7 to 9, wherein a plurality of the power supply lines are provided, and the pair of driver means are both connected to the plurality of power supply lines. apparatus.   The image display device according to claim 7, wherein the pair of driver units have the same circuit design.   The image display apparatus according to claim 7, wherein the light emitting element is an organic EL element.

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