JP2006006550A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine electronically controlling a game operation and a test operation. <P>SOLUTION: This game machine is provided with inverters 61-63, connectors 64-66 and an I/F board 100, as connecting means, interposed between a trial shoot testing machine 120 and a Pachislo slot machine 1 and realizing connecting compatibility of the both test signals, and a microcomputer 30, as a test control means, when receiving a test signal related to the game operation from the testing machine via those connecting means, controlling to test the game operation by responding to the test signal. The I/F board 100 is provided with electronic components 116 and 117 such as amplitude modulating circuits or the like modulating the test signal from the game machine 1 to the trial shoot testing machine 120 to be fitted to the transmission, photocouplers 107 and 108 transmitting the amplitude modulated test signal while electrically cutting it off, and a photocoupler 109 transmitting the test signal from the trial shooting machine 120 to the Pachislo slot machine 1 while electrically cutting it off. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a gaming machine that can be connected to a testing machine.

A conventional gaming machine electronically controls a gaming operation using a microcomputer (see, for example, Patent Document 1). Here, when a performance test of a gaming machine is performed before shipment, generally, a medal is inserted and operated for a predetermined time in the same manner as in actual gaming, and the test result is analyzed to determine whether there is a fair play performance. "No" is evaluated. In addition, a medal is inserted by a mechanical work, and a manual operation is monitored for erroneous insertion.
Japanese Patent Publication No. 3-72313 (page 9, lower left to middle right, FIG. 26, etc.)

  However, the conventional gaming machine has a problem in that when performing a performance test before shipment, a malfunction may occur in a mechanical medal insertion operation, so that a manual monitoring operation is required. In addition, no consideration has been given to performing performance tests using existing microcomputers of gaming machines.

  The present invention has been made to solve the conventional problems, and an object thereof is to provide a gaming machine capable of electronically controlling a gaming operation and a test operation.

(1) When the gaming machine of the present invention is connected to a testing machine (for example, 120 in FIG. 7), it exchanges test signals relating to gaming operations with the testing machine and is not connected to the testing machine. Then, a gaming machine that performs a gaming operation when a gaming value is input, and is a connecting means that intervenes between a testing machine and a gaming machine (for example, 1 in FIG. 7) to realize the connection compatibility of both signals. (For example, 61 to 63, 64 to 66, 100 in FIG. 7) and a test for controlling to respond to the test signal when a test signal related to a gaming operation is received from the testing machine via the connection means. And a control means (for example, 30 in FIG. 7).
(2) In the gaming machine of the present invention, in (1), the connection means includes modulation means for modulating a test signal from the gaming machine to the testing machine so as to be suitable for transmission (for example, 116 and 117 in FIG. 7); First cut-off transmission means for transmitting the test signal modulated by the modulation means while being cut off electrically (for example, 107 and 108 in FIG. 7), and electrically cut off the test signal from the test machine to the gaming machine. The second cut-off transmission means (for example, 109 in FIG. 7) for transmission is provided.
(3) The gaming machine according to the present invention has an input value counting means (for example, 22S and 30 in FIG. 6) for counting the number of game values input by a player from a predetermined input port, and a game according to an operation by the player. A game start command means for outputting a start command signal (for example, 6S and 30 in FIG. 6) and a stop command means for outputting a stop command signal in response to an operation by the player (for example, 7L, 7C, and 7R in FIG. 46, 30), variation display means for variably displaying a plurality of identification information necessary for the game (for example, 3L, 3C, 3R in FIG. 6), the variation display means is driven by the game start command signal, and the stop command signal The stop mode of the drive stop control means (for example, 39, 49L, 49C, 49R in FIG. 6) that stops the change display means by the stop display of the change display means stopped by the drive stop control means by the stop command signal is a predetermined stop mode. To be , A payout command means for outputting a payout command signal (for example, 30 in FIG. 6), a game value payout means for paying out a predetermined game value by the payout command signal (for example, 40 in FIG. 6), a test machine and a gaming machine A connection means (for example, 100 in FIG. 6) that intervenes between the two to realize the connection compatibility of both signals, and when the test signal related to the gaming operation from the testing machine is received via the connection means, the test Test control means (for example, 30 in FIG. 6) for controlling to test the gaming operation by responding to the signal, and the connecting means is suitable for transmission of the test signal from the gaming machine to the testing machine. An amplitude modulation circuit (for example, 116 and 117 in FIG. 7) that performs amplitude modulation, and a first photocoupler (for example, 107 in FIG. 7) that transmits the test signal that has been amplitude-modulated by the amplitude modulation circuit while being electrically cut off. , 108 When, and a second photo-coupler for transmitting while electrically blocking the test signal to the gaming machine from tester (e.g., 109 in FIG. 7), the arrangement having a.

  The present invention provides a gaming machine that performs a gaming operation when a gaming value is input, a connection means that intervenes between the test machine and the gaming machine to realize connection compatibility of both signals, and through the connection means. The effect that it is possible to electronically control the game operation and the test operation by providing a test control means for controlling so as to respond to the test signal when the test signal related to the game operation from the testing machine is received. Can be provided.

  Hereinafter, a gaming machine according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 shows a gaming machine according to an embodiment of the present invention. This gaming machine is a so-called “pachislot machine”. The pachi-slot machine 1 is a gaming machine that uses a game medium such as a coin or a medal, a game ball, a token, or the like, or a game medium such as a card that stores information on a game value assigned to a player. However, below, medals and cards (hereinafter referred to as CR cards) are used.

  A panel display portion 2a as a substantially vertical surface is formed on the front surface of the cabinet 2 forming the entire pachi-slot machine 1, and vertically long display windows 4L, 4C, and 4R are provided at the center thereof. The display windows 4L, 4C and 4R are provided with a top line 8b, a center line 8c and a bottom line 8d in the horizontal direction as winning lines, and a cross-up line 8a and a cross-down line 8e in the diagonal direction. These winning lines are respectively operated by operating a 1-BET switch 11, a 2-BET switch 12, and a maximum BET switch 13, which will be described later, or by inserting medals into the medal slot 22, respectively. The book is activated. Which winning line is activated is displayed by lighting of BET lamps 9a, 9b, 9c, which will be described later.

  Here, the winning lines 8a to 8e relate to success / failure of the winning combination. Specifically, one symbol (for example, “cherry (symbol 94)” to be described later) corresponding to a predetermined role (for example, “cherry small role” to be described later) is a predetermined position (for example, “cherry (symbol 94)” to be described later). For example, if the number of BETs to be described later is “3”, the symbol is stopped and displayed at the middle position in the left display window 4L), or the symbol constituting the symbol combination corresponding to the predetermined combination is any valid line. A predetermined combination is won by being stopped and displayed side by side at a predetermined position corresponding to.

  Inside the cabinet 2, three reels 3L, 3C, and 3R each having a symbol row constituted by a plurality of types of symbols on each outer peripheral surface are rotatably provided in a horizontal row. The design of each reel can be seen through the display windows 4L, 4C, 4R. Each reel rotates at a constant speed (for example, 80 rotations / minute).

  On the left side of the display windows 4L, 4C, and 4R, a 1-BET lamp 9a, a 2-BET lamp 9b, a maximum BET lamp 9c, an information display unit 18, and a cross key 24 are provided. The 1-BET lamp 9a, the 2-BET lamp 9b, and the maximum BET lamp 9c are turned on according to the number of medals betted to play one game (hereinafter referred to as “BET number”).

  The 1-BET lamp 9a is turned on when the BET number is "1" and one winning line is activated (when one activated line is set). The 2-BET lamp 9b is lit when the BET number is "2" and three pay lines are activated (when three valid lines are set). The maximum BET lamp 9c is turned on when the number of BETs is “3” and all (5) winning lines are activated (when all (5) activated lines are set). The information display unit 18 is composed of 7-segment LEDs, and displays the number of medals stored (credited), the number of medals paid out at the time of winning a prize, and the like. The cross key 24 is for operating the liquid crystal display device 5 to make various settings.

  A horizontal base 10 is formed below the display windows 4L, 4C, 4R, and a liquid crystal display device 5 is provided between the base 10 and the display windows 4L, 4C, 4R. Information relating to the game is displayed on the display screen 5 a of the liquid crystal display device 5. A medal slot 22 is provided on the right side of the liquid crystal display device 5, and a 1-BET switch 11, a 2-BET switch 12, and a maximum BET switch 13 are provided on the left side of the liquid crystal display device 5.

  One of the credited medals is bet on the game by pressing the 1-BET switch 11 once, and one of the credited medals is pressed by pressing the 2-BET switch 12 once. Two cards are bet on the game, and the maximum number of medals that can be bet on one game is bet by pressing the maximum BET switch 13 once. By operating these BET switches 11, 12, and 13, a predetermined pay line is activated as described above.

  A C / P switch 14 is provided on the left side of the front portion of the pedestal 10 to switch the credit / payout of medals acquired by the player in the game by a push button operation. By switching the C / P switch 14, medals are paid out from the medal payout opening 15 at the lower front, and the paid-out medals are stored in the medal receiving portion 16. On the right side of the C / P switch 14, the reel is rotated by the player's operation, and the start lever 6 for starting the symbol variation display in the display windows 4L, 4C, 4R is rotated within a predetermined angle range. It is attached movably.

  Three stop buttons 7L, 7C, and 7R for stopping the rotation of the three reels 3L, 3C, and 3R are provided at the center of the front surface portion of the pedestal portion 10 and below the liquid crystal display device 5, respectively. Yes. Speakers 21 </ b> L and 21 </ b> R are provided on the left and right above the medal receiving portion 16. In the present embodiment, one game (unit game) basically starts when the start lever 6 is operated, and ends when all the reels 3L, 3C, 3R are stopped.

  Furthermore, a CR unit (not shown) for setting the number of inserted medals using information stored in a CR card (which corresponds to a so-called prepaid card) is provided on one side of the cabinet 2. The CR unit includes a card insertion slot for inserting a CR card and a card reader unit for reading the CR card. Further, in the center of the front surface of the pedestal 10, a display unit 130 a (for example, one composed of 7 SEGLED) that displays information on the remaining number of medals stored in the CR card and the payout number, and a card insertion slot A card return button 130b for instructing the return of the inserted CR card, and an operation button 130c for operating the player to instruct the payout of a predetermined number of medals are provided. Further, the cabinet 2 has a CR board 130 (shown in FIG. 6) for transmitting a medal payout number set by the operation button 130c to the microcomputer as a CR signal.

  Here, “the number of sliding symbols” in the gaming state of the present embodiment will be described. The number of sliding symbols is the number of symbols to be displayed after the stop buttons 7L, 7C, and 7R are operated and when this operation is detected until the reels 3L, 3C, and 3R are stopped. In addition, the number of symbols (the amount of symbol movement) moved from when the stop button 7L, 7C, 7R is operated until the corresponding reel 3L, 3C, 3R stops. Specifically, the number of sliding symbols is determined by a predetermined effective line such as a center line 8c at the center of the symbol after the stop buttons 7L, 7C, 7R are operated and before the corresponding reels 3L, 3C, 3R stop. It matches the number of symbols that crossed. In the present embodiment, the maximum value of the number of sliding frames is set to “4”.

  In this embodiment, the reel stop operation (stop button operation) performed when all the reels are rotating is “first stop operation”, and the stop operation performed after the first stop operation is “first stop operation”. The “2 stop operation” and the stop operation performed after the second stop operation are referred to as “third stop operation”. Here, the maximum number of sliding pieces of the reel corresponding to the first stop operation is set to “1”, and the number of sliding pieces of the reel corresponding to the second stop operation and the third stop operation (maximum number of sliding pieces) is basically set. Therefore, it is set to “0”.

  FIG. 2 shows a symbol row in which 21 types of symbols represented on each reel 3L, 3C, 3R are arranged. Each symbol is assigned a code number “00” to “20”, and is stored (stored) in a ROM 32 (shown in FIG. 6), which will be described later, as a data table. On each reel 3L, 3C, 3R, "BAR (symbol 91)", "Watermelon (symbol 92)", "Replay (symbol 93)", "Cherry (symbol 94)", "Bell (symbol 95)" A symbol sequence composed of symbols is represented. Here, each of the reels 3L, 3C, 3R is rotationally driven so that the symbol row moves in the direction of the arrow in FIG. In this embodiment, a regular bonus (hereinafter referred to as RB), a replay, a watermelon small role, a bell small role, a cherry small role, and a loser are provided.

  FIG. 3 shows a combination, a symbol combination, and a payout number of this embodiment.

  The RB winning is realized by arranging “BAR-BAR-BAR” along the active line. In this case, the number of payouts is “0”, but the game state of the next game is “RB game state”. In addition, when “BAR-BAR-BAR” is not lined up along the active line while RB is internally won (when lost is won), the RB carryover state is set. The RB gaming state and the RB carryover state are gaming states in which a predetermined symbol combination “Bell-Bell-Bell” is aligned by betting one medal and it is easy to win a role that can acquire 15 medals.

  Note that the maximum number of games possible in one RB gaming state is 12. In addition, the number of winnings that can be won in one RB gaming state is eight. In other words, the RB gaming state ends when the number of games reaches 12 times or the number of winnings reaches 8.

  The winning of the cherry small role is realized by arranging “cherry-any symbol (ANY) -any symbol (ANY)” along the active line. In this case, the number of payouts is “1”.

  The winning of the small role of the bell is realized by arranging “bell-bell-bell” along the active line. In this case, the number of payouts is “15”.

  The prize for the small role of watermelon is realized by arranging "watermelon-watermelon-watermelon" along the effective line. In this case, the number of payouts is “6”.

  Replay winning is realized by arranging “Replay-Replay-Replay” along the active line. When the replay wins, the same number of medals as the number of inserted medals are automatically inserted, so that the player can play the next game without consuming the medals. In other words, the replay is a role in which a game can be performed without winning a game value by winning.

  FIG. 4 shows a probability lottery table used in this embodiment.

  In the present embodiment, an internal winning combination is determined using one probability lottery table, and an internal winning combination is selected among RB, cherry small combination, bell small combination, watermelon small combination, replay, and lose (none). I am doing so. In the general gaming state of FIG. 4, the probability of winning the RB is “1/256”. Similarly, the probability of winning the cherry role is “1/128”. Similarly, the probability of winning the small part of Bell is “1/16”. Similarly, the probability of winning a watermelon small role is “1/128”. Similarly, the probability of winning the replay is “2341/16384”. Similarly, the probability of winning the loss is “12699/16384”.

  In the RB carryover state of FIG. 4, the probability of winning the RB is “0”. Similarly, the probability of winning the cherry role is “1/128”. Similarly, the probability of winning the small part of Bell is “1/16”. Similarly, the probability of winning a watermelon small role is “1/128”. Similarly, the probability of winning the replay is “2341/16384”. Similarly, the probability of winning the loss is “12763/16384”.

  In the RB gaming state of FIG. 4, the probability of winning the RB is “0”. Similarly, the probability of winning the cherry role is “1/128”. Similarly, the probability of winning the small role of Bell is “16063/16384”. Similarly, the probability of winning a watermelon small role is “1/128”. Similarly, the probability of winning the replay is “1/256”. Similarly, the probability of winning the loss is “1/16384”.

  FIG. 5 shows a winning combination selection table for stopping used for determining a winning combination for stopping in the present embodiment.

  In the present embodiment, the winning combination for stoppage is determined using one winning combination selection table for stoppage. In the winning winning combination selection table in FIG. 5, the probability (selection probability) of selecting each winning winning combination for each internal winning combination and each gaming state is described. The winning combination for stop is information used for stop control of the reels 3L, 3C, 3R. In addition, when the winning combination for stop is determined, the reels 3L, 3C, 3R is controlled to stop. Furthermore, stop control is performed in a state where a symbol or symbol combination corresponding to a combination other than the winning combination for stop is not permitted.

  Here, in order to realize each selection probability, a predetermined lottery value set for each internal winning combination and each gaming state is subtracted from a random number value extracted in a predetermined random number extraction range (for example, “0 to 127”). When the subtracted value is negative, information corresponding to the lottery value (stop winning combination) is selected. In the general gaming state of FIG. 5, when the internal winning combination is RB, “losing” as the winning winning combination is selected with a probability of “128/128”. When the internal winning combination is a cherry small combination, “cherry small combination” as a winning combination for stopping is selected with a probability of “128/128”. Further, when the internal winning combination is a Bell small combination, “Bell small combination” as a winning combination for stopping is selected with a probability of “128/128”. When the internal winning combination is a watermelon small combination, “watermelon small combination” as a winning combination for stopping is selected with a probability of “128/128”. In addition, when the internal winning combination is replay, “replay” as the winning winning combination is selected with a probability of “128/128”, and the probability that “reach eyes” and “losing” are selected as the winning winning combination is “0”. Also, when the internal winning combination is a loss, the “losing” as the winning winning combination is selected with a probability of “128/128”, and the probability that “RB” and “losing” are selected as the winning winning combination is “ 0 ".

  In the RB carryover state of FIG. 5, when the internal winning combination is a cherry small combination, “cherry small combination” as a winning combination for stopping is selected with a probability of “128/128”. Further, when the internal winning combination is a Bell small combination, “Bell small combination” as a winning combination for stopping is selected with a probability of “128/128”. When the internal winning combination is a watermelon small combination, “watermelon small combination” as a winning combination for stopping is selected with a probability of “128/128”. In addition, when the internal winning combination is replay, “replay” as the winning winning combination is selected with a probability of “128/128”, and the probability that “reach eyes” and “losing” are selected as the winning winning combination is “0”. If the internal winning combination is a loss, the probability of “losing” as a winning winning combination is selected with a probability of “4/128” or the probability of “RB” as a winning winning combination being “120/128”. Or “reach eyes” as a winning combination for stopping is selected with a probability of “4/128”.

  In the RB gaming state of FIG. 5, when the internal winning combination is a cherry small combination, “cherry small combination” as a winning combination for stopping is selected with a probability of “128/128”. Further, when the internal winning combination is a Bell small combination, “Bell small combination” as a winning combination for stopping is selected with a probability of “128/128”. When the internal winning combination is a watermelon small combination, “watermelon small combination” as a winning combination for stopping is selected with a probability of “128/128”. Also, when the internal winning combination is replay, the probability that “replay” as a winning winning combination is selected with a probability of “64/128” or the probability that “reach eyes” as a winning winning combination is “32/128” Or “losing” as a winning winning combination is selected with a probability of “32/128”. When the internal winning combination is a loss, “losing” as a winning winning combination is selected with a probability of “64/128”, or “reach” as a winning winning combination is “64/128”. The probability that “RB” is selected as the winning combination for stopping is “0”.

  6 is based on a main control circuit 71 that controls game processing operations in the pachislot machine 1, peripheral devices (actuators) that are electrically connected to the main control circuit 71, and control commands transmitted from the main control circuit 71. A circuit configuration including a liquid crystal display device 5 and a sub-control circuit 72 that controls the speakers 21L and 21R is shown.

  The main control circuit 71 includes a microcomputer 30 disposed on a circuit board as a main component, and is added with a circuit for random number sampling. The microcomputer 30 includes a CPU 31 that performs a control operation according to a preset program (here, including a game test program for performing a game operation and a test operation using a test firing machine), a ROM 32 and a RAM 33 that are storage means, and will be described later. And various counters (not shown) such as a game shortest time measuring counter, an interrupt counter, and an electromagnetic counter.

  Connected to the CPU 31 are a clock pulse generation circuit 34 and a frequency divider 35 for generating a reference clock pulse, and a random number generator 36 and a sampling circuit 37 for generating a random number to be sampled. As a means for random number sampling, random number sampling may be executed in the microcomputer 30, that is, on the operation program of the CPU 31. In that case, the random number generator 36 and the sampling circuit 37 can be omitted, or can be left as a backup for the random number sampling operation.

  The ROM 32 of the microcomputer 30 stores a probability lottery table (shown in FIG. 4) used for determination of random number sampling performed every time the start lever 6 is operated (start operation), and the reel stop mode according to the stop button operation. The winning combination selection table for stopping (shown in FIG. 5), various control commands (commands), and the like are stored. This control command includes a stop command signal (corresponding to a reel stop command) for commanding the reel 3 to stop, a game start command signal (corresponding to a start command), a reel stop permission command, a winning command, and the like. Here, the sub control circuit 72 does not transmit commands, information, or the like to the main control circuit 71, and communication is performed in one direction from the main control circuit 71 to the sub control circuit 72. The RAM 33 includes a reel stop permission flag, a medal insertion flag, a medal insertion permission flag, a winning flag indicating a winning combination, a reel identifier (corresponding to a reel index) indicating a reel to be controlled, a medal payout flag, a hopper driving flag, and the like. Various information is stored.

  In the circuit of FIG. 6, BET lamps (1-BET lamp 9 a, 2-BET lamp 9 b, maximum BET lamp 9 c) and an information display section are the main actuators whose operation is controlled by a control signal from the microcomputer 30. 18, a hopper (including a drive unit for payout) 40 that stores medals and pays out a predetermined number of medals according to a command from the hopper drive circuit 41, a stepping motor 49L that rotationally drives the reels 3L, 3C, 3R, 49C and 49R.

  Furthermore, a motor drive circuit 39 that drives and controls the stepping motors 49L, 49C, and 49R, a hopper drive circuit 41 that drives and controls the hopper 40, a lamp drive circuit 45 that drives and controls the BET lamps 9a, 9b, and 9c, and the information display unit 18 A display unit drive circuit 48 that controls the driving of the CPU 31 is connected to the output unit of the CPU 31 via an I / O port (input / output port) 38. Each of these drive circuits receives a control signal such as a drive command output from the CPU 31, and controls the operation of each actuator.

  The main input signal generating means for generating an input signal necessary for the microcomputer 30 to generate a control command includes a start switch 6S, a 1-BET switch 11, a 2-BET switch 12, a maximum BET switch 13, There are a C / P switch 14, a medal sensor 22S, a reel stop signal circuit 46, a reel position detection circuit 50, and a payout completion signal circuit 51.

  The start switch 6S detects the operation of the start lever 6. The medal sensor 22S detects medals inserted into the medal insertion slot 22. The reel stop signal circuit 46 generates a stop signal in response to the operation of each stop button 7L, 7C, 7R. The reel position detection circuit 50 receives a pulse signal from the reel rotation sensor and supplies a signal (corresponding to a reel index signal) for detecting the position of each reel 3L, 3C, 3R to the CPU 31. The payout completion signal circuit 51 generates a signal for detecting completion of medal payout when the count value (the number of medals paid out from the hopper 40) of the medal detection unit 40S reaches the designated number data.

  Further, a CR board 130 is connected to the output unit of the CPU 31 via the I / O port 38 as main input signal generating means for generating an input signal necessary for the microcomputer 30 to generate a control command. . The CR board 130 is configured to exchange signals with the card reader unit, the display unit 130a, the card return button 130b, and the operation button 130c described above. The operation of the operation button 130c designates the payout of a predetermined number of medals. When this is done, information on the number of medals is transmitted to the CPU 31 as a CR signal.

  Further, an I / F board (interface board) 100 is used as an interface means when the microcomputer 30 communicates input / output signals necessary for the trial test with the microcomputer 124 of the test test machine 120 (shown in FIG. 7). Is connected to the CPU 31 via the I / O port 38 via a predetermined connector.

  In the circuit of FIG. 6, during the game, the random number generator 36 generates a random number belonging to a certain numerical range, and the sampling circuit 37 samples one random number at an appropriate timing after the start lever 6 is operated. To do. The winning combination is determined based on the random number thus sampled and the probability lottery table stored in the ROM 32.

  After the rotation of the reels 3L, 3C, 3R is started, the number of drive pulses supplied to each of the stepping motors 49L, 49C, 49R is counted, and the counted value is written in a predetermined area of the RAM 33. From the reels 3L, 3C, 3R, reset pulses are obtained every rotation, and these pulses are input to the CPU 31 via the reel position detection circuit 50. The count value of the drive pulse counted in the RAM 33 is cleared to “0” by the reset pulse thus obtained. As a result, the RAM 33 stores a count value corresponding to the rotation position within the range of one rotation for each of the reels 3L, 3C, and 3R.

  A symbol table (not shown) is stored in the ROM 32 in order to associate the rotational positions of the reels 3L, 3C, and 3R described above with the symbols drawn on the outer peripheral surface of the reel. In this symbol table, the code numbers sequentially given for each fixed rotation pitch of each reel 3L, 3C, 3R with reference to the rotation position where the reset pulse is generated are provided corresponding to each code number. Is associated with a symbol code indicating the symbol.

  Further, a winning symbol combination table (not shown) is stored in the ROM 32. In this winning symbol combination table, a winning symbol combination, a winning medal payout number, and a winning determination code representing the winning are associated with each other. The winning symbol combination table is referred to when the left reel 3L, the center reel 3C, and the right reel 3R are controlled to stop and when the winning confirmation is made after all the reels 3L, 3C, and 3R are stopped.

  Based on the lottery process (probability lottery process) based on the random number sampling, the CPU 31 operates the operation signal sent from the reel stop signal circuit 46 at the timing when the player operates the stop buttons 7L, 7C, 7R, and the stop control table ( (Not shown), a signal for controlling the reels 3L, 3C, 3R to stop (corresponding to a stop command signal) is sent to the motor drive circuit 39.

  In the stop mode indicating the winning combination of the winning combination, the CPU 31 supplies a payout command signal to the hopper driving circuit 41 and pays out a predetermined number of medals from the hopper 40. At this time, the medal detection unit 40S counts the number of medals to be paid out from the hopper 40, and when the count value reaches a designated number, a medal payout completion signal is input to the CPU 31. Thereby, CPU31 stops the drive of the hopper 40 via the hopper drive circuit 41, and complete | finishes a medal payout process.

  FIG. 7 shows the configuration of a test fire test system in which the pachislot machine 1 and the test fire test machine 120 are connected via the I / F board 100. Here, the test firing test machine 120 communicates with the pachislot machine 1 to exchange various test signals, accumulates and analyzes communication records, and evaluates the performance of the pachislot machine 1. In addition, the I / F board 100 ensures connection compatibility by controlling interface signals (corresponding to various test signals) between the pachislot machine 1 and the test firing test machine 120. It should be noted that the various test signals used in the test fire test machine 120 have versatility, and the various test signals used in the pachislot machine 1 are not versatile.

  In FIG. 7, the pachislot machine 1 performs a NOT operation on the above-described microcomputer 30 (referred to as a microcomputer in the figure) and the I / O port 38 and the signal from the I / O port 38 to invert the output. Provided for the inverters 61 and 62 and the inverter 63 that performs NOT operation on the signals to the I / O port 38 and inverts the input, and the inverters 61, 62, and 63. And connectors 64, 65, 66 for connecting to the side connectors (referred to as CN in the figure) 110, 111, 112. Here, the connector 64 is used for transmission in a test signal output process (1) in FIG. 13A described later, and the connector 65 is transmitted in a test signal output process (2) in FIG. 13B described later. It is used.

  The I / F board 100 includes connectors 110, 111, and 112 for connecting to the connectors 64, 65, and 66 on the pachislot machine 1 side, and connectors 113 for connecting to the connectors 125, 126, and 127 on the test fire test machine 120 side. , 114, 115 and inverters 101, 102 that perform NOT operation on the signals from the pachislot machine 1 and invert the input, and amplitude modulation circuits that modulate the signals inverted by the inverters 101, 102, etc. Components 116 and 117, photocouplers 107 and 108 that transmit the signals modulated in amplitude by the electronic components 116 and 117 to the test tester 120 side while being electrically insulated, and signals from the photocouplers 107 and 108 Inverters 104 and 105 that perform NOT operation on the test engine and invert the output to the test test machine 120, An inverter 106 that inverts the input by performing a NOT operation on the signal from the tester 120, and a photocoupler 109 that transmits the signal inverted by the inverter 106 to the pachislot machine 1 while electrically insulating it. The inverter 103 performs a NOT operation on the signal from the photocoupler 109 and inverts the output to the pachislot machine 1. Each of the photocouplers 107, 108, and 109 includes a light emitting diode, a phototransistor, and the like. When the light emitting diode emits light, a current (photocurrent) flows between the collector and base of the phototransistor and is turned on. Note that the photocoupler can operate at a higher speed than, for example, an optical MOSFET, and its output changes depending on the input current value. The amplitude modulation circuits of the electronic components 116 and 117 include, for example, an amplifier circuit using transistors, a resonance circuit using L and C, a circuit that feeds back the output of the resonance circuit to an amplifier circuit on the input side, and the like. The current of the frequency component that coincides with is generated.

  The test test machine 120 includes a general-purpose microcomputer 124, connectors 125, 126, 127 for connecting to the connectors 113, 114, 115 on the I / F board 100 side, and the pachislot machine 1 through the I / F board 100. The signals received from the connectors 125 and 126 are subjected to a NOT operation, and the inverters 121 and 122 for inverting the input and the signal from the microcomputer 124 are subjected to a NOT operation, and the pachislot machine 1 is subjected to the NOT operation. And an inverter 127 that inverts the output. The microcomputer 124 has a CPU that performs a control operation in accordance with a preset test test program, and ROM and RAM as storage means.

  In the present embodiment, the I / F board 100 is attached to the pachislot machine 1 and the game test program is executed in the pachislot machine 1 so that the game operation and the test fire test operation can be executed. Further, by attaching a CR unit to the pachislot machine 1, the player can bet medals by inserting medals or paying out medals from the CR cards during game operation.

  The control operation of the pachislot machine 1 configured as described above will be described with reference to FIGS. Here, various interrupt processes such as interrupt processes associated with power interruption, random number update, reset, and periodic interrupts are multiplexed and executed, and priority is given to each interrupt process.

  8 and 9 show reset interrupt processing of the main control circuit 71. FIG.

  First, the CPU 31 performs initialization at power-on (S101). Specifically, initialization of the storage contents of the RAM 33, initialization of communication data, and the like are performed.

  Next, the CPU 31 performs a power-on command set process (S102). Specifically, a power-on command for transmission to a power supply unit (not shown) is written in a predetermined storage area of the RAM 33.

  Next, the CPU 31 erases predetermined storage contents (information of a predetermined storage area (for example, an area for storing an internal winning combination)) in the RAM 33 at the end of the game (S103). Specifically, the data in the writable area of the RAM 33 used in the previous game is erased, the parameters necessary for the next game are written in the write area of the RAM 33, the start address of the sequence program of the next game is designated, I do.

  Next, the CPU 31 performs medal insertion monitoring and start check processing of FIG. 11 described later (S104). Here, it is determined whether there is an input from the CR board 130 based on the operation unit of the CR unit, an input from the medal sensor 22S, and an input from the BET switches 11-13. Further, it is determined whether or not there is an input from the start switch 6S based on the operation of the start lever 6. When these determinations are “YES”, the CPU 31 extracts random numbers for probability lottery as described above (S105).

  Next, the CPU 31 performs a probability lottery process (S106). Specifically, an internal winning combination is determined using the random number extracted in S105 and the probability lottery table.

  Next, the CPU 31 performs a stop winning combination determination process (S107). Specifically, the winning combination for stoppage is determined using the internal winning combination determined in S106 and the winning combination selection table for stoppage.

  Next, the CPU 31 performs a table line selection process (S108). Specifically, a winning line (corresponding to a table line) on which a symbol combination corresponding to the winning combination for stop determined in S107 is arranged is selected.

  Next, the CPU 31 performs a start command set process (S109). Specifically, a start command to be transmitted to the sub control circuit 72 is written in a predetermined storage area of the RAM 33. This start command includes information indicating an internal winning combination and a stopping winning combination.

  Next, the CPU 31 requests the motor drive circuit 39 to start rotation of all reels, and performs rotation processing of all reels 3L, 3C, 3R (S110).

  Next, the CPU 31 performs a game shortest time lapse waiting process (S111). Specifically, the input based on the operation of starting the player's game is invalidated until a predetermined time (for example, a predetermined second (eg, “4.1 seconds”)) has elapsed since the start of the previous game. Perform the process.

  Next, the CPU 31 sets a counter for measuring the shortest game time and counts the elapsed time from the current time (S112).

  Next, the CPU 31 performs a reel stop permission command set process (S113). Specifically, a reel stop permission command for transmission to the sub control circuit 72 is written in a predetermined storage area of the RAM 33, and a stop permission flag for all reels is set.

  Next, the CPU 31 determines whether or not the stop permission flag of all reels is “ON” (S114). If this determination is “YES”, the flow proceeds to S115.

  In S115, the CPU 31 monitors the edge level of the stop button signal and determines whether or not it is “on edge”. This corresponds to determining whether any of the stop buttons 7L, 7C, 7R has been operated. If this determination is “YES”, the process proceeds to S117, and if “NO”, the process proceeds to S116.

  In S116, the CPU 31 determines whether or not the stop button test signal is “ON EDGE”. Specifically, the information on the edge level of the stop button test signal written in the RAM 33 in the periodic interrupt process of FIG. If this determination is “YES”, the process proceeds to S117, and if “NO”, the process proceeds to S115. In S117, the CPU 31 sets the stop permission flag of the target reel to “off”.

  Next, the CPU 31 performs a sliding frame number determination process for the target reel (S118). Specifically, the number of sliding symbols is determined based on the symbol and symbol position of the internal winning combination.

  Next, the CPU 31 rotates the reels 3L, 3C, and 3R corresponding to the stopped stop buttons 7L, 7C, and 7R by the number of sliding frames determined in S115 (S119).

  Next, the CPU 31 sets the target reel stop request flag to “ON” (S120), and further writes a reel stop command for transmission to the sub-control circuit 72 in a predetermined storage area of the RAM 33 (S121). This reel stop command is for instructing an effect by the liquid crystal display device 5 or the like for the stop reel.

  Next, the CPU 31 determines whether or not all reels have been stopped (S122). If this determination is “YES”, the CPU 31 writes an all-reel stop command for transmission to the sub-control circuit 72 in a predetermined storage area of the RAM 33 (S123).

  Next, the CPU 31 performs a winning search process (S124). In this winning search process, a winning flag for identifying a winning combination (winning combination) is set on the basis of the pattern stop mode of the display windows 4L, 4C, 4R. Specifically, the winning combination is identified based on the code number of the symbols arranged along the center line 8c and the winning symbol combination table.

  Next, the CPU 31 performs an erroneous winning check process and determines whether or not the winning flag is normal (S125).

  Next, the CPU 31 performs a winning command set process (S126). Specifically, a winning command to be transmitted to the sub control circuit 72 is written in a predetermined storage area of the RAM 33. This winning command includes information related to the winning combination.

  Next, the CPU 31 determines whether or not the gaming state before winning a prize is a re-gaming state (S127). If this determination is “YES”, the process proceeds to S128, and if “NO”, the process proceeds to S129.

  In S128, the CPU 31 ends the re-gaming state. In S129, the CPU 31 sets the number of medals to be paid out based on the winning combination.

  Next, the CPU 31 determines whether or not the planned medal payout number set in S129 is larger than “0” (S130). If this determination is “YES”, the process proceeds to S131, and if “NO”, the process proceeds to S132.

  In S131, the CPU 31 performs medal credit or payout according to the winning combination. In S132, the CPU 31 determines whether or not the winning combination is RB. If this determination is “YES”, the process proceeds to S133, and if “NO”, the process proceeds to S135.

  In S <b> 133, the CPU 31 deletes RB data as a carryover combination from a predetermined storage area of the RAM 33. Next, the CPU 31 generates the RB gaming state described above (S134).

  In S135, the CPU 31 determines whether or not the RB has been internally won. If this determination is “YES”, the process proceeds to S136, and if “NO”, the process proceeds to S137. In S <b> 136, the CPU 31 writes RB data as a carryover combination in a predetermined storage area of the RAM 33.

  In S137, the CPU 31 determines whether or not the replay is won. If this determination is “YES”, the process proceeds to S138, and if “NO”, the process proceeds to S139. In S138, the CPU 31 generates the replay state described above.

  In S139, the CPU 31 determines whether or not the current gaming state is the RB gaming state. If this determination is “YES”, the process proceeds to S140, and if “NO”, the process proceeds to S103.

  In S140, the CPU 31 determines whether an RB end condition is satisfied. Specifically, it is determined whether the number of games has reached 12 or the number of winnings has reached 8. If this determination is “YES”, the process proceeds to S141, and if “NO”, the process proceeds to S103. In S141, the CPU 31 ends the RB gaming state.

  FIG. 10 shows a periodic interrupt process of the main control circuit 71. This periodic interrupt process occurs every 1.1173 ms.

  First, the CPU 31 saves the register data used in the periodic interrupt process (S201).

  Next, the CPU 31 performs input port check processing (S202). Specifically, it is confirmed whether or not there is an input from the start switch 6S when the start lever 6 is pressed.

  Next, the CPU 31 performs a test signal input process (S203). Specifically, the edge level of the test signal from the test firing tester 120 is monitored, and information on the edge level is written in a predetermined storage area of the RAM 33.

  Next, the CPU 31 performs communication data transmission processing (S203). Specifically, in the reset interrupt process (shown in FIGS. 8 and 9), data written in a predetermined storage area of the RAM 33 is transmitted to the sub control circuit 72.

  Next, the CPU 31 adds “1” to the interrupt counter (S205). Next, the CPU 31 determines whether or not the value of the interrupt counter is an even number (S206). If this determination is “YES”, the process proceeds to S207, and if “NO”, the process proceeds to S208.

  In S207, the CPU 31 performs 7SEG drive control processing. Specifically, the number of stored medals, the number of medals paid out at the time of winning, and the like are displayed on the information display unit 18.

  In S208 to S213, the CPU 31 sets information indicating a reel to be controlled as a reel identifier, and performs a reel control process. That is, information indicating the right reel, information indicating the middle reel, and information indicating the left reel are sequentially set as a reel identifier, and driving of the reel is sequentially controlled.

  Next, the CPU 31 performs a test signal output process (1) shown in FIG. 13A described later (S214). Here, a test signal having a shorter output cycle than the test signal output process (2) is transmitted to the test firing test machine 120.

  Next, the CPU 31 performs a test signal output process (2) shown in FIG. 13B described later (S215). Here, a test signal having a longer output cycle than the test signal output process (1) is transmitted to the test firing test machine 120.

  Next, the CPU 31 subtracts the values of various counters used for reel control (S216), and further performs electromagnetic counter control processing (S217). In this electromagnetic counter control process, the number of appropriate medals inserted from the medal insertion slot 22 is counted. Thereafter, the CPU 31 restores the register data saved in S201 (S218).

  FIG. 11 shows medal insertion monitoring and start check processing (corresponding to S104 in FIG. 8) of the main control circuit 71.

  First, the CPU 31 writes the maximum number of inserted sheets in a predetermined storage area of the RAM 33 according to the gaming state (S301).

  Next, the CPU 31 sets the medal insertion flag to “OFF” in a predetermined storage area of the RAM 33 (S302).

  Next, the CPU 31 sets the medal insertion monitoring state as an “initial state” in a predetermined storage area of the RAM 33 (S303).

  Next, the CPU 31 determines whether or not the current gaming state is the “re-gaming state” (S304). If this determination is “YES”, the process proceeds to S306, and if “NO”, the process proceeds to S305. In S <b> 305, the CPU 31 sets a medal insertion permission flag to “ON” in a predetermined storage area of the RAM 33.

  In S <b> 306, the CPU 31 sets the medal insertion number of the previous unit game as a medal insertion number in a predetermined storage area of the RAM 33. Next, the CPU 31 sets the medal insertion permission flag to “OFF” in a predetermined storage area of the RAM 33 (S307).

  Next, the CPU 31 determines whether or not the medal insertion permission flag is set to “ON” in a predetermined storage area of the RAM 33 (S308). If this determination is “YES”, the process proceeds to S309, and if “NO”, the process proceeds to S319.

  In S309, the CPU 31 determines whether or not the CR signal from the CR board 130 has been received. If this determination is “YES”, the process moves to S310, and if “NO”, the process moves to S311. In the gaming state, the CPU 31 monitors the CR signal. In the test state, the CPU 31 controls the CPU 31 to output a pseudo signal corresponding to the CR signal, and the CPU 31 monitors the pseudo signal. You may do it. With this method, the test firing test machine 120 can cause the pachislot machine 1 to perform a predetermined number of medal payout operations using a CR card without a card and test its performance.

  In S310, the CPU 31 sets a predetermined number as the expected medal payout number in a predetermined storage area of the RAM 33 in accordance with the CR signal. A predetermined number of medals will be betted for each game unit.

  In S311, the CPU 31 performs a medal payout process shown in FIG. Next, the CPU 31 performs medal insertion monitoring processing shown in FIG. 12B described later (S312).

  Next, the CPU 31 determines whether or not the medal insertion monitoring state is set as the “initial state” in a predetermined storage area of the RAM 33 (S313). If this determination is “YES”, the process proceeds to S314, and if “NO”, the process proceeds to S317.

  In S <b> 314, the CPU 31 determines whether or not the medal insertion flag is set to “ON” in a predetermined storage area of the RAM 33. If this determination is “YES”, the process proceeds to S315, and if “NO”, the process proceeds to S317.

  Next, the CPU 31 performs a medal insertion number confirmation process shown in FIG. 12C described later (S315). Next, the CPU 31 sets the medal insertion flag to “OFF” in a predetermined storage area of the RAM 33 (S316).

  In S317, the CPU 31 monitors the edge level of the medal insertion signal from the medal sensor 22S and determines whether or not it is “on edge”. If this determination is “YES”, the process proceeds to S318, and if “NO”, the process proceeds to S319.

  In S318, the CPU 31 performs a medal insertion number confirmation process shown in FIG. 12C described later by a medal insertion signal from the medal sensor 22S.

  Next, the CPU 31 determines whether or not the start permission flag is set to “ON” in the predetermined storage area of the RAM 33 (S319). If this determination is “YES”, the process proceeds to S320, and if “NO”, the process proceeds to S308.

  In S320, the CPU 31 monitors the edge level of the start lever signal and determines whether or not it is “on edge”. If this determination is “YES”, the process proceeds to S321, and if “NO”, the process proceeds to S322.

  In S321, the CPU 31 determines whether or not the start test signal from the test firing test machine 120 is “on edge”. Specifically, the determination is made by reading the edge level information of the test signal written in the predetermined storage area of the RAM 33 in the periodic interrupt process of FIG. If this determination is “YES”, the process proceeds to S322, and if “NO”, the process proceeds to S308. In S322, the CPU 31 sets the start permission flag to “OFF” in a predetermined storage area of the RAM 33.

  Next, the CPU 31 determines whether or not the medal insertion permission flag is set to “ON” in a predetermined storage area of the RAM 33 (S323). If this determination is “NO”, the process proceeds to S301, and if “YES”, the process proceeds to S324. In S324, the CPU 31 sets the medal insertion permission flag to “OFF” in a predetermined storage area of the RAM 33.

  FIG. 12A shows a medal payout process (corresponding to S131 in FIG. 9) of the main control circuit 71.

  First, the CPU 31 sets the medal payout flag to “OFF” in a predetermined storage area of the RAM 33 (S401).

  Next, the CPU 31 sets the hopper drive flag to “ON” in a predetermined storage area of the RAM 33 (S402).

  Next, the CPU 31 monitors the edge level of the medal payout signal from the medal detection unit 40S, and obtains the information on the edge level of the medal payout test signal written in the predetermined storage area of the RAM 33 by the periodic interruption process of FIG. It is determined whether or not any of the signals is “on edge” (S403). If this determination is “YES”, the flow proceeds to S404.

  In S <b> 404, the CPU 31 subtracts “1” from the medal payout scheduled number set in the predetermined storage area of the RAM 33. Next, the CPU 31 sets the medal payout flag to “ON” in a predetermined storage area of the RAM 33 (S405).

  Next, the CPU 31 determines whether or not the medal payout scheduled number set in the medal insertion monitoring and start check processing of FIG. 11 has become “0” (S406). If this determination is “YES”, the flow proceeds to S407. In S407, the CPU 31 sets the hopper drive flag as “OFF” in a predetermined storage area of the RAM 33. Note that if the edge level of the medal payout test signal is “ON EDGE” in S403, the medal-less test is performed with the test firing test machine 120, and therefore no medal payout is performed.

  FIG. 12B shows the medal insertion monitoring process (corresponding to S312 in FIG. 11) of the main control circuit 71.

  First, the CPU 31 monitors a signal from the medal sensor 22S and determines whether or not the medal insertion monitoring state has changed (S501). If this determination is “YES”, the flow proceeds to S502. In S502, the CPU 31 updates the medal insertion monitoring state.

  Next, the CPU 31 determines whether or not the medal insertion monitoring state has changed normally (S503). If this determination is “YES”, the process proceeds to S506, and if “NO”, the process proceeds to S504.

  In S504, the CPU 31 performs error processing such as game stop and error display. Next, the CPU 31 sets an initial state as a medal insertion monitoring state in a predetermined storage area of the RAM 33 (S505).

  In S <b> 506, the CPU 31 determines whether or not the medal insertion monitoring state is set as the “initial state” in a predetermined storage area of the RAM 33. If this determination is “YES”, the flow proceeds to S507. In S <b> 507, the CPU 31 sets the medal insertion flag to “ON” in a predetermined storage area of the RAM 33.

  In the gaming state, the CPU 31 monitors the insertion of medals by the player as described above. However, in the test state, the CPU 31 controls the medal sensor 22S to output a pseudo signal corresponding to the detection signal. The CPU 31 may monitor the pseudo signal. By this method, the test firing test machine 120 can cause the pachislot machine 1 to perform a medal insertion operation without a medal and test its performance.

  FIG. 12C shows the medal insertion number confirmation process (corresponding to S315 in FIG. 11) of the main control circuit 71.

  First, the CPU 31 determines whether the medal insertion number is “0” based on the medal insertion flag (S601). If this determination is “YES”, the process proceeds to S602, and if “NO”, the process proceeds to S603. In S <b> 602, the CPU 31 sets a start permission flag to “ON” in a predetermined storage area of the RAM 33.

  In S603, the CPU 31 determines whether or not the medal insertion number is smaller than the maximum insertion number set in the medal insertion monitoring and start check processing of FIG. If this determination is “YES”, the flow proceeds to S604. In S604, the CPU 31 adds “1” to the number of medals inserted.

  Next, the CPU 31 determines whether or not the medal insertion number is the maximum insertion number (S605). If this determination is “YES”, the flow proceeds to S606. In S <b> 606, the CPU 31 sets the medal insertion permission flag to “OFF” in a predetermined storage area of the RAM 33.

  FIG. 13A shows a test signal output process (1) (corresponding to S214 in FIG. 10) of the main control circuit 71.

  First, the CPU 31 instructs the test firing test machine 120 to perform left reel motor phase test signals (1) to (4) based on left reel pulse data used in reel control processing (corresponding to S208 and S209 in FIG. 10). Is transmitted (S701).

  Next, the CPU 31 sends the intermediate reel motor phase test signals (1) to (4) to the test firing test machine 120 based on the intermediate reel pulse data used in the reel control processing (corresponding to S210 and S211 in FIG. 10). Either of them is transmitted (S702).

  Next, the CPU 31 sends the right reel motor phase test signals (1) to (4) to the test firing test machine 120 based on the right reel pulse data used in the reel control processing (corresponding to S212 and S213 in FIG. 10). Either of them is transmitted (S703).

  FIG. 13B shows a test signal output process (2) of the main control circuit 71 (corresponding to S215 in FIG. 10).

  First, the CPU 31 transmits an insertion request lamp test signal to the test fire test machine 120 based on the medal insertion permission flag set in the medal insertion monitoring and start check processing of FIG. 11 (S801).

  Next, the CPU 31 transmits an RB operation test signal to the test fire test machine 120 based on whether or not the current gaming state is the RB gaming state (S802).

  Next, the CPU 31 transmits a re-game operation test signal to the test test machine 120 based on whether or not the current game state is the re-game state (S803).

  Next, the CPU 31 transmits a start permission test signal to the test firing test machine 120 based on the start permission flag set in the medal insertion number confirmation process of FIG. 12C (S804).

  Next, the CPU 31 transmits a medal insertion number test signal based on the medal insertion number set in the medal insertion number confirmation processing of FIG. 12C to the test firing test machine 120 (S805). Here, a medal insertion number test signal corresponding to the one in which one medal was first inserted (1 BET) is transmitted, and when the test firing test with 1 BET is completed a predetermined number of times, this corresponds to that in which two medals were inserted (2 BET). A medal insertion number test signal is transmitted, and when the test firing test with 2 BETs is completed a predetermined number of times, a medal insertion number test signal corresponding to the maximum number of medals inserted (maximum BET) is transmitted.

  Next, the CPU 31 transmits a left reel stop permission test signal to the test firing test machine 120 based on the left reel stop permission flag set in the reset interrupt process of FIG. 8 (S806).

  Next, the CPU 31 transmits a middle reel stop permission test signal to the test firing test machine 120 based on the middle reel stop permission flag set in the reset interrupt process of FIG. 8 (S807).

  Next, the CPU 31 transmits a right reel stop permission test signal to the test firing test machine 120 based on the right reel stop permission flag set in the reset interrupt process of FIG. 8 (S808).

  Next, the CPU 31 transmits a hopper drive test signal to the test firing test machine 120 based on the hopper drive flag set in the medal payout process of FIG. 12A (S809).

  Next, the CPU 31 determines whether or not the medal payout flag is set to “ON” in the medal payout process of FIG. 12A (S810). If this determination is “YES”, the process moves to S811, and if “NO”, the process moves to S813.

  In S811, the CPU 31 sets the medal payout flag to “OFF” in a predetermined storage area of the RAM 33. Next, the CPU 31 initializes a medal payout test timer (S812).

  Next, the CPU 31 determines whether or not the value of the medal payout test timer is greater than “0”. If this determination is “YES”, the process moves to S815, and if “NO”, the process moves to S814. In S <b> 814, the CPU 31 transmits an ON signal as a medal payout notification test signal to the test firing test machine 120.

  In S815, the CPU 31 transmits an ON signal as a medal payout notification test signal to the test fire testing machine 120. The medal payout notification test signal is a test signal for notifying the test firing test machine 120 that the medal has been paid out in a pseudo manner, and no medal is actually paid out.

  Next, the CPU 31 subtracts “1” from the value of the medal payout test timer (S816), and then the left reel index signal used in the reel control process (corresponding to S208 and S209 in FIG. 10) for the test firing test machine 120. The left reel index test signal is transmitted based on (S817).

  Next, the CPU 31 transmits a middle reel index test signal to the test firing test machine 120 based on the middle reel index signal used in the reel control processing (corresponding to S210 and S211 in FIG. 10) (S818).

  Next, the CPU 31 transmits a right reel index test signal to the test firing test machine 120 based on the right reel index signal used in the reel control processing (corresponding to S212 and S213 in FIG. 10) (S819).

  Next, the CPU 31 transmits a winning combination test signal to the test fire test machine 120 based on the internal winning combination determined in the probability lottery process (corresponding to S106 in FIG. 8) (S820).

  According to the pachislot machine 1 according to the embodiment of the present invention as described above, in a state where it is connected to the test firing test machine 120, a test signal related to game operation is exchanged with the test firing test machine 120, and the test firing test machine is provided. In a state in which the medals are inserted in a state in which the medals are inserted, a connection that intervenes between the test firing test machine 120 and the pachislot machine 1 and realizes connection compatibility of both signals is provided. As test control means for controlling to respond to the test signals when receiving the test signals regarding the gaming operation from the inverters 61 to 63, the connectors 64 to 66 and the I / F board 100 as the means, and the test fire test machine 120 Since the game operation is reproduced without inserting a medal using the test signal, the performance test of the pachislot machine 1 is automated. Doo is an effect that can be expected. This configuration corresponds to an embodiment of the invention according to claim 1.

  In addition, according to the present embodiment, the I / F board 100 includes electronic components 116 and 117 such as an amplitude modulation circuit that modulates a test signal from the pachislot machine 1 to the test fire test machine 120 so as to be suitable for transmission. By providing the photocouplers 107 and 108 that transmit the modulated test signal while being electrically cut off, and the photocoupler 109 that sends the test signal from the test fire tester 120 to the pachislot machine 1 while being electrically cut off. The effect of preventing malfunction due to erroneous input is expected. Also, by providing a photocoupler for transmission and reception, a test signal that requires modulation (here, a test signal transmitted from the pachislot machine 1) and a test signal that does not require modulation (here, a versatile test test) The test signal from the machine 120) can be divided and communication can be efficiently performed. This configuration corresponds to an embodiment of the invention according to claim 2.

  Furthermore, according to the present embodiment, the medal sensor 22S and the microcomputer 30 serving as input value counting means for counting the number of medals inserted by the player from the predetermined medal insertion slot 22, and the game start according to the operation by the player. A start switch 6S and a microcomputer 30 as game start command means for outputting a command signal, and stop buttons 7L, 7C and 7R as a stop command means for outputting a stop command signal in response to an operation by the player, a reel stop signal circuit 46 and microcomputer 30; reels 3L, 3C, and 3R for variably displaying a plurality of identification information necessary for the game; drive stop control means for driving the reel by a game start command signal and stopping the reel by a stop command signal Stepping motors 49L, 49C, 49R, motor drive circuit 39 and motor The microcomputer 30 as a payout command means for outputting a payout command signal, and a payout command signal when the stop mode of the reels stopped by the blackout computer 30 and the motor drive circuit 39 or the like by the stop command signal is a predetermined stop mode. The hopper 40 for paying out medals, inverters 61 to 63, connectors 64 to 66 and I / F as connection means that are interposed between the test fire test machine 120 and the pachislot machine 1 to realize connection compatibility of both signals. A board 100 and a microcomputer 30 as a test control means for controlling to test the game operation by responding to the test signal when the test signal related to the game operation is received from the board 100 The I / F board 100 transmits a test signal from the pachislot machine 1 to the test fire test machine 120. The electronic components 116 and 117 such as an amplitude modulation circuit that performs amplitude modulation as described above, the photocouplers 107 and 108 that transmit the amplitude-modulated test signal while being electrically cut off, and the test fire tester 120 to the pachislot machine 1 By providing the photocoupler 109 that transmits the test signal while electrically shutting off the test signal, it is possible to perform transmission at a higher speed than when, for example, an optical MOSFET is used. In addition, the test lever 120 transmits a test signal corresponding to a game start command signal and a stop command signal to the pachislot machine 1, thereby pressing the start lever 6 and the stop buttons 7L, 7C, 7R during the test. The effect of eliminating the need is also expected. Further, a test signal corresponding to a payout command signal is transmitted from the test firing test machine 120 to the pachislot machine 1, and the number of medals paid out in advance in the game test program is notified from the pachislot machine 1 to the test fire testing machine 120. By doing in this way, the effect that the paying-out operation of the hopper 40 becomes unnecessary is also expected. This configuration corresponds to an embodiment of the invention according to claim 3.

  In addition, according to the present embodiment, the test fire test machine 120 tests the gaming operation of the pachislot machine 1 by exchanging the various test signals described above with the pachislot machine 1, and tabulates the test results. Detailed error locations can be detected. Moreover, the test firing test machine 120 may determine whether or not the result is a result of encouraging euphoria based on the totaled result in addition to the game state inspection.

  In the above-described embodiment, the case where the game test program that allows the game operation by the pachislot machine 1 and the test operation by the test firing test machine 120 to be performed together as the program of the pachislot machine 1 has been described. In addition to this, the same effect can be obtained by using a game program for performing a game operation and a test program for performing a test operation, and appropriately switching both of them on the program of the pachislot machine 1 or by manual operation of the operator. Expected.

  In the above-described embodiment, the case where error processing is performed when the medal insertion monitoring state does not change normally (corresponding to S503 and S504 in FIG. 12B) has been described. It is not a thing. That is, when the pachislot machine 1 is installed in the amusement store, the connectors 64 to 66 are in a closed state, so that no test signal is actually input from the test firing test machine 120.

  However, when a signal corresponding to a start test signal from the test firing test machine 120 and a hopper payout signal from the medal detection unit 40S of the hopper 40 is detected during a non-test, such as during a game, the CPU 31 detects an illegal fraud from the outside. Even if it is determined that a signal operation has been performed and error notification is performed, the same effect can be expected. Alternatively, during a non-test such as during a game, first, the medal payout test signal from the test firing test machine 120 is “off edge”, the hopper payout signal from the medal detection unit 40S of the hopper 40 becomes “on edge”, and then the test fire When both the medal insertion number test signal for the testing machine 120 and the medal payout test signal are “on edge”, the CPU 31 determines that an illegal signal operation from the outside has been performed, and issues an error notification. However, the same effect is expected.

1 is a perspective view of a pachislot machine according to an embodiment of the present invention. It is a figure which shows the symbol row | line | column on the reel which concerns on one Embodiment of this invention. It is a figure which shows the relationship between the combination which concerns on one Embodiment of this invention, a symbol combination, and the number of payout. It is a figure explaining the probability lottery table which concerns on one Embodiment of this invention. It is a figure explaining the winning combination selection table for a stop concerning one embodiment of the present invention. It is a block diagram of the main control circuit concerning one embodiment of the present invention. 1 is a block diagram of a test firing tester, an I / F board, and a pachislot machine according to an embodiment of the present invention. It is a part of flowchart of the reset interruption process which concerns on one Embodiment of this invention. It is a part of flowchart of the reset interruption process which concerns on one Embodiment of this invention. It is a flowchart of the regular interruption process which concerns on one Embodiment of this invention. It is a flowchart of medal insertion monitoring and start check processing according to an embodiment of the present invention. 5 is a flowchart of a medal payout process, a medal insertion monitoring process, and a medal insertion number confirmation process according to an embodiment of the present invention. It is a flowchart of a test signal output process (1) and a test signal output process (2) according to an embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pachislot machine 2 Cabinet 3L, 3C, 3R Reel 4L, 4C, 4R Display window 5 Liquid crystal display device 6 Start lever 7L, 7C, 7R Stop button 30 Microcomputer 31 CPU
32 ROM
33 RAM
71 Main control circuit 72 Sub control circuit 100 I / F board 120 Test fire tester 130 CR board

Claims (3)

When connected to the testing machine, it exchanges test signals related to gaming operations with the testing machine, and when not connected to the testing machine, it is a gaming machine that performs gaming operations when a gaming value is input. ,
A connection means for interfacing between the test machine and the gaming machine to realize the compatibility of both signals, and a response to the test signal when receiving a test signal relating to a gaming operation from the test machine via the connection means And a test control means for controlling the game machine. In the gaming machine according to claim 1,
The connection means includes a modulation means for modulating a test signal from the gaming machine to the test machine so as to be suitable for transmission, and a first cut-off transmission means for transmitting the test signal modulated by the modulation means while being electrically cut off. And a second cutoff transmission means for transmitting a test signal from the test machine to the gaming machine while being electrically cut off. Input value counting means for counting the number of game values inserted by a player from a predetermined slot, game start command means for outputting a game start command signal in response to an operation by the player, and stop in response to an operation by the player Stop command means for outputting a command signal, fluctuation display means for fluctuating and displaying a plurality of identification information necessary for the game, driving for driving the fluctuation display means by the game start command signal, and stopping the fluctuation display means by the stop command signal When the stop control means and the stop mode of the variable display means stopped by the drive stop control means by the stop command signal are the predetermined stop mode, the payout command means for outputting the payout command signal, and the predetermined game by the payout command signal A game value payout means for paying out value, a connection means for interfacing between the test machine and the game machine to realize connection compatibility of both signals, and a game from the test machine via the connection means Upon receiving a test signal relating to the operation, and a test control means for controlling so as to test a game operation by responding to the test signal,
The connection means includes an amplitude modulation circuit that modulates the test signal from the gaming machine to the test machine so as to be suitable for transmission, and a first signal that transmits the test signal that is amplitude-modulated by the amplitude modulation circuit while being electrically cut off. A gaming machine comprising: a photocoupler; and a second photocoupler that transmits a test signal from the testing machine to the gaming machine while being electrically cut off.

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