JP2006005268A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of enhancing the relief rate of fuses by normally activating non-blown fuses. <P>SOLUTION: In the semiconductor device including a guard ring and a plurality of the fuses provided to the inside of the guard ring, an etching groove is provided between a plurality of the fuses. Then it is preferable that a material with high moisture-proof is embedded in each etching groove. Or lower layer wires respectively interconnecting a plurality of the fuses and an internal circuit at the outside of the guard ring are provided to the lower part of the guard ring, and upper layer wires respectively interconnecting a plurality of the fuses and the internal circuit are provided to an upper part of the guard ring. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a plurality of fuses provided inside a guard ring.

  2. Description of the Related Art In recent years, in a semiconductor memory device, with an increase in storage capacity, it has been common practice to provide a redundancy circuit to relieve a few bits of defects and improve yield. As a method of switching to this redundant circuit, a method of blowing a fuse that is a part of the redundant circuit by laser irradiation is often used.

  In order to prevent moisture from entering the internal circuit of the semiconductor device from the blown area of the fuse, a guard ring is provided so as to surround the blown area of the fuse (for example, Patent Document 1).

  Further, since the pitch increases when one fuse is arranged in one guard ring, a structure in which a plurality of fuses are arranged in one guard ring is used.

  FIG. 5 shows a top view of a conventional semiconductor device. In the figure, two fuses 12 and 13 are arranged in the guard ring 11. The fuse 13 is blown by an energy beam irradiation method.

  6 is a cross-sectional view taken along the line AA ′ of FIG. 5, and FIG. 7 is a cross-sectional view taken along the line BB ′ of FIG. In the figure, an insulating film 15 is formed on a semiconductor substrate 14, and a guard ring 11 and fuses 12 and 13 are provided in the insulating film 15. A passivation film 16 is formed on the insulating film 15. In the passivation film 16, an opening 17 is provided in a region corresponding to the melted region of the fuses 12 and 13.

  The fuses 12 and 13 are connected to the lower layer wiring 19 by a multilayer wiring 18 in which a plurality of wirings and vias are stacked in the vertical direction. The lower layer wiring 19 is disposed below the guard ring 11 and extends from the inside of the guard ring 11 to the outside. The multilayer wiring 20 is connected to the internal circuit.

JP-A-9-69571

  The moisture resistance deteriorates around the blow part of the fuse. Therefore, in the conventional semiconductor device, moisture 21 enters from the cut portion of the blown fuse 13, passes through the insulating film 15, reaches the fuse 12 in the same guard ring 11, and does not blow. A disconnection failure is likely to occur in the via portion of the multilayer wiring 18 that connects the lower layer wiring 19 to each other. As a result, there is a problem that a fuse that is not blown cannot be operated normally and the repair rate is deteriorated.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of operating a fuse that is not blown normally and improving the repair rate.

  The semiconductor device according to the present invention includes a guard ring, a plurality of fuses provided inside the guard ring, and an etching groove provided between the plurality of fuses. Other features of the present invention will become apparent below.

  According to the present invention, a fuse that is not blown can be operated normally, and the relief rate can be improved.

Embodiment 1 FIG.
FIG. 1 shows a top view of the semiconductor device according to the first embodiment of the present invention. In the figure, two fuses 12 and 13 of a predetermined pattern made of polycrystalline silicon are arranged in a guard ring 11. The fuse 13 is blown by the energy beam irradiation method.

  FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. In the figure, an insulating film 15 made of a silicon dioxide film, a BPSG film or the like is formed on a semiconductor substrate 14. A guard ring 11 and fuses 12 and 13 are provided in the insulating film 15. A passivation film 16 is formed on the insulating film 15. In the passivation film 16, an opening 17 is provided in a region corresponding to the melted region of the fuses 12 and 13.

  The fuses 12 and 13 are respectively connected to separate lower layer wirings 19 by a multilayer wiring 18 in which a plurality of wirings and vias are stacked in the vertical direction. The lower layer wiring 19 is disposed below the guard ring 11 and extends from the inside of the guard ring 11 to the outside. The multi-layer wiring 20 is connected to an internal circuit outside the guard ring. That is, the lower layer wiring 19 connects the fuses 12 and 13 to the internal circuit, respectively.

  Here, in the semiconductor device according to the first embodiment, the etching groove 22 is provided between the fuses 12 and 13. The depth of the etching groove 22 extends from the fuses 12 and 13 to several layers below.

  As a result, the fuses can be isolated from each other, and the penetration of moisture 21 from the blown fuse 13 into the unblowed fuse 12 can be prevented. Then, the fuse 12 that is not blown can be operated normally to improve the relief rate.

  It is preferable to embed a highly moisture-resistant material 23 in the etching groove 22. As a material to be embedded, a material having higher moisture resistance than the insulating film 15 such as Cu, Al, TEOS or the like is used. As a result, a moisture-proof wall without a gap can be formed, and moisture intrusion into the unblowed fuse can be more reliably prevented.

  Since a plurality of fuses are arranged in one guard ring, fuses can be arranged at a narrower pitch than a structure in which one fuse is arranged in one guard ring, and the size is reduced. be able to.

  In the above example, the case where two fuses are provided inside the guard ring has been described. However, the present invention is not limited to this, and the present invention can be applied to a case where three or more fuses are provided. it can. In this case, a moisture barrier is provided between the plurality of fuses.

Embodiment 2. FIG.
FIG. 3 is a top view of the semiconductor device according to the second embodiment of the present invention. 4 is a cross-sectional view taken along the line BB ′ of FIG. Constituent elements similar to those in FIGS.

  In the semiconductor device according to the second embodiment, the upper layer wiring 24 that connects the fuses 12 and 13 and the internal circuit is provided above the guard ring 11.

  In this way, by providing both the lower layer wiring and the upper layer wiring and providing two connection paths for the fuse and the internal circuit, even if one side is disconnected, the other connection path is not disconnected. The fuse operates normally, and the relief rate can be improved.

  Since moisture intrusion is likely to occur in the lower layer of the fuse, it is effective to connect the fuse to the internal circuit via the upper layer wiring above the guard ring.

It is a top view which shows the semiconductor device which concerns on Embodiment 1 of this invention. It is sectional drawing in AA 'of FIG. It is a top view which shows the semiconductor device which concerns on Embodiment 2 of this invention. It is sectional drawing in BB 'of FIG. It is a top view which shows the conventional semiconductor device. It is sectional drawing in AA 'of FIG. It is sectional drawing in BB 'of FIG.

Explanation of symbols

11 Guard rings 12, 13 Fuse 15 Insulating film 19 Lower layer wiring 22 Etching groove 23 High moisture resistant material 24 Upper layer wiring

Claims (3)

Guard rings,
A plurality of fuses provided inside the guard ring;
A semiconductor device having an etching groove provided between the plurality of fuses.   The semiconductor device according to claim 1, wherein a material having high moisture resistance is embedded in the etching groove. A guard ring provided in the insulating film;
A plurality of fuses provided inside the guard ring;
A lower layer wiring provided below the guard ring, each connecting the plurality of fuses and an internal circuit outside the guard ring;
A semiconductor device comprising upper layer wirings provided above the guard ring and respectively connecting the plurality of fuses and the internal circuit.

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