JP2006005207A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2006005207A5 JP2006005207A5 JP2004180722A JP2004180722A JP2006005207A5 JP 2006005207 A5 JP2006005207 A5 JP 2006005207A5 JP 2004180722 A JP2004180722 A JP 2004180722A JP 2004180722 A JP2004180722 A JP 2004180722A JP 2006005207 A5 JP2006005207 A5 JP 2006005207A5
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- semiconductor
- layer
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Claims (18)
（ａ）第１導電型の半導体基板と、
（ｂ）前記半導体基板上に形成されたコレクタ用の第２導電型の第１半導体層と、
（ｃ）前記第１半導体層上に形成され、前記第１半導体層より不純物濃度が低いコレクタ用の第２導電型の第２半導体層と、
（ｄ）前記第２半導体層内に形成され、前記第１半導体層と前記第２半導体層とを電気的に接続し、前記第２半導体層より不純物濃度が高い第３半導体層と、
（ｅ）前記第２半導体層上に形成されたベース用の第１導電型の第４半導体層と、
（ｆ）前記第４半導体層内に形成されたエミッタ用の第２導電型の第５半導体層と、
（ｇ）前記第４半導体層および前記第５半導体層より上層に形成された第１配線層と、
（ｈ）前記第１配線層より上層に形成され、前記第１半導体層および前記第２半導体層と電気的に接続されたコレクタ用の第１電極と、
（ｉ）前記第１配線層より上層に形成され、前記第４半導体層と電気的に接続されたベース用の第２電極と、
（ｊ）前記第１配線層より上層に形成され、前記第５半導体層と電気的に接続されたエミッタ用の第３電極とを備え、
前記第１配線層に含まれ、前記第１電極下および前記第２電極下のうちの選択された１つ以上に配置された第１配線は、基準電位と電気的に接続されていることを特徴とする半導体装置。 Have bipolar transistors,
(A) a first conductivity type semiconductor substrate;
(B) a first semiconductor layer of a second conductivity type for collector formed on the semiconductor substrate;
(C) a second conductive type second semiconductor layer formed on the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer;
(D) a third semiconductor layer formed in the second semiconductor layer, electrically connecting the first semiconductor layer and the second semiconductor layer, and having a higher impurity concentration than the second semiconductor layer;
(E) a fourth semiconductor layer of the first conductivity type for base formed on the second semiconductor layer;
(F) a fifth semiconductor layer of the second conductivity type for emitter formed in the fourth semiconductor layer;
(G) a first wiring layer formed above the fourth semiconductor layer and the fifth semiconductor layer;
(H) a first electrode for a collector formed above the first wiring layer and electrically connected to the first semiconductor layer and the second semiconductor layer;
(I) a second electrode for a base formed above the first wiring layer and electrically connected to the fourth semiconductor layer;
(J) a third electrode for emitter formed above the first wiring layer and electrically connected to the fifth semiconductor layer;
The first wiring included in the first wiring layer and disposed at one or more selected below the first electrode and the second electrode is electrically connected to a reference potential. A featured semiconductor device.
前記第１配線は、前記第５半導体層および前記第３電極と電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The semiconductor device, wherein the first wiring is electrically connected to the fifth semiconductor layer and the third electrode.
前記第５半導体層および前記第３電極は、前記半導体基板に電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 2,
The semiconductor device, wherein the fifth semiconductor layer and the third electrode are electrically connected to the semiconductor substrate.
通信機器のフロントエンド部における低ノイズ増幅器、低ノイズ増幅器バッファ、ドライバおよび電力増幅器のうちの１つ以上に用いることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A semiconductor device characterized by being used for one or more of a low noise amplifier, a low noise amplifier buffer, a driver, and a power amplifier in a front end portion of a communication device.
前記低ノイズ増幅器および低ノイズ増幅器バッファは、１つの半導体チップ内に形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 4.
The semiconductor device, wherein the low noise amplifier and the low noise amplifier buffer are formed in one semiconductor chip.
前記ドライバおよび前記電力増幅器は、１つの半導体チップ内に形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 4.
The driver and the power amplifier are formed in one semiconductor chip.
前記通信機器の信号の周波数帯は、５ＧＨｚ帯または２ＧＨｚ帯であることを特徴とする半導体装置。 The semiconductor device according to claim 4.
A frequency band of a signal of the communication device is a 5 GHz band or a 2 GHz band.
前記半導体基板上には複数層の配線層が形成され、
前記第１配線層は最下層の配線層であることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A plurality of wiring layers are formed on the semiconductor substrate,
The semiconductor device according to claim 1, wherein the first wiring layer is a lowermost wiring layer.
前記第１配線層は金属を主成分とすることを特徴とする半導体装置。 The semiconductor device according to claim 8.
The semiconductor device, wherein the first wiring layer contains a metal as a main component.
前記半導体基板上には複数層の配線層が形成され、
前記第１配線層は最上層の配線層であることを特徴とする半導体装置。 The semiconductor device according to claim 1,
A plurality of wiring layers are formed on the semiconductor substrate,
The semiconductor device according to claim 1, wherein the first wiring layer is an uppermost wiring layer.
前記第１配線は、前記第１電極下にのみ配置され、
前記バイポーラトランジスタの出力は１Ｗ以上であることを特徴とする半導体装置。 The semiconductor device according to claim 1,
The first wiring is disposed only under the first electrode,
The semiconductor device according to claim 1, wherein an output of the bipolar transistor is 1 W or more.
（ａ）第１導電型の半導体基板と、
（ｂ）前記半導体基板上に形成されたコレクタ用の第２導電型の第１半導体層と、
（ｃ）前記第１半導体層上に形成され、前記第１半導体層より不純物濃度が低いコレクタ用の第２導電型の第２半導体層と、
（ｄ）前記第２半導体層内に形成され、前記第１半導体層と前記第２半導体層とを電気的に接続し、前記第２半導体層より不純物濃度が高い第３半導体層と、
（ｅ）前記第２半導体層上に形成されたベース用の第１導電型の第４半導体層と、
（ｆ）前記第４半導体層内に形成されたエミッタ用の第２導電型の第５半導体層と、
（ｇ）前記第４半導体層および前記第５半導体層より上層に形成された第１導電体層と、
（ｈ）前記第１導電体層より上層に形成され、前記第１半導体層および前記第２半導体層と電気的に接続されたコレクタ用の第１電極と、
（ｉ）前記第１導電体層より上層に形成され、前記第４半導体層と電気的に接続されたベース用の第２電極と、
（ｊ）前記第１導電体層より上層に形成され、前記第５半導体層と電気的に接続されたエミッタ用の第３電極とを備え、
前記第１導電体層は、前記第４半導体層と電気的に接続された第１導電体片と、前記第１電極下および前記第２電極下のうちの選択された１つ以上に配置された第２導電体片とを含み、
前記第２導電体片は、基準電位と電気的に接続されていることを特徴とする半導体装置。 Have bipolar transistors,
(A) a first conductivity type semiconductor substrate;
(B) a first semiconductor layer of a second conductivity type for collector formed on the semiconductor substrate;
(C) a second conductive type second semiconductor layer formed on the first semiconductor layer and having a lower impurity concentration than the first semiconductor layer;
(D) a third semiconductor layer formed in the second semiconductor layer, electrically connecting the first semiconductor layer and the second semiconductor layer, and having a higher impurity concentration than the second semiconductor layer;
(E) a fourth semiconductor layer of the first conductivity type for base formed on the second semiconductor layer;
(F) a fifth semiconductor layer of the second conductivity type for emitter formed in the fourth semiconductor layer;
(G) a first conductor layer formed above the fourth semiconductor layer and the fifth semiconductor layer;
(H) a first electrode for a collector formed above the first conductor layer and electrically connected to the first semiconductor layer and the second semiconductor layer;
(I) a second electrode for a base formed above the first conductor layer and electrically connected to the fourth semiconductor layer;
(J) a third electrode for emitter formed above the first conductor layer and electrically connected to the fifth semiconductor layer;
The first conductor layer is disposed on a first conductor piece electrically connected to the fourth semiconductor layer, and on one or more selected below the first electrode and the second electrode. A second conductor piece,
The semiconductor device, wherein the second conductor piece is electrically connected to a reference potential.
前記第２導電体片は、前記第５半導体層および前記第３電極と電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 12, wherein
The semiconductor device, wherein the second conductor piece is electrically connected to the fifth semiconductor layer and the third electrode.
前記第５半導体層および前記第３電極は、前記半導体基板に電気的に接続されていることを特徴とする半導体装置。 The semiconductor device according to claim 13.
The semiconductor device, wherein the fifth semiconductor layer and the third electrode are electrically connected to the semiconductor substrate.
前記第１導電体層は、シリコンを主成分とし、表面に前記シリコンと金属との化合物層が形成されていることを特徴とする半導体装置。 The semiconductor device according to claim 12, wherein
The semiconductor device according to claim 1, wherein the first conductor layer is mainly composed of silicon, and a compound layer of silicon and metal is formed on a surface thereof.
前記第２導電体片は、前記第１電極下にのみ配置され、
前記バイポーラトランジスタの出力は１Ｗ以上であることを特徴とする半導体装置。 The semiconductor device according to claim 12, wherein
The second conductor piece is disposed only under the first electrode,
The semiconductor device according to claim 1, wherein an output of the bipolar transistor is 1 W or more.
ｐ型半導体基板と、a p-type semiconductor substrate;
前記ｐ型半導体基板の主面の第１領域上に選択的に形成されたコレクタ用ｎ型半導体層と、A collector n-type semiconductor layer selectively formed on the first region of the main surface of the p-type semiconductor substrate;
前記コレクタ用ｎ型半導体層の表面に形成されたベース用ｐ型半導体層と、A base p-type semiconductor layer formed on the surface of the collector n-type semiconductor layer;
前記ベース用ｐ型半導体層の表面に形成されたエミッタ用ｎ型半導体層と、An emitter n-type semiconductor layer formed on the surface of the base p-type semiconductor layer;
前記第１領域を囲むように前記ｐ型半導体基板の主面の第２領域上に形成されたアイソレーション用ｐ型半導体層と、An isolation p-type semiconductor layer formed on the second region of the main surface of the p-type semiconductor substrate so as to surround the first region;
前記アイソレーション用ｐ型半導体層の表面に形成されたアイソレーション用絶縁膜と、An isolation insulating film formed on the surface of the isolation p-type semiconductor layer;
前記エミッタ用ｎ型半導体層、前記ベース用ｐ型半導体層および前記コレクタ用ｎ型半導体層のそれぞれに電気的に接続されたエミッタ電極、ベース電極およびコレクタ電極と、An emitter electrode, a base electrode, and a collector electrode electrically connected to each of the emitter n-type semiconductor layer, the base p-type semiconductor layer, and the collector n-type semiconductor layer;
前記エミッタ電極、前記ベース電極および前記コレクタ電極のそれぞれに電気的に接続され、前記アイソレーション用絶縁膜上に配置されたワイヤ接続用のエミッタパッド電極、ベースパッド電極およびコレクタパッド電極とを有し、An emitter pad electrode, a base pad electrode, and a collector pad electrode for wire connection, which are electrically connected to the emitter electrode, the base electrode, and the collector electrode, respectively, and disposed on the isolation insulating film; ,
前記ｐ型半導体基板と前記エミッタパッド電極とには、接地電位が供給され、A ground potential is supplied to the p-type semiconductor substrate and the emitter pad electrode,
前記ｐ型半導体基板の厚さ方向において、前記ベースパッド電極と前記アイソレーション用絶縁膜との間には、前記ベースパッド電極を構成する導電膜とは別層の導電膜が配置され、In the thickness direction of the p-type semiconductor substrate, a conductive film different from the conductive film constituting the base pad electrode is disposed between the base pad electrode and the isolation insulating film,
前記別層の導電膜には、前記接地電位が供給されていることを特徴とする半導体装置。2. The semiconductor device according to claim 1, wherein the ground potential is supplied to the another layer of the conductive film.
前記エミッタパッド電極、前記ベースパッド電極および前記コレクタパッド電極は、最上層の導電膜により形成され、The emitter pad electrode, the base pad electrode, and the collector pad electrode are formed by an uppermost conductive film,
前記別層の導電膜は、前記最上層の導電膜より下層の導電膜により形成されていることを特徴とする半導体装置。The semiconductor device according to claim 1, wherein the another layer of the conductive film is formed of a lower conductive film than the uppermost conductive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004180722A JP2006005207A (en) | 2004-06-18 | 2004-06-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004180722A JP2006005207A (en) | 2004-06-18 | 2004-06-18 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2007142792A Division JP2007266621A (en) | 2007-05-30 | 2007-05-30 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2006005207A JP2006005207A (en) | 2006-01-05 |
| JP2006005207A5 true JP2006005207A5 (en) | 2007-07-12 |
Family
ID=35773313
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004180722A Pending JP2006005207A (en) | 2004-06-18 | 2004-06-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2006005207A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007243140A (en) * | 2006-02-09 | 2007-09-20 | Renesas Technology Corp | Semiconductor device, electronic equipment, and semiconductor device fabrication method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07130757A (en) * | 1993-10-28 | 1995-05-19 | Sony Corp | Manufacture of bipolar transistor |
| JP4626935B2 (en) * | 2002-10-01 | 2011-02-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
-
2004
- 2004-06-18 JP JP2004180722A patent/JP2006005207A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI557884B (en) | Monolithic microwave integrated circuit and method for forming the same | |
| JP5274264B2 (en) | Integrated circuit seal ring structure | |
| US8072004B2 (en) | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | |
| US9698102B2 (en) | Power and ground routing of integrated circuit devices with improved IR drop and chip performance | |
| JP2000012788A5 (en) | ||
| JP2004207723A (en) | Flip-chip fet element | |
| US20180342448A1 (en) | Semiconductor component and method of manufacture | |
| CN1716597B (en) | Semiconductor device | |
| US9653586B2 (en) | Amplifier device comprising enhanced thermal transfer and structural features | |
| JP2007243140A (en) | Semiconductor device, electronic equipment, and semiconductor device fabrication method | |
| JP2001230423A (en) | Soi mosfet device and manufacturing method thereof | |
| TWI784064B (en) | Gate-controlled bipolar junction transistor and operation method thereof | |
| JP2006005207A5 (en) | ||
| US6897547B2 (en) | Semiconductor device including bipolar junction transistor, and production method therefor | |
| JP2009540620A (en) | RF power transistor device with high performance shunt capacitor and method of use | |
| US10553709B2 (en) | Heterojunction bipolar transistor | |
| JPH10242169A (en) | Semiconductor device | |
| TWI289919B (en) | Wiring structure for a pad section in a semiconductor device | |
| JP7074392B2 (en) | Semiconductor device | |
| TW471154B (en) | Robust bonding pad structure for integrated circuit chips | |
| JP5035588B2 (en) | Semiconductor device having bipolar transistor | |
| JP2009182304A (en) | Semiconductor device | |
| JP7180842B2 (en) | semiconductor equipment | |
| KR100471520B1 (en) | Semiconductor device with special emitter connection | |
| US20140319703A1 (en) | Self-defining, low capacitance wire bond pad |