JP2006004234A - Instruction execution control system for microprocessor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize an instruction execution control system capable of automatically determining generation of data conflict in instruction execution by a microprocessor, and avoiding the data conflict without needing optimization by a compiler. <P>SOLUTION: This system comprises a determination circuit 10 predicting and determining generation of data conflict from decode information of a plurality of instructions and specifying the timing and address thereof; a control circuit 11 generating a conflict avoidance control signal in case that the generation of data conflict is predicted; a latch 12 temporarily holding data that is the object of conflict according to the conflict avoidance control signal; and a selector 14 selecting, in the event of data conflict, data held by the latch 12 according to the conflict avoidance signal, instead of data selection from a general storage area 4, whereby pipeline installation is avoided. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an instruction execution control system for improving the processing capability of a microprocessor.

  Conventionally, various techniques for improving the parallelism of processing have been developed as techniques for improving the processing capability of a microprocessor. Patent Document 1 discloses a technology for improving processing capability related to the VLIW (Very Long Instruction Word) method.

The VLIW method is a method in which a plurality of instructions are accommodated in one instruction word and executed at the same time. A program is previously executed by a compiler so that dependency relations (data conflicts, etc.) are not generated as much as possible between instructions to be executed. Optimize. When there is no instruction to be executed at the same time, a NOP (No Operation) instruction is executed. Therefore, an optimization technique by a compiler is required to improve the processing performance.
Japanese Patent Application No. 6-230969

  However, the conventional method has a problem that the pipeline installation becomes a big problem when the dependency such as data conflict occurs frequently, and the processing capability deteriorates.

  In the present invention, when a data conflict occurs in the instruction execution of the microprocessor, the control system automatically determines the situation and avoids the conflict due to the dependency between the instructions to be executed without requiring optimization by the compiler. An object of the present invention is to provide an instruction execution control method that can be used.

  According to a first aspect of the instruction execution control system of the present invention, in a microprocessor having an instruction memory, a decoder, an operation unit, and a storage area and executing instructions in a pipeline system, instructions are executed by a plurality of instruction decode information in the decoder. A determination circuit that predicts and determines the occurrence of data conflict at the time of execution and identifies the timing when the data conflict occurs and the data address of the storage area, and generates a conflict avoidance control signal when the determination circuit predicts the occurrence of data conflict A control circuit; a latch that temporarily holds data at the data address of the storage area specified by the determination circuit in response to the conflict avoidance control signal; and data specified by the determination circuit in response to the conflict avoidance control signal At the time of conflict occurrence And the selector to perform the data selection, is performed to avoid pipeline stall equipped with a.

  According to a second aspect of the instruction execution control system of the present invention, in the instruction execution control system according to the first aspect, the selector normally selects data in the storage area and generates a data conflict specified by the determination circuit. At the timing, the data held in the latch is selected and the selected data is sent to the arithmetic unit.

  According to the configurations of the first and second aspects, the determination circuit predicts and determines the occurrence of data conflict, and the control circuit generates the control signal for avoiding the data conflict, which is necessary when the data conflict occurs. Data in the storage area is temporarily held in the latch, and when the data conflict occurs, the data in the latch can be selected so that the wrong data is not used, so data conflict can be avoided and the processing capacity is improved. Can be made.

  According to a third aspect of the instruction execution control system of the present invention, in the instruction execution control system of the first aspect, the decoder and the determination circuit include a plurality of decoders necessary for predicting the occurrence of data conflict according to the number of pipeline stages. Is always processed.

  According to this configuration, it is possible to retain the instruction code of several instructions ahead necessary for predicting the occurrence of the data conflict and determine whether or not the data conflict occurs, so that the data conflict can be performed regardless of the number of pipeline stages. Occurrence can be predicted.

  According to the present invention, the occurrence of a data conflict is predicted in advance, and the data is temporarily held in the latch, so that correct data from a predetermined address can be used and data can be written to the address at the same time. Conflicts can be avoided and the processing performance of the microprocessor can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a microprocessor for implementing an instruction execution control system according to an embodiment of the present invention. In FIG. 1, the microprocessor includes an instruction memory 1, a decoder 2, an operation unit 3, a storage area (register, memory) 4, a determination circuit 10, a control circuit 11, a latch 12, and selectors 13 and 14, and a data bus 1 A data bus 2 and a data bus 3 are provided.

  The instruction read from the instruction memory 1 is decoded by the decoder 2, and the data is sent to the arithmetic unit 3 and the storage area 4 via the data bus 1. The selector 14 selects the data in the storage area 4 or the latch 12 and sends it to the arithmetic unit 3 through the data bus 2. The output of the calculation unit 3 is sent to the storage area 4 via the data bus 3.

  The determination circuit 10 determines the time when the conflict occurs and the address of the storage area from the information of the decoding result by the decoder 2. The control circuit 11 generates the control signal 1 and the control signal 2 based on the determination result of the determination circuit 10.

  The control signal 1 selects data at an address where a conflict occurs, transfers the data from the storage area 4 to the latch 12, and temporarily holds the data in the latch 12. The control signal 2 selects one of the data in the storage area 4 or the latch 12 so that the data does not collide. That is, the data in the latch 12 is transferred to the data bus 2 when a conflict has occurred, and the data in the storage area 4 is transferred to the data bus 2 when no conflict has occurred.

  FIG. 2 is a diagram illustrating a case where a conflict occurs during 5-stage pipeline control as an example of a problem with the conventional method. In the 5-stage pipeline shown in FIG. 2, each stage is IF (instruction fetch), DEC (instruction decoder), EX (instruction execution), MA (memory access), and WB (register write).

  As a relation between the instruction A and the instruction B, a conflict occurs when data is read from this register in the instruction B at the same time that data is written in the specific register in the instruction A. In the case of the conventional method, a stall of several cycles occurred, and the processing deteriorated.

  FIG. 3 is a flowchart showing an instruction execution control operation according to the present embodiment. In step 31, the data from the instruction memory 1 is decoded by the decoder 2. In step 32, the determination circuit 10 determines the possibility of occurrence of a conflict. If it is determined that bus control is necessary due to the occurrence of the conflict, the time and Identify the address.

  Based on the information, the control circuit 11 generates a control signal in step 33, and temporarily stores the data at the address where the conflict has occurred in the latch 12 in step 34. The data held in the latch 12 is transferred to the data bus via the selector 14 at the time when a conflict occurs in step 35.

  In this way, data can be written at the same time as reading to a location where a conflict has occurred. Therefore, even if a conflict occurs, an instruction can be executed without degrading the processing performance.

  The instruction execution control method in the microprocessor of the present invention is useful in that it can be avoided when a conflict occurs, and a general-purpose processor can avoid deterioration in processing performance due to the occurrence of conflict.

The block diagram which shows the structure of the microprocessor which implements the instruction execution control system which concerns on one embodiment of this invention. The figure explaining the case where a conflict generate | occur | produces at the time of 5-stage pipeline control. The flowchart which shows the instruction execution control operation | movement by one embodiment of this invention.

Explanation of symbols

1 instruction memory 2 decoder 3 operation unit 4 storage area (register, memory)
10 Judgment Circuit 11 Control Circuit 12 Latch 13, 14 Selector 31-35 Step IF Instruction Fetch DEC Instruction Decoder EX Instruction Execution MA Memory Access WB Register Write

Claims (3)

An instruction execution control method in a microprocessor that has an instruction memory, a decoder, a calculation unit, and a storage area and executes instructions in a pipeline manner,
A determination circuit for predicting and determining occurrence of data conflict at the time of executing an instruction based on a plurality of instruction decode information in the decoder, and specifying a timing at the time of data conflict occurrence and a data address of the storage area;
A control circuit that generates a conflict avoidance control signal when a data conflict occurrence is predicted by the determination circuit;
A latch that temporarily holds data at the data address of the storage area specified by the determination circuit in response to the conflict avoidance control signal;
A selector that performs data selection at the time of occurrence of data conflict specified by the determination circuit according to the conflict avoidance control signal;
A microprocessor instruction execution control system that avoids pipeline installation.   The selector normally selects data in the storage area, selects data held in the latch at the time of occurrence of data conflict specified by the determination circuit, and sends the selected data to the arithmetic unit. 2. The microprocessor instruction execution control system according to claim 1.   2. The instruction execution control system for a microprocessor according to claim 1, wherein the decoder and the determination circuit always process a plurality of instructions necessary for predicting and determining data conflict occurrence according to the number of pipeline stages.

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