JP2006004030A - Information processing device, method, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correct an error with higher precision. <P>SOLUTION: Parity outputted from a C1 decoding part 22 is delayed by a delay part 41, and then, supplied to a combination part 42. The combination part 42 sets error points in number found by subtracting a set number from a maximum number to the parity when the error pointer number set to 28 symbol data outputted from a C2 decoding part 24 is lower than the settable maximum error pointer number. A combination of the parity setting the error pointer is changed, and C1 decoding is carried out for each combination by a C1 decoding part 43. A determination part 44 extracts a combination including zero as an error constituent from a decoding result for each inputted combination and outputs C1 decoding based on the combination to the following processing. This invention can be applied to a device performing CIRC decoding. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an information processing apparatus and method, and a program, and more particularly to an information processing apparatus and method suitable for error correction at the time of decoding when an encoding method such as CIRC (Circular Interleave Reed-solomon Code) is applied. , As well as programs.

  For example, in an information processing apparatus or the like that processes predetermined information such as a CD (Compact Disc) player, CIRC is used as an error correction method for correcting an error caused by a scratch that exceeds an allowable range during the manufacturing process or use of a recording medium to be handled. Is used. For example, the CIRC related to the CD method uses a combination of a Reed-solomon code that is an error correction code having a high random error correction capability and a cyclic interleaving method that converts a burst error into a random error by interleaving. It has been.

  FIG. 1 is a diagram illustrating an example of a configuration of an encoder 10 that performs error correction using a CD-type CIRC. In the CD-type CIRC, 6 samples each of the L and R channels, that is, 12 samples of the audio signal displayed by 16 bits are formed as one unit. Each 16-bit data is divided into upper 8 bits and lower 8 bits, and each 8-bit data is handled as one symbol.

  As shown in FIG. 1, 12 samples are formed by 24 symbols. The data of the sample time that is an even number from the beginning of such 24 symbol data is delayed by 2 words by the interleave unit 11, and then the 24 symbol data is crossed so that adjacent data are separated from each other at a constant interval. Is done. A first error correction code C2 is configured by the C2 encoding unit 12 from the 24 symbol data arranged to intersect in this way.

  This C2 is a Reed-Solomon code with n = 28, k = 24 and redundancy of 4, and the minimum distance is 5. The parity of C2 is denoted as Q. The first check word string, that is, Q parity which is 4 symbol data is arranged at the center of 24 symbol data. Next, a total of 28 symbols of P parity 4 symbols and 24 symbol data are interleaved by the delay unit 13 after being delayed by a different amount of difference for each symbol.

  Difference equal delay is a constant delay amount D of 4 words in order of the delay amount of 1D, 2D, 3D, 4D... 26D and 27D from the second symbol data excluding the first symbol data in the basic unit. Delay. The second error correction code C1 is configured by the C1 encoding unit 14 from the 28 symbol data delayed by the differential delay. This C1 is a Reed-Solomon code where n = 32, k = 28 and the redundancy is 4, and the minimum distance is 5.

  Let P be the parity of C1. The second check word string, that is, the P parity which is 4 symbol data is arranged next to the final symbol data of 28 symbol data. Next, the output unit 15 delays the even-numbered symbol data one word at a time and generates a total of 32 symbol data, thereby completing the encoding.

  The data encoded in this way is decoded by a decoder as shown in FIG. FIG. 2 is a diagram showing an example of the configuration of the decoder 20 that performs error correction by CD-type CIRC.

  The 32 symbol data encoded by the encoder 10 is basically decoded by performing a process reverse to the process performed by the encoder. In the decoder 20 shown in FIG. 2, 32-symbol data indicated as W, P, and Q, that is, a data string is a signal picked up from the optical disc and demodulated. The 24-symbol data indicated by W, ie, the data word string, is audio data, and P and Q are parity data for error detection and correction, ie, first and second check word strings.

  The 32 symbol data is supplied to the decoder 20. The decoder 20 includes an input unit 21 (consisting of a descrambling unit 21a and an inverter unit 21b), a C1 decoding unit 22 as a first decoder, a deinterleaving unit 23 as a first delay unit, and a second decoder As a C2 decoder 24 and an inverse cross delay unit 25 as an output unit.

  The descrambling unit 21a is composed of 16 one-word delay lines, and delays even-numbered symbol data by one word at a time in order to unscramble the scrambled 32 symbol data. That is, since the size of the pit formed on the optical disc in the CD system is within 8 bits, if the signal processing unit is 8 bits = 1 symbol data, the error due to scratches on the optical disc is almost 1 symbol unit. Become.

  If there is a scratch between symbols, an error of 2 symbols results. Therefore, in order to disperse such a continuous error, a delay in symbol units is performed. This is a scramble process, and a descramble process is performed to release the scramble process during reproduction.

  The inverter unit 21b inverts 0 and 1 of 4 symbol data of Q parity and 4 symbol data of P parity. This is to restore the inverted P / Q 8-symbol data of 0 and 1 as part of countermeasures against fixed patterns and burst errors.

  The C1 decoding unit 22 detects the burst error of the remaining 28 symbol data using the 4 symbol data of P parity out of the 32 symbol data and corrects the random error. In this case, error correction is performed by generating four syndromes using a parity check matrix, that is, a Reed-Solomon code. A data block in which two or more symbol errors have occurred is determined to be uncorrectable, and 28 symbol data is transmitted to the next stage without being corrected. Here, a sign (minimum decrease of 1 bit) is added to all the words in the data string so as to indicate whether or not there is an error.

  The deinterleaving unit 23 delays the 28 symbol data transmitted from the C1 decoding unit 22 by a differential delay and cancels the interleaving. That is, most errors that occur during the reproduction of an optical disk are thought to be caused by scratches, dust, etc., but once a defect occurs, many adjacent symbols are damaged all at once. If many symbols are damaged in the same data block, error detection and correction becomes impossible.

  During recording (encoding), symbols in the same data block are dispersed and recorded in other data blocks, and during reproduction, the dispersed symbols are restored to their original data block positions. This restoration process is called deinterleaving.

  The deinterleaving unit 23 is a delay having other delay times of 27D, 26D, 25D,... 2D, 1D (D is a basic unit of a constant delay amount of 4 words) for delaying the 28 symbol data by equal delay. The first to twenty-seventh transmission channels are constituted by lines.

  The C2 decoding unit 24 cancels the interleaving, that is, all 28 data words are delayed by the same delay time of 27D, and the 4 symbol data of Q parity out of the 28 symbol data restored to the original data block position. Are used to generate 4 syndromes from the Reed-Solomon code and 28 words of input, and correct up to a maximum of 4 symbol errors. Here, the mark for the error-corrected word is turned off, but the mark for the error word that cannot be corrected is not turned off.

  The inverse cross delay unit 25 crosses each other in order to restore the original position within the 24 symbol data block supplied from the C2 decoding unit 24, and the adjacent symbol data on the encoding time axis is subjected to 2-word delay processing. In order to restore the dispersed data to the original position, symbol data that is not subjected to 2-word delay processing is subjected to 2-word delay processing. This is because such delay processing does not continuously output uncorrectable error data during reproduction.

  By performing decoding in this way, data in which the error is corrected is generated, and sound based on the data is provided to the user.

  However, there may be error data that cannot be corrected by the C1 and C2 error correction capability, such as when there is a lot of error data on the optical disk. In such a case, data different from the original data is generated by the error data that is not corrected, and the audio signal reproduced from the generated data includes noise.

In order to prevent the situation where such errors cannot be corrected, it has been proposed that C1 and C2 error correction (error correction by CIRC) be performed not only once but twice (or a plurality of times). ing. (For example, see Patent Document 1)
JP-A-5-29964

  However, when error correction by CD-type CIRC is repeatedly performed as described in Patent Document 1, the second C1 correction is performed in the state where the error pointer of the parity portion of C1 does not exist in the second C1 correction. It will be.

  If the error pointer is applied to all symbols when correction is impossible in the first C1, the symbols other than the C1 parity are corrected in combination with different blocks by C2 correction. For this reason, the error pointer of a part that is not an error or a part that has been error-corrected may be reset. However, since the C1 parity is not included in the C2 correction, the C1 parity is not reset, and there is a problem that the same thing as the first time in which an error may be hidden is input as it is for the second time. .

  Therefore, since there are 4 C1 parities, if there are some 4 symbols that are indeterminate and there are some data portions other than the parity that cannot be C2 corrected, 4 or more symbols are indeterminate, so further correction is possible. There was a problem that it was not possible.

  When correction is performed without using an error pointer, only two error corrections can be performed, and the error correction by repetition has a problem that the range that can be corrected is narrowed.

  The present invention has been made in view of such a situation, and by using the remaining error pointers of error pointers existing in a part other than the parity, which part of the parity where no error pointer exists is a correct value. It is an object of the present invention to make it possible to correct an error correctly by searching for and confirming the error and to correct the error with higher accuracy.

  The information processing apparatus according to the present invention has a determination unit that determines a first number of error pointers set in a data string excluding parity, and a second number of error pointers that can be set in the parity and the data string. When the first number of error pointers determined by the above is small, a setting unit that sets an error pointer in the parity within a range of a third number obtained by subtracting the first number from the second number, and an error by the setting unit And decoding means for performing decoding using parity set with a pointer.

  When the number of parity is larger than the third number, the setting unit changes a combination of parity for setting the error pointer, and the decoding unit decodes the data string for each combination, and among the decoding results, A set including 0 in the error component can be set as a decoding result.

  The decoding means can decode the data string based on CIRC (Circular Interleave Reed-solomon Code).

  The information processing method of the present invention includes a determination step for determining a first number of error pointers set in a data string excluding parity, and a determination step based on a second number of error pointers that can be set in parity and the data string. A setting step for setting an error pointer in the parity within a range of a third number obtained by subtracting the first number from the second number when the first number of error pointers determined by the processing of And a decoding step of performing decoding using a parity in which an error pointer is set.

  The program according to the present invention includes a determination step for determining a first number of error pointers set in a data string excluding parity, and a determination step process based on a second number of error pointers that can be set in parity and the data string. When the first number of error pointers determined by the step is small, a setting step for setting an error pointer in the parity within a range of a third number obtained by subtracting the first number from the second number, and processing of the setting step And a decoding step of performing decoding using a parity in which an error pointer is set.

  In the information processing apparatus and method, and the program of the present invention, when a smaller number of error pointers than the number of error pointers that can be set are set in the encoded data string, within the remaining settable range, The error pointer is set in combination for the non-existing parity, and decoding is performed for each set.

  According to the present invention, it is possible to perform error correction with high accuracy.

  According to the present invention, when performing error correction a plurality of times, it is possible to perform error correction by checking whether there is an error in the parity itself. This makes it possible to correct the error with higher accuracy.

  BEST MODE FOR CARRYING OUT THE INVENTION The best mode of the present invention will be described below. The correspondence relationship between the disclosed invention and the embodiments is exemplified as follows. Although there is an embodiment which is described in the specification but is not described here as corresponding to the invention, it means that the embodiment corresponds to the invention. It doesn't mean not. Conversely, even if an embodiment is described herein as corresponding to an invention, that means that the embodiment does not correspond to an invention other than the invention. Absent.

  Further, this description does not mean all the inventions described in the specification. In other words, this description is an invention described in the specification and is not claimed in this application, that is, an invention that will be filed in division in the future, appearing by amendment, and added. The existence of is not denied.

  The information processing apparatus of the present invention is, for example, the decoder 40 shown in FIG. 3 or FIG. The information processing apparatus according to the present invention is a determination unit that determines the first number of error pointers set in the data string excluding the parity (for example, the combination unit in FIG. 3 that executes the processing in steps S31 to S33 in FIG. 6). 42), and when the first number of error pointers determined by the determining means is less than the second number of error pointers that can be set in the parity and data string, the first number is subtracted from the second number. 3. Setting means for setting an error pointer in the parity within the range of 3 (for example, the combination unit 41 and the C1 decoding unit 43 in FIG. 3 that execute the processing of steps S35 to S37 in FIG. 6), and an error pointer by the setting means Decoding means that performs decoding using the set parity (for example, the combination unit 41 and the C1 decoding unit 4 in FIG. 3 that execute the processing of steps S35 to S37 in FIG. 6) ) And a.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 3 is a diagram showing a configuration of an embodiment of a decoder to which the present invention is applied. FIG. 4 is a functional block diagram of the decoder 40 shown in FIG. 3 and 4 show the configuration of the same decoder. 3 and 4, the same portions are denoted by the same reference numerals to indicate the correspondence.

  The decoder 40 shown in FIG. 3 (FIG. 4) has a function as an information processing apparatus that processes data (information) encoded by a CD (Compact Disc) type CIRC (Circular Interleave Reed-solomon Code). For example, it is provided in a CD player. The data supplied to the decoder 40 is data encoded by an encoder 10 having the configuration shown in FIG. 1 and recorded on a predetermined recording medium (for example, CD).

  The decoder 40 is configured to perform error correction of CIRC C1 and C2 sequences twice. That is, first, the first error correction of the C1 and C2 series is performed. Thereafter, the 28 symbol data of the error correction result of the C2 sequence is interleaved again, and after the interleaved 28 symbol data is delayed, the error correction of the second C1 sequence is performed with the 4 symbol data of P parity. Is done.

  Then, after 28 symbol data of the error correction result of the second C1 sequence is deinterleaved, error correction of the second C2 sequence is performed with 4 symbol data of Q parity. Therefore, it is possible to correct an error of 2 symbols in the 1st C1 sequence, 4 symbols in the 2nd C1 sequence of 4 symbols in the 1st C2 sequence, and 4 symbols in the 2nd C2 sequence.

  With such a configuration, the error correction capability can be improved.

  The configuration of the decoder 40 that performs such processing will be described with reference to FIGS. The decoder 40 shown in FIGS. 3 and 4 includes an input unit 21 (consisting of a descramble unit 21a and an inverter unit 21b), a C1 decoding unit 22, a deinterleaving unit 23, and a C2 decoding unit. 24, an interleaving unit 41, a combination unit 42, a C1 decoding unit 43, a determination unit 44, a deinterleaving unit 45, a C2 decoding unit 46, and a cross delay processing unit 25.

  3 that are the same as those in FIG. 2 are given the same reference numerals, and descriptions thereof will be omitted as appropriate. Although not shown in FIG. 3, data basically similar to the data shown on the left side in FIG. 2 (data input to the decoder 20) is input to the decoder 40 shown in FIG. .

  The descrambling unit 21a includes 16 one-word delay lines. The descrambling unit 21a delays even-numbered symbol data by one word at a time in order to unscramble 32 symbol data scrambled at the time of recording.

  In the CD method, the size of a pit formed on an optical disk is within 8 bits, and when the signal processing unit is 8 bits = 1 symbol data, errors due to scratches on the optical disk are almost in 1 symbol units. .

  If there is a scratch between symbols, an error of 2 symbols will result. In order to disperse such continuous errors, a delay in symbol units is performed at the time of data recording (during encoding). The processing at the time of recording (processing performed in the output unit 15 in FIG. 1) is scrambled, and descrambling is performed to cancel the scrambled processing at the time of reproduction. The descrambling unit 21a performs the descrambling process.

  The inverter unit 21b inverts 0 and 1 of 4 symbol data of Q parity and 4 symbol data of P parity. This is performed in order to restore 0 and 1 of 8 symbol data of P and Q as a countermeasure against a fixed pattern and a burst error at the time of encoding.

  The C1 decoding unit 22 detects a burst error of the remaining 28 symbol data using 4 symbol data of P parity among the 32 symbol data, and also corrects a random error. This error correction is performed by generating four syndromes using a parity check matrix, that is, a Reed-Solomon code.

  If two or more symbol errors occur at this stage, the data block is determined to be uncorrectable, and 28 symbol data is transmitted to the next stage without being corrected. Here, a sign (minimum decrease of 1 bit) is added to all the words in the data string so as to indicate whether or not there is an error.

  The deinterleaving unit 23 delays the 28 symbol data transmitted from the C1 decoding unit 22 by a differential delay and cancels the interleaving. Errors that occur during playback of a recording medium such as an optical disk are often caused by scratches, dust, and the like, and once a defect occurs, many adjacent symbols tend to be damaged all at once. If many symbols are damaged in the same data block, error detection and correction becomes impossible.

  In order to prevent this, symbols in the same data block are recorded in a state of being distributed to other data blocks at the time of recording (coding) (processing by the delay unit 13 in FIG. 1), and at the time of reproduction (decoding) Time), the dispersed symbols are restored to their original data block positions. This restoration process is called deinterleaving, and the deinterleaving unit 23 performs this process.

  The deinterleaving unit 23 is a delay having other delay times of 27D, 26D, 25D,... 2D, 1D (D is a basic unit of a constant delay amount of 4 words) for delaying the 28 symbol data by equal delay. The first to twenty-seventh transmission channels are constituted by lines.

  The C2 decoding unit 24 cancels the interleaving, that is, all 28 data words are delayed by the same delay time of 27D, and the 4 symbol data of Q parity out of the 28 symbol data restored to the original data block position. Are used to generate 4 syndromes from the Reed-Solomon code and 28 words of input, and correct up to a maximum of 4 symbol errors. Here, the mark for the error-corrected word is turned off, but the mark for the error word that cannot be corrected is not turned off.

  In the decoder 40 shown in FIG. 3, error correction by CIRC is performed again. Therefore, after the first-stage error correction is performed by the C1 decoding unit 22 and the C2 decoding unit 24, the 24 symbol data output from the C2 decoding unit 24 and the first and second check word strings are converted into the delay unit 23. The processing for restoring the same array state as the array state of the data string input to is executed.

  The delay unit 41 has a delay amount of 1D, 2D, 3D... 26D and 27D from the second transmission channel excluding the first transmission channel in order to re-interleave the input 28 symbol data. Consists of lines. Further, the delay unit 41 is configured to have a delay line having a 27D delay amount as the 29th to 32nd channels in order to delay the four check words supplied from the C1 decoding unit 22.

  The 32 symbol data reinterleaved by the delay unit 41 as the second delay unit is supplied to the C1 decoding unit 43. Although details will be described later, four check words supplied from the C1 decoding unit 22 among the 32 symbol data supplied to the C1 decoding unit 43 are input via the combination unit 42. Here, four check words are input via the combination unit 42, but the four check words are also directly supplied to the C1 decoding unit 43 and also supplied to the combination unit 42. It is good also as a structure.

  The combination unit 42 is provided to further improve the accuracy of error correction, and details thereof will be described later. In addition, by providing the combination unit 42, the C1 decoding unit 43 includes a plurality of C1 decoding units that execute the same decoding process.

  The C1 decoding unit 43 performs the same processing that is performed in the C1 decoding unit 22 described above. That is, the C1 decoding unit 43 performs error correction, and performs an error presence / absence labeling for all words. The output data string from the C1 decoding unit 43 is supplied to the delay unit 45 via the determination unit 44. The determination unit 44 extracts one result (data string) from a plurality of decoding results supplied from the C1 decoding unit 43 based on a determination method described later, and supplies the result to the delay unit 45.

  The delay unit 45 has the same configuration as the delay unit 23 and deinterleaves the input 28 symbol data again. The data string deinterleaved by the delay unit 45 is supplied to the C2 decoding unit 46. The C2 decoding unit 46 performs error correction on the data string input in the same process as the C2 decoding unit 24 described above, and outputs the data string. The data string output from the C2 decoding unit 46 is supplied to the reverse cross delay unit 25.

  The inverse cross delay unit 25 crosses each other in order to be restored to the original position in the 24 symbol data supplied from the C2 decoding unit 46, and the symbol data adjacent on the time axis at the time of encoding is subjected to 2-word delay processing. In order to restore the dispersed data to the original position, the symbol data not subjected to the 2-word delay process is subjected to the 2-word delay process. Such a delay process is performed in order to prevent error data that cannot be corrected from being output continuously during reproduction.

  By performing decoding in this way, data in which the error is corrected is generated, and sound based on the data is provided to the user.

  Next, the operation of the decoder 40 shown in FIG. 3 or 4 will be described with reference to the flowcharts of FIGS. In step S11, the decoder 40 inputs data. The input data is data read from a predetermined recording medium (for example, CD) by controlling a pickup (not shown).

  The decoder 40 inputs data at the input unit 21. The input unit 21 includes a descrambling unit 21a and an inverter unit 21b. The descrambling unit 21a and the inverter unit 21b delay even-numbered symbols by one frame. By executing this process, the amount of delay of only one odd frame during recording is canceled, and 0 and 1 of 4 symbol data of Q parity and 4 symbol data of P parity are inverted.

  The data string that has been processed by the input unit 21 is supplied to the C1 decoding unit 22. In step S12, the C1 decoding unit 22 detects a burst error of the remaining 28 symbol data using the 4 symbol data of P parity among the supplied 32 symbol data and corrects the random error.

  The data string decoded by the C1 decoding unit 22 is supplied to the deinterleaving unit 23. In step S13, the deinterleaving unit 23 delays the supplied 28-symbol data by a differential delay and cancels the interleaving. The 28 symbol data from which the interleaving has been canceled is supplied to the C2 decoding unit 24.

  In step S14, the C2 decoding unit 24 generates four syndromes from the Reed-Solomon code and the input 28 words using 4 symbol data of Q parity among the 28 symbol data restored to the original data block position. Correct up to 4 symbol errors. Here, the mark for the error-corrected word is turned off, but the mark for the error word that cannot be corrected is not turned off.

  The first stage decoding and error correction are performed by the processing so far. Subsequently, in order to perform the second stage decoding and error correction, the following processing is executed.

  The 28 symbol data output from the C2 decoding unit 24 is supplied to the delay unit 41. In step S15, the delay unit 41 interleaves the input 28 symbol data again. This process is executed in order to perform error correction by CIRC again. The delay unit 41 delays and outputs the four check word strings supplied from the C1 decoding unit 22. The check word string supplied from the C1 decoding unit 22 is the same as the check word supplied to the C1 decoding unit 22 that performs the first-stage C1 decoding.

  The 32 data strings interleaved again by the delay unit 41 are supplied to the C1 decoding unit 43. Of the 32 data strings supplied to the C1 decoding unit 43, the four check words supplied from the C1 decoding unit 22 are also supplied to the combination unit 42.

  The combination unit 42, the C1 decoding unit 43, and the determination unit 44 execute determination processing in step S16. This process will be described later with reference to the flowcharts of FIGS. By executing the processing in step S16, the accuracy of error correction is further improved.

  When the processing of step S16 is executed and 28 symbol data is output from the determination unit 44, the data string is supplied to the delay unit 45. In step S17, the delay unit 45 deinterleaves the input 28 symbol data again. This process is performed in the same manner as the process performed by the delay unit 23 in step S13. The data string deinterleaved by the delay unit 45 is supplied to the C2 decoding unit 46. In step S18, the C2 decoding unit 46 performs error correction on the input data string in the same process performed by the C2 decoding unit 24 in step S14, and outputs it to the inverse cross delay unit 25. The output data string from the C2 decoding unit 46 is supplied to the reverse cross delay unit 25.

  In step S19, the inverse cross delay unit 25 crosses each other in order to restore the original position within the 24 symbol data supplied from the C2 decoding unit 46, and sets the symbol data adjacent on the time axis of encoding to 2 Symbol data that is not subjected to 2-word delay processing is subjected to 2-word delay processing in order to restore the original data after being dispersed by word delay processing.

  The data string decoded in this way is supplied to a speaker or the like (not shown).

  Next, the determination process executed in step S16 will be described. This determination process is executed in order to perform error correction with higher accuracy in consideration of the following. In other words, the four check words (P parity) supplied to the C1 decoding unit 43 are provided to correct errors included in the 28 symbol data sequence. May contain errors. When an error is included in the parity itself, there is a possibility that the error included in the 28-bit data string cannot be corrected correctly.

  If the error included in the 28 symbol data is corrected in a state where the parity itself includes an error, not only the error cannot be corrected but also the error may be further increased. As a result, erroneously corrected data may be handled as correct data. In order to prevent this, the determination process in step S16 is executed.

  Of the 32 symbol data supplied to the C1 decoding unit 43, if an error is included in 28 symbol data excluding 4 symbol data that is a parity, an error pointer indicating the location of the error is attached. A data string is supplied to the C1 decoding unit 43. This error pointer is not attached to the parity supplied to the C1 decoding unit 43.

  In the CD-type CIRC, error pointers can be corrected at a maximum of four locations. Therefore, the error of the parity itself is checked by using the remaining error pointer of the error pointer existing in the part other than the parity (that is, the part of the 28-symbol data string) as the error pointer of the parity. In other words, when m error pointers are attached to the 28-symbol data string, (4-m) error pointers are used as error pointers for checking parity errors. The process including this check is a determination process here.

  With reference to the flowchart shown in FIG. 6, the determination process performed in step S16 will be described. First, the combination unit 42 (FIGS. 3 and 4) determines whether or not there is one error pointer attached to the 28-symbol data string in step S31. If it is determined in step S31 that there is not one error pointer, the process proceeds to step S32 to determine whether there are two error pointers.

  If it is determined in step S32 that there are not two error pointers, the process proceeds to step S33 to determine whether there are three error pointers. If it is determined in step S33 that there are not three error pointers, the process proceeds to step S34. When it is determined that there are not three error pointers, there are four or more error pointers attached to the 28-symbol data string.

  When four or more error pointers are attached, there is no extra error pointer that can be attached to the parity, so that processing such as correcting the error of the parity itself is not executed. In addition, when four or more error pointers are attached, there is a possibility that the error correction itself is erroneously corrected. Therefore, control is performed so that error correction is not performed for portions other than parity.

  Considering this, if it is determined in step S33 that there are not three error pointers, the process proceeds to step S34, and control is performed so that the parity correction process is not executed.

  On the other hand, if it is determined in step S31 that there is only one error pointer attached to the 28 symbol data string, the process proceeds to step S35. The determination process 1 executed in step S35 will be described with reference to the flowchart of FIG.

  In step S51, the combination unit 42 sets an error pointer to the symbol P1, parity A, parity B, and parity C, and instructs the C1 decoding unit 43 to perform C1 decoding under the set conditions. Based on such an instruction, the C1 decoding unit 43 performs four-point correction.

  Here, the symbol P1 indicates a symbol having an error pointer in the 28 symbol data string. Parity A, parity B, and parity C indicate three parities of the parity of the 4-symbol data, respectively. In the following description, symbol P2, symbol P3, parity D, and the like are also used, and the meaning thereof is assumed to indicate the same meaning as symbol P1, parity A, parity B, and parity C described above. Further, it is assumed that the parity A, the parity B, the parity C, and the parity D are arranged in the order of “ABCD”.

  In step S51, error pointers are set for the symbol P1, the parity A, the parity B, and the parity C, and the C1 decoding unit 43 performs C1 decoding based on the setting.

  In step S52, error pointers are set in the symbols P1, parity A, parity B, and parity D, and C1 decoding is performed in the C1 decoding unit 43 based on the settings.

  In step S53, error pointers are set for the symbol P1, the parity A, the parity C, and the parity D, and the C1 decoding unit 43 performs C1 decoding based on the settings.

  In step S54, error pointers are set for the symbols P1, parity B, parity C, and parity D, and the C1 decoding unit 43 performs C1 decoding based on the settings.

  When the processes of steps S51 to S54 are performed in parallel, in other words, when four C1 decodings are performed simultaneously, the C1 decoding unit 43 requires four parts for performing C1 decoding. Therefore, as shown in FIG. 3, in the present embodiment, a plurality of C1 decoding units 43 are provided. When a plurality of combinations are provided, the number depends on the number of combinations set in the combination unit 42. In this case, the maximum value of the number is six. The reason for 6 will be described later with reference to the flowchart of FIG. Therefore, in this case, the C1 decoding unit 43 may be configured by six C1 decoding units.

  By configuring so that processing can be performed in parallel, the processing (decoding processing) itself can be accelerated.

  In step S55, it is determined whether or not there is a combination including 0 as an error component by using the result obtained by executing each process of steps S51 to S54. The process in step S55 is performed by the determination unit 44. In this case, four calculation results are supplied from the C1 decoding unit 43 to the determination unit 44.

  The error component becomes 0 when the data is not an error. Therefore, whether or not there is a combination including 0 as such an error component is determined as the process of step S55. With reference to FIG. 10, a description will be given of how to determine whether an error exists in the parity itself.

  The notation “A, B, C, P1” on the left side of the figure means that an error pointer is set for each of parity A, parity B, and parity C, and an error pointer is attached to symbol P1. It means that it was done. The upper notation in the figure indicates which parity of the parity for which the error pointer is set has an error. For example, the notation “one-point error (P1)” has an error in the parity itself. The notation “2 location error (P1, A)” indicates that there is an error at 1 location in the parity, and that the error is parity A.

  In the example shown in FIG. 10, only the error component output when the parity A is an error is illustrated, assuming that there is an error in only two places. Further, in the example shown in FIG. 10, only the error component output when the parity A and the parity B are errors is shown, assuming that there are errors at only three places. Furthermore, in the example shown in FIG. 10, when there are errors at four locations (that is, when all the parity for which error pointers are set are errors), parity A, parity C, and parity C are errors. Only the error components that are sometimes output are shown.

  10 to 12, the error pointer set in the 28-symbol data is shown, but in the following description, the error pointer set for the parity is mainly described. .

  When error pointers are set in parity A, parity B, and parity C, if the parity set with these error pointers is not an error, “A = 0, B = 0, C = 0 as error components” , P1 = Ep1 ″ is output.

  In such a case, as a result, only one error (P1 = Ep1 in the above example) exists in the 32 symbol data including parity. Therefore, it is possible to correct the error (it is possible to correct the error of the symbol P1 using the error component Ep1).

  When error pointers are set for parity A, parity B, and parity C, and only the parity A of the parity for which these error pointers are set is an error, “A = Ea, B = 0, C = 0, P1 = Ep1 ". In this case, Ea is a value other than 0, and a value other than 0 indicates that the data is an error. The value is used when correcting the data.

  In such a case, as a result, two errors (A = Ea and P1 = Ep1 in the above example) exist in the 32 symbol data including the parity. When one error exists in the parity set with the error pointer, it is possible to correct two errors existing in the 32 symbol data.

  However, if an error exists in a parity other than the parity for which the error pointer is set, that is, if an error exists in a parity other than the three parities for which the error pointer is set, the result is Therefore, it is handled that there are five errors in the 32 symbol data. In such a case, it is not possible to accurately identify or correct a symbol having an error.

  For example, referring to FIG. 10, when an error pointer is set and processed for parity B, parity C, and parity D, even if there is no error in the parity for which these error pointers are set, the error pointer Is not set, the parity A, which is the error, is affected and “B = Eb ′, C = Ec ′, D = Ed ′, P1 = Ep1 ′” are error components. Will be output.

  In FIG. 10, the notation with a dash (') indicates that an uncertain error component (a value whose parity cannot be corrected using the error component) is output.

  As another example, when error pointers are set in parity A, parity B, and parity C, if parity A and parity B out of the parity set with these error pointers are errors, an error will occur. As components, “A = Ea, B = Eb, C = 0, P1 = Ep1” is output. In this case, Ea and Eb are values other than 0, and a value other than 0 indicates that there is an error in the data. The value is used when correcting the data.

  In such a case, as a result, there are three errors in the 32 symbol data including parity. When there are two errors in the parity in which the error pointer is set as in the above example, it is possible to identify three errors existing in the 32 symbol data.

  However, if there is an error in parity other than the parity for which the error pointer is set, that is, if there is an error in one parity other than the three parity for which the error pointer is set, As a result, it is handled that there are five errors in the 32 symbol data. In such a case, it is not possible to accurately identify or correct a symbol having an error.

  For example, referring to FIG. 10, when an error pointer is set for parity B, parity C, and parity D, an error exists only in parity B of the parity for which these error pointers are set. Even when there is an error in parity A for which no error pointer is set (that is, when an error actually occurs in parity A and parity B), the effect of parity A, which is the error As a result, “B = Eb ′, C = Ec ′, D = Ed ′, and P1 = Ep1 ′” are output as error components. In such a case, it is not possible to accurately identify or correct a symbol having an error.

  As yet another example, when error pointers are set for parity A, parity B, and parity C and all of the parity for which these error pointers are set are errors, “A = Ea, B = Eb, C = Ec, and P1 = Ep1 ″ are output. In this case, Ea, Eb, and Ec are values other than 0, and a value other than 0 indicates that there is an error in the data. The value is used when correcting the data.

  In such a case, as a result, there are four errors in the 32 symbol data including parity. When there are three errors in the parity in which the error pointer is set as in the above example, it is possible to specify the four errors existing in the 32 symbol data including the parity.

  However, if there is an error in parity other than the parity for which the error pointer is set, that is, if there is an error in one parity other than the three parity for which the error pointer is set, As a result, it is handled that there are five errors in the 32 symbol data. In such a case, it is not possible to accurately identify or correct a symbol having an error.

  For example, referring to FIG. 10, when an error pointer is set in parity B, parity C, and parity D, it seems that an error exists in all the parities in which those error pointers are set. When there is an error even in parity A for which no error pointer is set (that is, when there is actually an error in all of parity A, B, C, and D), the effect of parity A that is the error As a result, “B = Eb ′, C = Ec ′, D = Ed ′, and P1 = Ep1 ′” are output as error components. In such a case, it is not possible to accurately identify or correct a symbol having an error.

  In consideration of this, the number of errors included in the 32-symbol data including parity is 4 or less if at least one parity whose error component is 0 is included in the parity set with the error pointer. It turns out that it becomes. Therefore, if even one parity whose error component is 0 is included in the parity set with the error pointer, the error can be detected even if the parity itself includes an error. Using this fact, in step S55 (FIG. 7), it is determined whether or not there is a combination including 0 as an error component.

  Returning to the description of the flowchart shown in FIG. 7, it is determined in step S55 whether or not there is a combination including 0 in the error component. Referring to FIG. 10 again, the combinations including 0 in the error component are illustrated with hatching. In other words, the determination unit 44 (FIGS. 3 and 4) has a combination in which an oblique line shown in FIG. 10 is drawn in the input data string (a combination not shown in FIG. 10 is also described above). Is present), in step S55, it is determined as YES, and the process proceeds to step S56.

  In step S56, when there are a plurality of combinations including 0 in the error component, one combination is specified, and it is confirmed whether or not the correction by the specified combination is correct. For example, when there is no error in all the parity, the error component of the parity for which the error pointer is set is 0, so that it is described in the column “1 error (P1)” when referring to FIG. 10 again. The four combinations are input to the determination unit 44.

  Thus, when a plurality of combinations exist as candidates, the determination unit 44 selects one combination. Then, it is confirmed whether correct correction is performed with the selected combination. Basically, when there is a combination containing 0 in the error component, there is a high possibility that the correction in the combination is correctly performed. Therefore, the process of step S56 may be a process of simply extracting one combination and outputting the resulting data string.

  Also, when checking whether the correction is correct or not, if multiple combinations exist as candidates, compare the correction results for each candidate, and if all are the same, determine that the correction is correct Thus, it may be determined whether or not the correction is correct in step S56.

  Also, when checking whether the correction is correct or not, the error pointer at the location of the error pointer where the error component is 0 (parity or a symbol in the data string other than parity) may be removed, and there is no error. Then, the error pointer that has been removed is set in the symbol, and the four corrections are executed again to compare the error values.

  In other words, if the error component of the part where the error pointer is set is 0, it indicates that the symbol whose error component is 0 was not actually an error, so there was no need to set the error pointer. Yes. Therefore, the error pointer that did not need to be set is reset to another symbol and corrected in four places to confirm that no error has existed in the other symbols.

  Such verification may also be performed.

  In any case, in step S56, it is determined whether or not the correction is correct. If it is determined that the correction is correct, the process proceeds to step S17 (FIG. 5), and the corrected data string is obtained. , And supplied from the determination unit 44 to the deinterleaving unit 45. Since the processing after step S17 has already been described, the description thereof is omitted here.

  On the other hand, if it is determined in step S56 that the correction is not correct, or if it is determined in step S55 that there is no combination including 0 in the error component, the process proceeds to step S57. When the process has proceeded to step S57, the determination unit 45 indicates that there are five or more locations that are errors or that error correction has not been performed correctly for some reason. A data string that is not subjected to error correction processing is output to the deinterleaving unit 45.

  Since the processing after the data string is supplied to the deinterleaving unit 45, that is, the processing after step S17 (FIG. 5) has already been described, the description thereof is omitted here.

  In this way, when one error pointer is set in 28 symbol data of the 32 symbol data supplied to the C1 decoding unit 43, the remaining three error pointers that can be set are changed to 4 words. Three of the parities are set, and it is determined whether or not there is an error in the parity itself. In addition, by performing error correction of the data string together, it becomes possible to perform error correction with higher accuracy.

  Returning to the description of the flowchart of FIG. 6, if it is determined in step S31 that the error pointer attached to the 28-symbol data is not one place, and in step S32, it is determined that there are two places, the process proceeds to step S36. It is advanced. In step S36, the determination process 2 is executed. The determination process 2 executed in step S36 will be described with reference to the flowchart of FIG.

  In this case, since there are two error pointers in the 28 symbol data excluding the parity in the 32 symbol data, the number of error pointers that can be set to the parity is two. Therefore, error pointers are set in two of the four parities A, B, C, and D, and the C1 decoding unit 43 performs decoding. Since two parities are selected from four parities and an error pointer is set, there are six combinations. FIG. 11 shows the combinations and error components due to the combinations.

  The way of viewing the table shown in FIG. 11 is basically the same as the way of viewing the table shown in FIG.

  In step S71, four-point correction is performed with error pointers set for the symbols P1, P2, parity A, and parity B. In step S72, four-point correction is performed with the error pointers set in the symbols P1, P2, parity A, and parity C. In step S73, four-point correction is performed with error pointers set for the symbols P1, P2, parity A, and parity D.

  In step S74, four-point correction is performed with the error pointers set in the symbols P1, P2, parity B, and parity C. In step S75, four-point correction is performed with error pointers set for the symbols P1, P2, parity B, and parity D. In step S76, four-point correction is performed with error pointers set for the symbols P1, P2, parity C, and parity D.

  Thus, since two parities are selected from four parities and an error pointer is set, there are six combinations. Therefore, in steps S71 to S76, four-point correction when an error pointer is set to a different parity is performed in each step. Therefore, when the processes of steps S71 to S76 are performed in parallel, the C1 decoding unit 45 (FIG. 3) needs to be configured by six C1 decoding units.

  In step S77, since six decoding results are input to the determination unit 44, the determination unit 44 refers to the input decoding result and determines whether there is a combination including 0 in the error component. The processing after step S77 is basically the same as the processing after step S55 in FIG.

  Returning to the description of the flowchart of FIG. 6, if it is determined in step S33 that there are three error pointers attached to the 28-symbol data, the process proceeds to step S37. In step S37, determination process 3 is executed. The determination process 3 executed in step S37 will be described with reference to the flowchart of FIG.

  In this case, since there are three error pointers in the 28 symbol data excluding the parity in the 32 symbol data, the number of error pointers that can be set in the parity is one. Therefore, an error pointer is set in one of the four parities A, B, C, and D, and the C1 decoding unit 43 performs decoding. Since one parity is selected from four parities and an error pointer is set, there are four combinations. FIG. 12 shows the combinations and error components due to the combinations.

  The way of viewing the table shown in FIG. 12 is basically the same as the way of viewing the table shown in FIG.

  In step S91, four-point correction is performed with the error pointers set in the symbols P1, P2, P3, and parity A. In step S92, four-point correction is performed in the state where the error pointer is set in the symbol P1, the symbol P2, the symbol 3, and the parity B. In step S93, four-point correction is performed in the state where the error pointer is set in the symbol P1, the symbol P2, the symbol 3, and the parity C. In step S94, four-point correction is performed in the state where the error pointer is set to the symbol P1, the symbol P2, the symbol 3, and the parity D.

  Thus, since one parity is selected from the four parities and the error pointer is set, there are four combinations. Therefore, in steps S91 to S94, four-point correction when an error pointer is set to a different parity is performed in each step. Therefore, when the processes of steps S91 to S94 are performed in parallel, the C1 decoding unit 45 (FIG. 3) needs to be configured by four C1 decoding units.

  Considering this, if the C1 decoding unit 43 is configured by six C1 decoding units, as described above, when a total of four error pointers are set in 32 symbol data, the C1 decoding unit 43 is configured in parallel. Processing can be executed.

  In step S97, since four decoding results are input to the determination unit 44, the determination unit 44 refers to the input decoding result and determines whether there is a combination including 0 in the error component. . The processing after step S95 is basically the same as the processing after step S55 in FIG.

  As described above, in the present embodiment, the first number of error pointers set in the data string excluding the parity is determined, and the determination step is performed based on the parity and the second number of error pointers that can be set in the data string. When the first number of error pointers determined by the processing in (2) is small, that is, when there is an error pointer that can be assigned to parity, a range of the third number obtained by subtracting the first number from the second number Then, an error pointer is set in the parity, and decoding is performed using the parity in which the error pointer is set.

  Thus, by applying the present invention, error correction can be performed with higher accuracy.

  10 to FIG. 12 again, only the portion shown by hatching (the group including 0 as the error component) is the target of the data string output from the determination unit 44. The number of sets including 0 as an error component depends on the number of error pointers set in 28 symbol data other than parity.

  Therefore, the combination unit 42 may limit the combinations of parity for which error pointers are set at the time when the number of error pointers set for 28 symbol data other than parity is determined.

  In the above-described embodiment, the number of error pointers that can be set is four, and an example in which the number of parities is four has been described. However, the number of error pointers that can be set is the parity. In some cases, the error pointer can be set for all the parity. In such a case, there is basically only one combination. In such a case, the determination unit 44 does not need to perform processing such as selecting one combination.

  In consideration of this, the number of error pointers and the number of parity can simplify the processing performed by the determination unit 44, and the configuration in which the determination unit 44 itself is deleted depending on the design method. It is also possible to do.

  In the above-described embodiment, the example of performing the decoding using CIRC twice (two stages) has been described, but the present invention is also applied to the case where the decoding is performed a plurality of times such as three stages. It is possible to apply.

  In the above-described embodiment, the CD method has been described as an example. However, the present invention can be applied to methods other than the CD method.

The above-described series of processing (for example, decoding processing) can be executed by hardware having the respective functions, but can also be executed by software. When a series of processing is executed by software, various functions can be executed by installing a computer in which the programs that make up the software are installed in dedicated hardware, or by installing various programs. For example, it is installed from a recording medium in a general-purpose personal computer or the like.

  FIG. 13 is a diagram illustrating an internal configuration example of a general-purpose personal computer. A CPU (Central Processing Unit) 101 of the personal computer executes various processes in accordance with programs stored in a ROM (Read Only Memory) 102. A RAM (Random Access Memory) 103 appropriately stores data and programs necessary for the CPU 101 to execute various processes. The input / output interface 105 is connected to an input unit 106 including a keyboard and a mouse, and outputs a signal input to the input unit 106 to the CPU 101. The input / output interface 105 is also connected to an output unit 107 including a display and a speaker.

  Further, a storage unit 108 configured by a hard disk or the like and a communication unit 109 that exchanges data with other devices via a network such as the Internet are connected to the input / output interface 105. The drive 110 is used when reading data from or writing data to a recording medium such as the magnetic disk 121, the optical disk 122, the magneto-optical disk 123, and the semiconductor memory 124.

  As shown in FIG. 13, the recording medium is distributed to provide a program to the user separately from the personal computer, and includes a magnetic disk 121 (including a flexible disk) on which the program is recorded, an optical disk 122 (CD- Consists of package media including ROM (Compact Disc-Read Only Memory), DVD (including Digital Versatile Disc), magneto-optical disk 123 (including MD (Mini-Disc) (registered trademark)), or semiconductor memory 124 In addition, it is configured by a ROM 102 storing a program and a hard disk including a storage unit 108 provided to the user in a state of being pre-installed in a computer.

  In this specification, the steps for describing the program provided by the medium are performed in parallel or individually in accordance with the described order, as well as the processing performed in time series, not necessarily in time series. The process to be executed is also included.

  Further, in this specification, the system represents the entire apparatus constituted by a plurality of apparatuses.

It is a systematic diagram of an example of the conventional CIRC encoder. It is a systematic diagram of an example of the conventional CIRC decoder. It is a systematic diagram of one Embodiment of the CIRC decoder of this invention. It is a functional block diagram of one embodiment of a CIRC decoder of the present invention. It is a flowchart for demonstrating a decoding process. It is a flowchart for demonstrating a determination process. 5 is a flowchart for explaining determination processing 1; 10 is a flowchart for explaining determination processing 2; 10 is a flowchart for explaining determination processing 3; It is a figure for demonstrating an error component. It is a figure for demonstrating an error component. It is a figure for demonstrating an error component. It is a figure explaining a medium.

Explanation of symbols

  21 input unit, 21a descrambling unit, 21b inverter unit, 22 C1 decoding unit, 23 deinterleaving unit, 24 C2 decoding unit, 25 cross delay processing unit, 40 decoder, 41 interleaving unit, 42 combination unit, 43 C1 decoding Section, 44 determination section, 45 deinterleaving section, 46 C2 decoding section

Claims (5)

Determination means for determining a first number of error pointers set in a data string excluding parity;
When the first number of error pointers determined by the determination means is less than the second number of error pointers that can be set in the parity and the data string, the first number is changed from the second number to the first number. Setting means for setting an error pointer in the parity within a range of the subtracted third number;
An information processing apparatus comprising: decoding means for performing decoding using a parity in which an error pointer is set by the setting means. The setting means, when the number of parity is larger than the third number, to change the combination of parity to set the error pointer;
2. The information processing apparatus according to claim 1, wherein the decoding unit decodes the data string for each of the combinations, and sets a decoding result including a set including an error component of 0 in the decoding result. The information processing apparatus according to claim 1, wherein the decoding unit decodes the data sequence based on CIRC (Circular Interleave Reed-solomon Code). A determination step of determining a first number of error pointers set in a data string excluding parity;
When the first number of error pointers determined by the processing of the determination step is less than the second number of error pointers that can be set in the parity and the data string, the first number from the second number A setting step for setting an error pointer in the parity within a range of a third number obtained by subtracting a number;
And a decoding step of performing decoding using a parity in which an error pointer is set by the processing of the setting step. A determination step of determining a first number of error pointers set in a data string excluding parity;
When the first number of error pointers determined by the processing of the determination step is less than the second number of error pointers that can be set in the parity and the data string, the first number from the second number A setting step for setting an error pointer in the parity within a range of a third number obtained by subtracting a number;
A program causing a computer to execute a process including a decoding step of performing decoding using a parity in which an error pointer is set by the process of the setting step.

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