JP2006003792A - Display device and driving method for display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device capable of preventing wrong discharge of a pixel cell to be set in an extinction state, by using a plasma display panel having a cell structure in which a selection cell and a display cell are separated, and to provide a driving method for the display panel. <P>SOLUTION: The display device is equipped with an address means for generating address discharge within the selection cell by successively applying pixel data pulse, corresponding to pixel data to each other of column electrodes by one display line each simultaneously with a scanning pulse, while successively applying the scanning pulse to one row electrode of the row electrode pair of the display panel in an address period; a sustaining means for applying a sustain pulse of the polarity reverse from the polarity of the scanning pulse to each of the row electrodes constituting the row electrode pair in a sustain period; and an auxiliary discharge means for generating the auxiliary discharge of the reverse polarity from the polarity of the selection discharge within the selection cell by applying an auxiliary pulse between the one row electrode of the row electrode pair and the column electrode, after the end of the address period and before the start of the sustain period. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device including a display panel and a driving method for driving the display panel.

2. Description of the Related Art In recent years, a plasma display device equipped with a surface discharge AC plasma display panel as a large and thin color display panel has attracted attention (see, for example, Patent Document 1).
JP, 5-205642, A As a surface discharge system AC type plasma display panel, the panel in which the pixel cell which bears each pixel consists of a selection cell and a display cell is known (for example, patent documents 2 or patent documents 3). reference). In the panel, a front substrate and a rear substrate disposed opposite to each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on the inner surface of the front substrate, and a row electrode pair intersecting with the inner surface of the rear substrate. A plurality of arranged column electrodes, a display cell at each intersection of the row electrode pair and the column electrode, a light absorption layer on the substrate side, and a light absorption layer on the back substrate side A pixel cell composed of the selected cell is formed. In the display cell, one row electrode constituting the row electrode pair and the other row electrode face each other in the discharge space, and in the selected cell, the column electrode and one row electrode of the row electrode pair are discharged. Opposite in space. When driving a plasma display panel, there is at least an address period for performing an operation for determining whether each pixel cell is turned on or off, and a sustain period for maintaining a discharge for lighting. In the selected cell of the pixel cell to be in a state, discharge (selective discharge) is performed between one of the row electrode pairs and the row electrode in the address period, and in the display cell of the pixel cell, discharge is performed between the row electrode pair in the sustain period. This is performed and the lighting state is maintained. On the other hand, in the selected cell of the pixel cell to be turned off, erase discharge is performed between one of the row electrode pairs and the row electrode in the address period, and in the display cell of the pixel cell, discharge is performed between the row electrode pair in the sustain period. Does not occur, and the extinguished state is maintained. JP 2003-31130 A JP 2003-086108 A

  As described above, in a display panel having a cell structure in which a selected cell and a display cell are separated, in order to draw a selective discharge generated in the selected cell into the display cell and set the display cell in a lit state or an unlit state, It is necessary to apply a relatively high voltage pulse between one of the row electrodes (scanning electrode) and the column electrode. However, depending on the wall charge distribution state in the selected cell immediately before the address period, an erroneous discharge occurs in the selected cell of the pixel cell to be set to the extinguished state in the sustain period, and the erroneous discharge further causes a row in the display cell. There is a possibility that a sustaining (sustaining) discharge is generated between the electrode pairs, resulting in a lighting state.

  The problems to be solved by the present invention include the above-mentioned problem as an example, and a display panel having a cell structure in which a selected cell and a display cell are separated from each other is used to turn off a pixel cell to be set to a light-off state. It is an object of the present invention to provide a display device capable of preventing erroneous discharge and a method for driving the display panel.

  According to the display device of the first aspect of the present invention, a display period of one field is constituted by a plurality of subfields having an address period and a sustain period in accordance with pixel data for each pixel based on an input video signal, and image display is performed. A front substrate and a rear substrate disposed opposite to each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on an inner surface of the front substrate, and the row electrode pair on an inner surface of the rear substrate. A plurality of column electrodes arranged intersecting each other, and at each intersection of the row electrode pair and the column electrode, a display cell, a light absorption layer is provided on the front substrate side, and on the rear substrate side The display panel having a unit light emitting region formed of a selected cell provided with a secondary electron emission layer, and the scanning while sequentially applying a scanning pulse to one row electrode of the row electrode pair in the address period. Simultaneous with pulse Address means for sequentially applying a pixel data pulse corresponding to the pixel data to each of the column electrodes one display line at a time to generate an address discharge in the selected cell, and a row constituting the row electrode pair in the sustain period Sustain means for applying a sustain pulse having a polarity opposite to that of the scan pulse to each of the electrodes, and between the one row electrode and the column electrode of the row electrode pair after the end of the address period and before the start of the sustain period. And an auxiliary discharge means for generating an auxiliary discharge having a polarity opposite to that of the selected discharge in the selected cell by applying an auxiliary pulse to the selected cell.

  According to a fifth aspect of the present invention, there is provided a display panel driving method comprising: a front substrate and a rear substrate disposed opposite to each other across a discharge space; a plurality of row electrode pairs provided on an inner surface of the front substrate; A plurality of column electrodes arranged on the inner surface so as to intersect the row electrode pair, and a display cell and a light absorption layer on the front substrate side are provided at each intersection of the row electrode pair and the column electrode. And a display panel having a unit light emitting region formed of a selected cell provided with a secondary electron emission layer on the back substrate side is driven according to pixel data for each pixel based on an input video signal to display an image. A display period of one field for the input video signal is composed of a plurality of subfields having an address period and a sustain period, and one row electrode of the row electrode pair in the address period. Scan to The pixel data pulse corresponding to the pixel data is sequentially applied to each column electrode one display line at a time simultaneously with the scanning pulse while sequentially applying the pulse, causing an address discharge in the selected cell, and in the sustain period, A sustain pulse having a polarity opposite to that of the scan pulse is applied to each of the row electrodes constituting the row electrode pair, and one row electrode of the row electrode pair after the end of the address period and before the start of the sustain period And an auxiliary pulse is applied between the column electrodes to cause an auxiliary discharge having a polarity opposite to that of the selective discharge in the selected cell.

  FIG. 1 is a diagram showing a configuration of a plasma display device as a display device according to the present invention.

  As shown in FIG. 1, the plasma display device includes a PDP 50 as a plasma display panel, an X electrode driver 51, a Y electrode driver 53, an address driver 55, and a drive control circuit 56.

The PDP 50 is formed with strip-like column electrodes D _{1 to} D _m that extend in the vertical direction on the display screen. Furthermore, the PDP 50, the row electrodes X ₁ to X _n and row electrodes Y ₁ to Y _n are each stretched in the horizontal direction of the display screen is formed by arranging the numerical order and alternately, as shown in FIG. 1 ing. Each of the pair of row electrodes, that is, the row electrode pair (X ₁ , Y ₁ ) to the row electrode pair (X _n , Y _n ) serves as the first display line to the nth display line in the PDP 50. A pixel cell (unit light emitting region) PC that bears a pixel is formed at each intersection (region surrounded by a one-dot chain line in FIG. 1) between each display line and each of the column electrodes D _{1 to} D _m . That is, the PDP 50 belongs to the pixel cells PC ₁ , ₁ to PC ₁ , _m belonging to the first display line, the pixel cells PC 2, _{1 to} PC 2, _m ,... Belonging to the second display line, to the nth display line. pixel cell PC _n, 1~PC _{n, m} is what is arranged in a matrix.

  2 to 5 are diagrams showing a part of the internal structure of the PDP 50. FIG.

  FIG. 2 is a plan view of the PDP 50 as viewed from the display surface side. 3 is a cross-sectional view of the PDP 50 as viewed from the line V1-V1 shown in FIG. 4 is a cross-sectional view of the PDP 50 as viewed from the line V2-V2 shown in FIG. FIG. 5 is a cross-sectional view of the PDP 50 viewed from the line W1-W1 shown in FIG.

  As shown in FIG. 2, the row electrode Y includes a strip-like bus electrode Yb (a main body portion of the row electrode Y) extending in the horizontal direction of the display screen and a plurality of transparent electrodes Ya connected to the bus electrode Yb. Is done. The bus electrode Yb is made of, for example, a black metal film. The transparent electrode Ya is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Yb. The transparent electrode Ya extends in a direction perpendicular to the bus electrode Yb, and has one end and the other end that are wide as shown in FIG. That is, the transparent electrode Ya can be regarded as a protruding electrode protruding from the main body of the row electrode Y. The row electrode X includes a strip-shaped bus electrode Xb (a main body portion of the row electrode X) extending in the horizontal direction of the display screen and a plurality of transparent electrodes Xa connected to the bus electrode Xb. The bus electrode Xb is made of, for example, a black metal film. The transparent electrode Xa is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Xb. The transparent electrode Xa extends in a direction orthogonal to the bus electrode Xb, and one end thereof has a wide shape as shown in FIG. That is, the transparent electrode Xa can be regarded as a protruding electrode protruding from the main body of the row electrode X. As shown in FIG. 2, the wide portions of the transparent electrodes Xa and Ya are arranged to face each other with a discharge gap g having a predetermined width. That is, the transparent electrodes Xa and Ya as protruding electrodes protruding from the main body portions of the paired row electrodes X and Y are arranged to face each other via the discharge gap g.

  The row electrode Y composed of the transparent electrode Ya and the bus electrode Yb and the row electrode X composed of the transparent electrode Xa and the bus electrode Xb are formed on the back surface of the front transparent substrate 10 serving as the display surface of the PDP 50 as shown in FIG. ing. Further, a dielectric layer 11 is formed on the back surface of the front transparent substrate 10 so as to cover the row electrodes X and Y. A raised dielectric layer 12 protruding from the dielectric layer 11 toward the back side is formed at a position corresponding to each selected cell C2 (described later) on the surface of the dielectric layer 11. The raised dielectric layer 12 is composed of a strip-shaped light absorbing layer containing a black or dark pigment, and is formed to extend in the horizontal direction of the display surface as shown in FIG. The surface of the raised dielectric layer 12 and the surface of the dielectric layer 11 where the raised dielectric layer 12 is not formed are covered with a protective layer (not shown) made of MgO (magnesium oxide). On the rear substrate 13 arranged in parallel to the front transparent substrate 10, a plurality of column electrodes D extending in a direction (vertical direction) orthogonal to the bus electrodes Xb and Yb are opened with a predetermined gap therebetween. They are arranged in parallel. A white column electrode protective layer (dielectric layer) 14 that covers the column electrode D is formed on the rear substrate 13. On the column electrode protective layer 14, a partition wall 15 including a first horizontal wall 15A, a second horizontal wall 15B, and a vertical wall 15C is formed. The first horizontal wall 15A is formed to extend in the horizontal direction of the display surface at a position on the column electrode protection layer 14 facing the bus electrode Xb. The second horizontal wall 15B is formed to extend in the horizontal direction of the display surface at a position on the column electrode protection layer 14 facing the bus electrode Yb. The vertical wall 15C is formed to extend in a direction orthogonal to the bus electrode Xb (Yb) at a position between the transparent electrodes Xa (Ya) arranged at equal intervals on the bus electrode Xb (Yb). ing.

In addition, as shown in FIG. 3, secondary electrons are present in the region (including the side surfaces of the vertical wall 15 </ b> C, the first horizontal wall 15 </ b> A, and the second horizontal wall 15 </ b> B) facing the raised dielectric layer 12 on the column electrode protective layer 14. A release material layer 30 is formed. The secondary electron emission material layer 30 is a layer made of a high γ material having a low work function (for example, 4.2 eV or less) and a high so-called secondary electron emission coefficient. Examples of materials used as the secondary electron emission material layer 30 include alkaline earth metal oxides such as MgO, CaO, SrO, and BaO, alkali metal oxides such as Cs ₂ O, fluorides such as CaF ₂ and MgF _{2, and the} like. There are TiO ₂ , Y ₂ O ₃ , or materials whose secondary electron emission coefficient is increased by crystal defects or impurity doping, diamond-like thin films, carbon nanotubes, and the like. On the other hand, in regions other than the region facing the raised dielectric layer 12 on the column electrode protective layer 14 (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B), as shown in FIG. A body layer 16 is formed. There are three types of phosphor layers 16: a red phosphor layer that emits red light, a green phosphor layer that emits green light, and a blue phosphor layer that emits blue light, and the assignment is determined for each pixel cell PC. A discharge space filled with a discharge gas exists between the secondary electron emission material layer 30 and the phosphor layer 16 and the dielectric layer 11. The height of each of the first horizontal wall 15A, the second horizontal wall 15B, and the vertical wall 15C is not so high as to reach the surface of the raised dielectric layer 12 or the dielectric layer 11, as shown in FIGS. Therefore, as shown in FIG. 3, there is a gap r between the second lateral wall 15B and the raised dielectric layer 12 through which the discharge gas can flow. Between the first lateral wall 15A and the raised dielectric layer 12, a dielectric layer 17 extending in the direction along the first lateral wall 15A is formed to prevent discharge interference. Further, between the vertical wall 15C and the raised dielectric layer 12, a dielectric layer 18 is intermittently formed in a direction along the vertical wall 15C as shown in FIG.

  Here, a region surrounded by the first horizontal wall 15A and the vertical wall 15C (a region surrounded by an alternate long and short dash line in FIG. 2) is a pixel cell PC that carries a pixel. Further, as shown in FIGS. 2 and 3, the pixel cell PC is divided into a display cell C1 (first discharge cell) and a selection cell C2 (second discharge cell) by the second lateral wall 15B. As shown in FIGS. 2 and 3, the display cell C <b> 1 includes a pair of row electrodes X and Y that bear a display line, and a phosphor layer 16. On the other hand, the selected cell C2 includes a row electrode Y of a pair of row electrodes that bears the display line, a row electrode X of a pair of row electrodes that bears a display line adjacent to the display surface of the display line, A raised dielectric layer 12 and a secondary electron emission material layer 30 are included. In the display cell C1, as shown in FIG. 2, a wide portion formed at one end of the transparent electrode Xa of the row electrode X, and a wide portion formed at one end of the transparent electrode Ya of the row electrode Y Are arranged opposite to each other via the discharge gap g. On the other hand, in the selected cell C2, the wide portion formed at the other end of the transparent electrode Ya is included, but the transparent electrode X is not included.

  Further, as shown in FIG. 3, the discharge spaces of the pixel cells PC adjacent to each other in the vertical direction of the display surface (the horizontal direction in FIG. 3) are blocked by the first horizontal wall 15 </ b> A and the dielectric layer 17. However, the discharge spaces of the display cell C1 and the selected cell C2 belonging to the same pixel cell PC communicate with each other through a gap r as shown in FIG. Further, the discharge spaces of the selected cells C2 adjacent to each other in the left-right direction of the display surface are blocked by the raised dielectric layer 12 and the dielectric layer 18 as shown in FIG. The discharge spaces of the display cells C1 to be communicated with each other.

Thus, the pixel cells PC1 formed on PDP 50, ₁ to PC _n, each _m is constructed from the display discharge space is communicated with the cell C1 and selection cell C2 to each other.

The X electrode driver 51 corresponds to the row electrodes X ₁ , X ₂ , X ₃ , X ₄ , X ₅ ,..., X _n−1 and X _{n of} the PDP 50 according to the timing signal supplied from the drive control circuit 56. Various drive pulses are applied to each _n . The electrode driver 53 responds to the timing signal supplied from the drive control circuit 56, and the row electrodes Y ₁ , Y ₂ , Y ₃ , Y ₄ , Y ₅ ,..., Y _n-1 and Y _{n of the} PDP 50. Various drive pulses are applied to each. The address driver 55 applies pixel data pulses to the column electrodes D _{1 to} D _m of the PDP 50 in accordance with the timing signal supplied from the drive control circuit 56.

  First, the drive control circuit 56 converts the input video signal into, for example, 8-bit pixel data representing the luminance level for each pixel, and performs error diffusion processing and dither processing on the pixel data. For example, in the error diffusion process, first, the upper 6 bits of pixel data are used as display data, and the remaining lower 2 bits are used as error data. Then, the weighted addition of each error data of the pixel data corresponding to each peripheral pixel is reflected in the display data. With such an operation, the luminance of the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore the luminance equivalent to the 8-bit pixel data is obtained with 6-bit display data smaller than 8 bits. Gradation can be expressed. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are processed as one pixel group, and dither coefficients each having a different coefficient value are assigned and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel group. Thus, dither addition pixel data is obtained. According to the addition of the dither coefficient, each pixel group can express the luminance corresponding to 8 bits only by the upper 4 bits of the dither addition pixel data.

The drive control circuit 56 converts the 8-bit pixel data into 4-bit multi-gradation pixel data PD _S by these error diffusion processing and dither processing, and further converts the multi-gradation pixel data PD _S into FIG. It is converted into 15-bit pixel drive data GD according to the data conversion table as shown. As a result, pixel data capable of expressing 256 gradations in 8 bits is converted into 15-bit pixel drive data GD consisting of 16 patterns in total. Next, the drive control circuit 56, one screen of pixel drive data GD _{1, 1} to GD n, for each _m, the separation of these pixel drive data GD _{1, 1} to GD n, _m each at the same bit digit with each other As a result, pixel drive data bit groups DB1 to DB15 are obtained. For each of the subfields SF1 to SF15, the drive control circuit 56 supplies the data bits in the pixel drive data bit group DB corresponding to the subfield to the address driver 55 by one display line (m).

  FIG. 7 is a diagram showing a light emission drive sequence when the PDP 50 is driven by gradation using the selective erasure address method.

  In the light emission drive sequence shown in FIG. 7, the display period of each field in the video signal is divided into 15 subfields SF1 to SF15, and the address process W and the sustain process I are executed in each subfield. In the first subfield SF1 of the plurality of subfields, the simultaneous reset process R is executed prior to the address process W, and the erase process E is executed immediately after the sustain process I in the last subfield SF15. Further, the auxiliary discharge process AD is provided before the start of the sustain process I for the pixel cells in which the erase address discharge has occurred in the address process W. The period during which the address process W is executed is an address period, and the period during which the sustain process I is executed is a sustain period.

First, in the simultaneous reset process R of the subfield SF1, the Y electrode driver 53 generates a reset pulse RP _Y that has a gradual downward change compared to a sustain pulse described later, and each of the row electrodes Y _{1 to} Y _n of the PDP 50. Are applied simultaneously. Further, at the same timing as the reset pulse RP _Y , the X electrode driver 51 generates the reset pulse RP _X and applies it simultaneously to each of the row electrodes X _{1 to} X _n of the PDP 50. During this time, the address driver 55 simultaneously applies to each of the column electrodes D ₁ to D _m of the PDP50 and generates a reset pulse RP _D. In response to the application of these reset pulses RP _D , RP _Y and RP _X , a reset discharge (write discharge) is generated between the column electrode D and the row electrode Y in the selected cell C2 of each of the pixel cells PC of the PDP 50. A wall charge is formed in the selected cell C2. Then, the reset discharge moves to the display cell C1 side through the gap r shown in FIG. 3, and discharge is generated between the row electrodes Y and X in the display cell C1. Due to such discharge transition, wall charges are formed in the display cells C1 of all the image cells PC.

  As described above, in the simultaneous reset process R based on the selective erasure address method, wall charges are formed in the display cells C1 of all the pixel cells PC of the PDP 50, and all these pixel cells PC are initialized to the lighting cell mode.

Next, in subfields SF1~SF15 each address step W, while the Y electrode driver 53 applies a negative voltage V1 to all the row electrodes Y ₁ to Y _n, a positive polarity voltage V2 (V2> V1) Are sequentially applied to the row electrodes Y _{2 to} Y _n . During this time, the X electrode driver 51 sets each of the row electrodes X _{1 to} X _n to 0V. The address driver 55 converts each data bit in the pixel drive data bit group DB1 corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, the address driver 55 converts a logic level 0 pixel drive data bit into a positive high voltage pixel data pulse DP, while converting a logic level 1 pixel drive data bit into a low voltage (0 volt) pixel data pulse. Convert to DP. Then, the pixel data pulse DP is applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronization with the application timing of the scanning pulse SP. In other words, the address driver 55 first applies a pixel data pulse group DP ₁ composed of m pixel data pulses DP corresponding to the first display line to the column electrodes D _{1 to} D _m , and then the second display line. is the pixel data pulse group DP ₂ comprised of m pixel data pulses DP corresponding to the column electrodes D ₁ to D _m in. An erase address discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the scan pulse SP having the positive voltage V2 and the low-voltage (0 volt) pixel data pulse DP are simultaneously applied. Is born. Then, along with the erase address discharge, the discharge moves to the display cell C1 side through the gap r shown in FIG. 3, and a discharge is generated between the row electrodes Y and X in the display cell C1. As described above, the wall charges formed in the display cell C1 disappear due to the discharge transition from the selected cell C2 to the display cell C1. On the other hand, no erase address discharge as described above occurs in the selected cell C2 of the pixel cell PC to which the high-voltage pixel data pulse DP is applied although the scan pulse SP is applied. Therefore, since the discharge transfer from the selected cell C2 to the display cell C1 as described above does not occur, the current state of the wall charge formation in the display cell C1 is maintained. That is, when the wall charge is present in the display cell C1, it remains as it is. When the wall charge is not present, the wall charge is not formed in the wall charge.

  As described above, in the address process W based on the selective erase address method, an erase address discharge is selectively generated in the selected cell C2 of each pixel cell PC in accordance with each data bit of the pixel drive data bit group corresponding to the subfield. To erase the wall charges. As a result, the pixel cell PC in which wall charges remain is set in the lighted cell mode, and the pixel cell PC from which wall charges have been erased is set in the extinguished cell mode.

Next, in subfields SF1~SF15 each sustain stage I, are each X electrode driver 51 and the Y electrode driver 53, the sustain pulse IP _X, alternately to the row electrodes X ₁ to X _n and Y ₁ to Y _n Apply IP _Y. The number of times the sustain pulse IP is applied is a number corresponding to luminance weighting for each of the subfields SF1 to SF15. Sustain discharge is generated by the application of the sustain pulses IP _X and IP _Y , and the light emission state associated with the discharge is maintained.

  Only the pixel cell set as the lighted cell in the address process W in each subfield repeats light emission in the sustain process I immediately after that. At this time, halftone luminance is expressed by the total number of light emissions performed in each of the subfields SF1 to SF15 in one field.

In the erase process of the subfield SF15 E, the address driver 55 applies this by generating an erase pulse EP1 to the column electrodes D ₁ to D _m. Further, the second sustain driver 8 generates an erase pulse EP2 having a polarity opposite to that of the erase pulse EP1 simultaneously with the application timing of the erase pulse EP1, and applies it to the row electrodes Y _{1 to} Y _n . By simultaneously applying these erase pulses EP1 and EP2, an erase discharge is generated in the selected cell C2 of all the pixel cells PC in the PDP 50, and the wall charges remaining in all the pixel cells are extinguished. That is, by this erasing discharge, all the pixel cells in the PDP 50 are turned off.

  For the pixel cell PC set in the extinguished cell mode, the auxiliary discharge process AD is executed. In the auxiliary discharge process AD, the positive first auxiliary pulse AP1 is applied to the column electrode D, and at the same time, the negative second auxiliary pulse AP2 is applied to the row electrode Y. The first auxiliary pulse AP1 is a pulse having a square waveform, and the second auxiliary pulse AP2 is a pulse having a gently descending waveform. By applying the first and second auxiliary pulses AP1 and AP2, a weak discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel PC.

  FIG. 8 shows that after an erase address discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC in the address process W of the subfield SFi (i is any one of 2 to 15). Each pulse and the wall charge distribution state when the first and second auxiliary pulses are applied in the auxiliary discharge process AD are shown. After the sustain discharge is generated between the row electrodes X and Y in the sustain process I of the subfield SFi-1 before the subfield SFi, the wall charge distribution state at the start time of the subfield SFi is as follows in the selected cell C2. Negative wall charges − are formed on the column electrodes D, and positive wall charges + are formed on the row electrodes Y. A negative wall charge − is formed on the row electrode X in the display cell C1, and a positive wall charge + is formed on the row electrode Y. In FIG. 8, the wall charge − is indicated by a circle having −, and the wall charge + is indicated by a circle having +. In the address step W of the subfield SFi, a low-voltage pixel data pulse DP is applied to the column electrode D, and a scanning pulse SP is applied to the row electrode Y. As a result, an erase address discharge is generated between the column electrode D and the row electrode Y in the selected cell C2. Along with the erase address discharge, the discharge moves to the display cell C1 side through the gap r shown in FIG. 3 (arrow A1 in FIG. 8). A negative wall charge − is formed in the electrode. A positive wall charge + is formed on the column electrode of the display cell C1. The potential due to the wall charges between the row electrodes X and Y of the display cell C1 becomes less than a predetermined value, and the pixel cell PC enters the extinguished cell state.

In the subsequent auxiliary discharge stroke AD, the first auxiliary pulse AP1 is applied to the column electrode D, and at the same time, the second auxiliary pulse AP2 is applied to the row electrode Y. Therefore, a weak discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel PC. As a result, a negative wall charge − is formed on the column electrode D in the selected cell C2, and the row electrode Positive wall charges + are formed on Y (in FIG. 8, the wall charges hatched in the circles). That is, the polarities of the wall charges of the column electrode D and the row electrode Y in the selected cell C2 are reversed. On the other hand, there is no change in the wall charges at the row electrode X and the row electrode Y in the display cell C1 at this time. Therefore, in the sustain process I of the subfield SFi, the sustain discharge does not occur between the row electrodes X and Y even when the sustain pulses IP _X and IP _Y are applied, and no erroneous discharge occurs in the selected cell C2.

FIG. 9 shows that the first and second auxiliary pulses are not applied after the erase address discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC in the address process W of the subfield SFi. The wall charge distribution state in the case is shown. The pulse application and the wall charge distribution state up to the end of the address process W in the subfield SFi are the same as those shown in FIG. In the case of FIG. 9, immediately after the end of the address process W, the process proceeds to the sustain process, and in the sustain process I of the subfield SFi, the sustain pulse IP _Y applied to the row electrode Y in the column in the selected cell C2 of the pixel PC. There is a possibility that an erroneous discharge occurs between the electrode D and the row electrode Y as shown in FIG. When an erroneous discharge occurs, the erroneous discharge moves to the display cell C1 side through the gap r shown in FIG. 3 (arrow A2 in FIG. 9), and as a result, the row electrode Y in the display cell C1 has a positive polarity. Wall charge + is formed. Therefore, the sustain discharge is repeated by the sustain pulses IP _X and IP _Y that are alternately generated, and then the same as the state in which writing is performed as the lighting cell.

On the other hand, in the above-described embodiment, the polarity of the wall charges of the column electrode D and the row electrode Y in the selected cell C2 is inverted by the application of the first and second auxiliary pulses in the auxiliary discharge process AD, so that the column electrode D A negative wall charge − is formed on the upper side, and a positive wall charge + is formed on the row electrode Y. Accordingly, suspension by application of sustain pulse IP _Y that erroneous discharge occurs between the column electrode D and the row electrode Y within the select cell C2 is prevented in the sustain process I.

  In the above-described embodiment, the first auxiliary pulse AP1 is applied to the column electrode D and the second auxiliary pulse AP2 is applied to the row electrode Y in the auxiliary discharge process AD, thereby causing weak auxiliary discharge in the selected cell C2. Although the configuration is shown, the application of the first auxiliary pulse AP1 is omitted in the auxiliary discharge process AD, the second auxiliary pulse AP2 is applied only to the row electrode Y, and the row electrode Y and the column electrode D are connected in the selected cell C2. You may comprise so that a weak auxiliary discharge may be produced in between.

  Further, the unit of field and subfield used in the above-described embodiment is a case where an interlace video signal such as the NTSC system is taken into consideration. In the non-eater race video signal, the frame (screen) and the frame display period are used. Corresponds to a subframe which is a divided period.

  As described above, according to the present invention, the scanning pulse is sequentially applied to one row electrode of the row electrode pair of the display panel in the address period, and the pixel data pulse corresponding to the pixel data is simultaneously applied to the scanning data one display line at a time. Address means for sequentially applying each column electrode to cause an address discharge in the selected cell; and sustain means for applying a sustain pulse having a polarity opposite to the scan pulse to each of the row electrodes constituting the row electrode pair in the sustain period; After the end of the address period and before the start of the sustain period, an auxiliary pulse is applied between one row electrode and the column electrode of the row electrode pair to cause an auxiliary discharge having a polarity opposite to that of the selective discharge in the selected cell. Discharge means, so that the display panel having a cell structure in which the selected cell and the display cell are separated should be set to a light-off state. It is possible to prevent the erroneous discharge of the pixel cell.

It is a figure which shows schematic structure of the plasma display apparatus to which this invention is applied. It is the top view which looked at a part of structure of PDP in the apparatus of FIG. 1 from the display surface side. It is a figure which shows the cross section of PDP on the V1-V1 line | wire shown by FIG. It is a figure which shows the cross section of PDP on the V2-V2 line | wire shown by FIG. It is a figure which shows the cross section of PDP on the W1-W1 line | wire shown by FIG. It is a figure which shows the light emission drive pattern based on the pixel data conversion table in the selective erasure address method, and the pixel drive data GD obtained by this pixel data conversion table. It is a figure which shows an example of the light emission drive sequence at the time of the drive by the selective erase address method. Each pulse and wall charge distribution state when the first and second auxiliary pulses are applied in the auxiliary discharge process after the erase address discharge is generated are shown. Each pulse and wall charge distribution state when the first and second auxiliary pulses are not applied after the erase address discharge is generated are shown.

Explanation of symbols

50 PDP
51 X electrode driver 53 Y electrode driver 55 Address driver 56 Drive control circuit C1 Display cell C2 Selection cell PC Pixel cell

Claims (5)

According to pixel data for each pixel based on an input video signal, a display device configured to display an image by configuring a display period of one field by a plurality of subfields having an address period and a sustain period,
A front substrate and a rear substrate arranged opposite to each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on the inner surface of the front substrate, and a plurality of rows arranged on the inner surface of the rear substrate so as to intersect the row electrode pairs A display cell, a light absorption layer on the front substrate side, and a secondary electron emission layer on the back substrate side at each intersection of the row electrode pair and the column electrode. A display panel in which a unit light emitting region composed of selected cells is formed;
In the address period, a scan pulse is sequentially applied to one row electrode of the row electrode pair, and simultaneously with the scan pulse, a pixel data pulse corresponding to the pixel data is sequentially applied to each column electrode for each display line. Address means for causing an address discharge in the selected cell;
Sustaining means for applying a sustain pulse having a polarity opposite to that of the scan pulse to each of the row electrodes constituting the row electrode pair in the sustain period;
After the end of the address period and before the start of the sustain period, an auxiliary pulse is applied between one row electrode and the column electrode of the row electrode pair to reverse polarity to the selected discharge in the selected cell. A display device comprising: auxiliary discharge means for generating auxiliary discharge.   The display device according to claim 1, wherein the scanning pulse is a positive pulse, and the pixel data pulse is a pulse having a negative polarity with respect to the scanning pulse.   The auxiliary pulse has a first auxiliary pulse having a first polarity applied to the column electrode, and a first waveform having a gradually falling waveform applied to one row electrode of the row electrode pair simultaneously with the first auxiliary pulse. The display device according to claim 1, comprising a second auxiliary pulse having two polarities.   2. The display device according to claim 1, wherein the polarity of wall charges on the column electrode and on one row electrode of the row electrode pair in the selective discharge is reversed by the auxiliary discharge. A front substrate and a rear substrate arranged opposite to each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on the inner surface of the front substrate, and a plurality of rows arranged on the inner surface of the rear substrate so as to intersect the row electrode pairs A display cell, a light absorption layer on the front substrate side, and a secondary electron emission layer on the back substrate side at each intersection of the row electrode pair and the column electrode. A driving method for displaying an image by driving a display panel formed with a unit light emitting area composed of selected cells according to pixel data for each pixel based on an input video signal,
A display period of one field for the input video signal is composed of a plurality of subfields having an address period and a sustain period,
In the address period, a scan pulse is sequentially applied to one row electrode of the row electrode pair, and simultaneously with the scan pulse, a pixel data pulse corresponding to the pixel data is sequentially applied to each column electrode for each display line. Causing an address discharge in the selected cell;
In the sustain period, a sustain pulse having a polarity opposite to that of the scan pulse is applied to each of the row electrodes constituting the row electrode pair,
After the end of the address period and before the start of the sustain period, an auxiliary pulse is applied between one row electrode and the column electrode of the row electrode pair to reverse polarity to the selected discharge in the selected cell. A driving method characterized by causing an auxiliary discharge to occur.

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