JP2006003250A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a fault detection rate by improving the controllability of a logic circuit having a poor controllability at a scan mode operation. <P>SOLUTION: In an integrated circuit including a scan circuit, a selector SEL2 is inserted into a data path to the logic circuit LGX being driven through a data input terminal DIN2 also served as a scan controlling terminal, and at the scan mode operation, a data signal being input from a data input terminal DIN3 other than the data input terminal DIN2 is selected and input to the logic circuit LGX, thereby improving the controllability of the logic circuit LGX at the scan mode operation. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an integrated circuit, and more particularly to an integrated circuit including a scan test circuit.

  Generally, when a large-scale integrated circuit (hereinafter referred to as LSI) is shipped to the market, a pass / fail judgment test is performed by an LSI tester. The test pattern used at this time needs to find as many fault locations as possible in the logic circuit constituting the LSI.

  However, with the increase in the scale of logic circuits, the amount of test vectors and the test time become enormous when trying to test all of the logic circuits. Therefore, in order to solve this problem, so-called design for testability is performed.

  This design for testability is a design technique in which the LSI test policy is fixed at the LSI design stage and a test circuit is incorporated in the LSI. There is a concept of observability and controllability as basic indicators of whether or not LSI testing can be easily performed. A circuit with good observability is a circuit whose logic value is easy to observe from outside the circuit, and a circuit with good controllability is the logic value of a node in the circuit. It is easy to set by external data input. A circuit having better observability and controllability can more easily create an effective test pattern, and as a result, the failure detection rate of the logic circuit constituting the LSI is improved.

  A scan test circuit is known as a test circuit with improved observability and controllability. FIG. 2 is a circuit diagram showing a part of an LSI having a conventional scan test circuit. In the LSI, four logic circuits LG1 to LG4 are arranged, and three scan flip-flop circuits SFF1 to SFF3 for scan test are arranged between the logic circuits LG1 to LG4.

  The first-stage scan flip-flop circuit SFF1 includes a flip-flop circuit FF1, a scan test signal from the data input terminal DIN according to the scan enable signal SCANEN, and an output of the logic circuit LG1 according to the scan test signal. A multiplexer MPX1 is provided for selectively inputting any one to the data input terminal D of the flip-flop circuit FF1. The second-stage scan flip-flop circuit SFF2 corresponds to the output signal (scan test signal) from the output terminal Q of the previous-stage flip-flop FF1 in accordance with the flip-flop circuit FF2 and the scan enable signal SCANEN. A multiplexer MPX2 for selectively inputting one of the output signals of the logic circuit LG2 to the data input terminal D of the flip-flop circuit FF2 is provided.

  Similarly, the third-stage scan flip-flop circuit SFF3 outputs an output signal (scan test signal) from the output terminal Q of the previous flip-flop FF2 and its output signal in response to the flip-flop circuit FF3 and the scan enable signal SCANEN. Is provided with a multiplexer MPX3 for selectively inputting any one of the output signals of the logic circuit LG3 to the data input terminal D of the flip-flop circuit FF3. A clock is commonly input from the clock terminal CLK to the clock input terminals C of the flip-flop circuits FF1 to FF3. A selector SEL1 for selectively outputting either the output of the flip-flop circuit FF3 or the output signal of the logic circuit LG4 to the data output terminal Dout according to the scan enable signal SCANEN.

  There are a shift mode and a capture mode as a scan mode of an LSI provided with this scan test circuit. FIG. 3 is a diagram showing a time transition of each mode in the scan mode. For example, when the scan enable signal SCANEN becomes high, the shift mode is set, the multiplexer MPX1 selects the scan test signal from the data input terminal DIN1, and inputs this to the flip-flop circuit FF1, and the multiplexer MPX2 is the preceding flip-flop circuit. The scan test signal from FF1 is selected and input to the flip-flop circuit FF2, and the multiplexer MPX3 selects the scan test signal from the preceding flip-flop circuit FF2 and inputs it to the flip-flop circuit FF3. The selector SEL1 selects the scan test signal from the flip-flop circuit FF2 and outputs it to the data output terminal Dout.

  That is, in the shift mode, the flip-flop circuits FF1 to FF3 constitute a shift register, and from the output terminal Q of the flip-flop circuit to the data input terminal D of the flip-flop circuit of the next stage, The scan test signals are sequentially sent, and in a time corresponding to 3 clocks, the scan test signals are held in all the flip-flop circuits FF1 to FF3 forming the scan test circuit. Thus, the scan test signals held in the flip-flop circuits FF1 to FF3 are passed through the logic circuits LG1 to LG4, and predetermined data signals are output from the logic circuits LG1 to LG4, respectively.

  Thereafter, when the scan enable signal SCANEN goes low, the captured mode is set, and the data signals from the logic circuits LG1 to LG4 are taken into the flip-flop circuits FF1 to FF3 through the multiplexers MPX1 to MXP3. At this time, since it is only necessary to simultaneously take in data signals to the flip-flop circuits FF1 to FF3, capture is performed in a time corresponding to one clock.

  When the scan enable signal SCANEN goes high, the shift mode is set again, and the data signals held in the flip-flop circuits FF1 to FF3 are sequentially output from the data output terminal Dout and pass through the logic circuits LG1 to LG4. The expected value that should be obtained in step (1) and the actual data signal are compared, and the pass / fail judgment of each of the logic circuits LG1 to LG4 can be made.

  The scan enable signal SCANEN is normally assigned a dedicated external input terminal and should be input data directly from the external input terminal. However, when the number of LSI external terminals is small, it is difficult to assign as a dedicated external input terminal. There is a case.

In this case, as shown in FIG. 4, an AND circuit AND to which a scan mode signal input from the scan mode terminal SCAN and a scan control signal input from the other data input terminal DIN2 are input is generated. That is, when the scan mode signal is high, the scan control signal input from the data input terminal DIN2 is valid, and the shift mode or the capture mode is set according to the level. Here, the data input terminal DIN2 is also used as a scan control terminal due to restrictions on the number of external terminals of the LSI.
JP-A-5-259761

  However, in the circuit of FIG. 4, in the scan mode, the data input terminal DIN2 functions as a scan control terminal, and the data value is linked to the scan enable signal SCANEN. Therefore, if an attempt is made to configure a scan test circuit similar to the scan test circuit using the data input terminal DIN1 using the data input terminal DIN2, the controllability of the logic circuit LGX connected to the data input terminal DIN2 is controlled. As a result, the failure detection rate is lowered.

  Accordingly, an integrated circuit according to the present invention includes a plurality of logic circuits and a plurality of scan flip-flop circuits arranged between the logic circuits, and each of the scan flip-flop circuits corresponds to the flip-flop circuit and a scan enable signal. And a multiplexer for selectively inputting one of a scan test signal and an output of a logic circuit corresponding to the scan test signal to the flip-flop circuit, and the plurality of scan flip-flops according to the scan enable signal A first data input terminal to which a scan control signal for generating the scan enable signal and a data signal are input, and a first data input terminal; 2 data input terminals and the first mode according to the scan mode signal. A selector for selecting one of a signal input from a data input terminal and a signal input from the second data input terminal, and an output of the selector is input to a logic circuit It is.

  According to the integrated circuit of the present invention, it is possible to improve the controllability of a logic circuit that was poorly controllable in the scan mode and to improve the failure detection rate.

  Next, an integrated circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing a part of an LSI including a scan test circuit. In the LSI, four logic circuits LG1 to LG4 are arranged, and three scan flip-flop circuits SFF1 to SFF3 for scan test are arranged between the logic circuits LG1 to LG4. In an LSI having an actual scan test circuit, the number of scan flip-flop circuits is several hundred or more. The circuit configuration of the scan flip-flop circuits SFF1 to SFF3 is the same as that of the conventional circuit shown in FIGS. Similarly, the shift mode is set when the scan enable signal SCANEN goes high, and the capture mode is set when the scan enable signal SCANEN goes low.

  In the circuit of the present embodiment, the selector SEL2 is inserted in the data path to the logic circuit LGX driven by the data input terminal DIN2 that is also used as a scan control terminal, and is different from the data input terminal DIN2 in the scan mode. The data signal input from the data input terminal DIN3 is selected and input to the logic circuit LGX, thereby improving the controllability of the logic circuit LGX in the scan mode.

  That is, in the scan mode, the scan mode signal input from the scan mode terminal SCAN becomes high, and the scan control signal input from the data input terminal DIN2 becomes valid. When the scan control signal is high, the shift mode is set, and when the scan control signal is low, the capture mode is set. Since the scan control signal input from the data input terminal DIN2 is linked to the scan enable signal SCANEN, when the logic circuit LGX is driven by this signal, the controllability deteriorates. Therefore, in the scan mode, the selector SEL2 selectively outputs the data signal input from the data input terminal DIN3 different from the data input terminal DIN2 to the logic circuit LGX through the selector SEL2 in response to the scan mode signal becoming high. To do. The logic circuit LGX is connected to the scan flip-flop circuit SFFX, and these circuits constitute a part of the scan test circuit.

  On the other hand, in a mode other than the scan mode (in the normal mode), the scan mode signal input from the scan mode terminal SCAN goes low, and the selector SEL2 selectively outputs the data signal input from the data input terminal DIN2 to the logic circuit LGX. .

  Therefore, according to the integrated circuit of the present embodiment, when the scan test circuit is configured by using the data input terminal DIN2, the controllability of the logic circuit LGX that was poorly controllable in the scan mode is improved, and the failure detection rate is improved. Can be improved.

1 is a circuit diagram showing a part of an LSI including a scan test circuit according to an embodiment of the present invention. It is a circuit diagram which shows a part of LSI provided with the scan test circuit based on a prior art example. FIG. 3 is a diagram showing time transition of each mode in the scan mode. It is a circuit diagram which shows a part of LSI provided with the scan test circuit based on a prior art example.

Explanation of symbols

SFF1, SFF2, SFF3 Scan flip-flop circuit MPX1, MPX2, MPX3 Multiplexer FF1, FF2, FF3 Flip-flop circuit SEL1, SEL2 Selector LG1, LG2, LG3, LG4, LGX Logic circuit

Claims (2)

And a plurality of scan flip-flop circuits arranged between the logic circuits, wherein each scan flip-flop circuit includes a flip-flop circuit, a scan test signal according to a scan enable signal, and the scan test signal. And a multiplexer for selectively inputting one of the outputs of the logic circuit corresponding to the input to the flip-flop circuit, and the plurality of scan flip-flop circuits connected in series according to the scan enable signal An integrated circuit on which a test circuit is formed,
A scan control signal for generating the scan enable signal, and a first data input terminal to which a data signal is input;
A second data input terminal;
A selector that selects one of a signal input from the first data input terminal and a signal input from the second data input terminal according to a scan mode signal, and the output of the selector is a logic An integrated circuit which is inputted to a circuit. 2. The AND circuit to which the scan control signal and the scan mode signal input from the first data input terminal are input, and the scan enable signal is output from the AND circuit. An integrated circuit as described.

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