JP2006003194A - Interpolating split circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a circuit configuration by using two-phase output signal not including a carrier component f(ωt) and interpolating and splitting with a closed loop method. <P>SOLUTION: The interpolating split circuit of this invention is constituted to input a first and a second output signals (SX, SY) having different phases from each other in a cosine and a sine multiplier circuits (713, 714) of an interpolating circuit (70), to input each multiplied output from the cosine and the sine multiplier circuits (713, 714) in a subtraction circuit (715) for subtraction process, to output a deviation (ε) and to obtain a positional data (ϕ) by using the deviation (ε). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an interpolating / dividing circuit, and more particularly to a novel circuit for simplifying the rotation configuration by interpolating in a closed-loop manner using a two-phase output signal that does not include a carrier component f (ωt). Regarding improvement.

  As an interpolation division method of this type of optical encoder that has been used conventionally, as shown in Patent Document 1, a two-phase signal including a carrier component is interpolated by an open-loop interpolation division circuit. And obtained position data.

That is, it is configured as shown in FIGS.
The sine wave signal source 10 applies a sinusoidal liquid signal SG (see FIG. 6C) between the nodes P and N. The light emitting circuit 20 includes a light emitting diode 21 connected to the anode or the node P, a diode 23 whose cathode and anode are connected to the anode and cathode of the light emitting diode 21, respectively, and a cathode connected to the cathode of the light emitting diode 21, Is composed of a light emitting diode 22 connected to node N, and a diode 24 whose anode and cathode are connected to the cathode and anode of light emitting diode 22, respectively.

  The light emitting circuit 30 includes a light emitting diode 31 having an anode connected to the node P, a cathode and an anode connected to the anode and the cathode of the light emitting diode 31, and a cathode connected to the cathode of the light emitting diode 31, respectively. Is composed of a light emitting diode 32 connected to node N, and a diode 34 whose anode and cathode are connected to the cathode and anode of light emitting diode 32, respectively. Light of the light emitting diodes 21, 22, 31, and 32 of the light emitting circuits 20 and 30 passes through the light transmitting slits of the index scale 40 and the main scale 50 and is received by the light receiving elements 61 and 62. Lights received by the light receiving elements 61 and 62 from the light emitting diodes 21 and 31 are arranged so that their phases are shifted by 90 ° within the pitch of the optical encoder 1. The light received by the light receiving element 61 from the optical diodes 21 and 22 is arranged so that the phase is shifted by 180 ° within one pitch of the optical encoder. The light received by the light receiving element 62 from the photodiodes 31 and 32 is arranged so that the phase is shifted by 180 ° within the pitch of the optical encoder 1. Further, when the polarity at the node P of the sine wave signal source 10 is positive with respect to the node N, the light emitting diodes 21 and 31 emit light, and when the polarity is negative, the light emitting diodes 22 and 32 emit light.

Therefore, if light that changes in a sine wave shape is emitted from the light emitting circuit 20 to the light receiving element 61 via the scales 40 and 50, light that changes in a cosine wave shape is emitted from the light emitting circuit 30. It becomes. However, if the main scale 50 is inclined from the reference position by an angle θ, the cosine or sine of the angle θ is multiplied by the light received from the light emitting circuit 20 or the light emitting circuit 30, and the output signals SX, SY of the light receiving elements 61, 62 (See FIGS. 6A and 6B). A resolver / digital converter 70 (hereinafter abbreviated as R / D converter 70) resolves / digitally converts SX and SY based on the signal SG and outputs a digital signal 80 indicating a position within one pitch. As an example, the R / D converter 70 for performing resolver / digital conversion as shown in FIG. 9 is composed of an AC bridge 71, a phase detection demodulator 72, an up / down counter 73, an up / down VCO 74, and an integrator 75. Has been. As shown in FIG. 10, the AC bridge 71 includes a buffer 711, a COS multiplication circuit 713, a SIN multiplication circuit 714, and a subtraction circuit 715.

If the sine wave signal source 10 outputs SINωt and the main scale 50 is rotated by the rotation angle θ to the R / D converter 70 having such a configuration, the AC bridge 71 of the R / D converter 70 The buffer circuit 711 receives inputs V1 and V2 expressed by the following equations (2) and (3) (SINωt is amplitude-modulated by SINθ or COSθ).
V1 = V * SINωt * SINθ (2)
V2 = V * SINωt * COSθ (3)
However, V is a constant. The buffer circuit 711 selects one of the outputs in the four quadrants of these signals (this is for simplifying the circuit and is not directly related to the present invention. The digital value of the angle φ detected as the angle θ at this time is input from the up / down counter 73, and the COS multiplier circuit 713 and the SIN multiplier circuit 714 multiply V1 and V2 by COSφ and SINφ, respectively. The following formulas (4) and (5) are obtained.

V11 = V * SINωt * SINθ * COSφ (4)
V22 = V * SINωt * COSθ * SINφ (5)
The subtraction circuit 715 subtracts V22 from V11 to obtain the following expression (6) that represents an AC position error.
V3 = V * SINωt * SIN (θ−φ) (6)
The phase detection demodulator 72 demodulates the output V3 of the AC bridge 71 using SINωt and outputs it as a DC position error. The DC position error is obtained by counting the count value of the up / down counter 73 via the integrator 75 and the up / down VCO 74 until SIN (θ−φ) in the third term on the right side of Equation (6) is 0, that is, θ = φ. Change it. When θ = φ, accurate position data 80 is output from the up / down counter 73. In this case, since the phase detection demodulator 72 uses the sine wave signal output of the sine wave signal source 10 for demodulation, a highly accurate one such as a two-phase oscillator is not required.

  Further, unlike the embodiment of FIG. 5, the same result can be obtained even when the square wave signal source 90 is used instead of the sine wave signal source 10 as in the second embodiment of FIG. Can do. FIG. 8 shows a signal of each part in this case.

Japanese Patent No. 3381936

Since the conventional interpolation / division circuit is configured as described above, the following problems exist.
That is, the sin / cos two-phase output signal to be divided needs to include a carrier component f (ωt) having a constant frequency ω, and an f (ωt) generation circuit and a detection circuit are required, resulting in a complicated circuit configuration. I had to be.

  The interpolating / dividing circuit according to the present invention receives the light from the light source of the light emitting circuit through the main scale by the first and second light receiving elements, and is obtained from the first and second light receiving elements. The second output signal is input to a cos multiplication circuit and a sin multiplication circuit which are provided in a deviation detection unit of the interpolation circuit and to which a digital position feedback value (sinφ, cosφ) is input, and the first output from the cos, sin multiplication circuit. The second multiplication output is input to a subtraction circuit, and a subtraction process is performed to output a deviation (ε), and position data (φ) is obtained using the deviation (ε). (ε) is input to a compensator to obtain a velocity output, and the velocity output is inputted to an integrator to obtain the position data (φ) and the digital position feedback value (sinφ, cosφ). .

Since the interpolation division circuit according to the present invention is configured as described above, the following effects can be obtained.
That is, a circuit for generating a carrier component f (ωt) using a conventional sinusoidal signal source for the light emitting circuit for driving the light emitting source is not necessary, and the circuit configuration can be simplified.
In addition, the detection circuit is not required for the interpolation circuit, and the interpolation circuit itself can be simplified.

  An object of the present invention is to greatly simplify the circuit configuration by adopting a closed loop system that does not use the carrier component f (ωt).

Hereinafter, preferred embodiments of an interpolation / division circuit according to the present invention will be described with reference to the drawings.
Note that the same or equivalent parts as in the conventional example will be described using the same reference numerals.
In FIG. 1, reference numeral 21 denotes a light emission source 21 that is driven to emit light by the light emission circuit 20. The light receiving elements 61 and 62 are configured to receive light.

The first and second output signals SX and SY of the two phases (sin θ and cos θ) obtained from the first and second light receiving elements 61 and 62 are input to the interpolation circuit 70, and the angle from the interpolation circuit 70 is Position data φ as a signal is output.
The first and second output signals SX and SY described above are configured to be 90 degrees out of phase with each other as shown in FIG.

The interpolation circuit 70 is configured as shown in FIG.
That is, the first and second output signals SX and SY are input to the deviation detecting unit 71, and the deviation ε obtained by the deviation detecting unit 71 is input to the compensator 75. The speed output 79 is output from the compensator 75. The velocity output 79 is integrated by an integrator 75A to obtain position data (φ) 80, and the position data (φ) 80 is sent to the deviation detector 71 as digital position feedback values sinφ and cosφ. It is configured to form a closed loop when input.

  The compensator 75 is provided to establish the closed loop, and is constituted by a circuit in which conditions such as a time constant and an amplification degree for establishing the closed loop are set. The circuit configuration is a well-known configuration. Can be used.

Specifically, the deviation detector 71 is configured as shown in FIG. That is, the first and second output signals SX and SY are input to the cos multiplication circuit 713 and the cos multiplication circuit 714 of the deviation detection unit 71, and the first obtained from the cos and sin multiplication circuits 713 and 714 is obtained. The second outputs V11 and V22 are input to the subtraction circuit 715, and the deviation ε is output as sin (θ−φ) from the subtraction circuit 715.
The position data (φ) 80 is input to the cos and sin multiplication circuits 713 and 714 as digital position feedback values sinφ and cosφ.

  The present invention can be applied not only to an encoder by adding a synchronous detection circuit to the deviation detector 71 but also to a resolver.

It is a whole block diagram which shows the interpolation division circuit by this invention. It is a wave form diagram of each output signal of FIG. FIG. 2 is a block diagram showing a specific configuration of the interpolation circuit of FIG. 1. It is a block diagram which shows the specific structure of the deviation detection part of FIG. It is a circuit diagram which shows a 1st conventional structure. FIG. 6 is a waveform diagram of each signal in FIG. 5. It is a circuit diagram which shows a 2nd conventional structure. It is a wave form diagram which shows each signal of FIG. It is a block diagram which shows the specific structure of the R / D converter of FIG. FIG. 10 is a block diagram illustrating a specific configuration of the AC bridge of FIG. 9.

Explanation of symbols

SX first output signal (sin θ)
SY Second output signal (cos θ)
20 light emitting circuit 21 light emitting source 50 main scale 61 first light receiving element 62 second light receiving element ε deviation [sin (θ−φ)]
70 Interpolation Circuit 71 Deviation Detection Unit 75 Compensator 75A Integrator 79 Speed Output 80 Position Data φ
713 cos multiplication circuit 714 sin multiplication circuit 715 subtraction circuit

Claims (2)

  Light (21a) from the light emitting source (21) of the light emitting circuit (20) is received by the first and second light receiving elements (61, 62) through the main scale (50), and the first and second light receiving elements ( 61, 62), the first and second output signals (SY, SX) having different phases are provided in the deviation detector (71) of the interpolation circuit (70), and the digital position feedback values (sinφ, cosφ) are obtained. The first and second multiplication outputs (V11, V22) input from the cos multiplication circuit (713) and the sin multiplication circuit (714) are input to the subtraction circuit (715). An interpolation division circuit configured to be inputted and subtracted to output a deviation (ε) and to obtain position data φ (80) using the deviation (ε).   The deviation (ε) is input to a compensator (75) to obtain a speed output (79), and the speed output (79) is input to an integrator (75A) to input the position data φ (80) and 2. The interpolation division circuit according to claim 1, wherein digital position feedback values (sinφ, cosφ) are obtained.

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