JP2005537670A - Transistor element having anisotropic High-K gate dielectric - Google Patents

Abstract

The field effect transistor 300 has a gate insulating layer including an anisotropic dielectric 305. The direction is selected such that the first dielectric constant parallel to the gate insulating layer is substantially lower than the second dielectric constant perpendicular to the gate insulating layer.

Description

  The present invention relates to the fabrication of advanced integrated circuits having transistor elements that generally have a minimum feature size (shape) of 0.1 μm or less, and more specifically, oxide capacitance equivalent thickness of 2 nm or less. The present invention relates to a high-capacity gate structure including a dielectric.

  In modern integrated circuits, the minimum feature size is steadily shrinking and is expected to be 0.1 μm with the current method and 0.08 μm in the near future. Among the many problems encountered in steadily reducing feature size, there is one important issue that must be solved to allow further scaling of device size. The problem will be described below. At present, the vast majority of integrated circuits are based on silicon. Silicon is available for virtually unlimited use, experience gathered in the last 50 years, and well-known characteristics, and as a result, silicon is the material of choice for next generation circuits. Will continue to be. One of the reasons why silicon is so important in the manufacture of semiconductor devices is the excellent feature of the silicon / silicon dioxide interface that allows reliable electrical isolation of different regions. The silicon / silicon dioxide interface is stable at high temperatures and therefore allows subsequent high temperature processes, such as required annealing cycles, to activate dopants and at the expense of electrical characteristics of the interface Without damaging the crystal damage.

  Most modern integrated circuits have a large number of field effect transistors and, for the reasons noted above, preferably as a gate insulating layer where silicon dioxide separates the polysilicon gate electrode from the silicon channel region. Used. In the device performance of field effect transistors that are steadily improving, the length of this channel region continues to be shortened to increase switching speed and increase the current capacity of the drive. The performance of the transistor is limited by the voltage supplied to the gate electrode in order to change the surface of the channel region to a charge density high enough to give the desired current for a given supply voltage, so that the gate electrode, channel region, And some capacitive coupling provided by the capacitors formed by the silicon dioxide placed between them must be maintained. It has also been found that reducing the channel length requires improved capacitive coupling during transistor operation to avoid so-called short channel behavior. This short channel effect can increase the leakage current and can cause the threshold voltage to depend on the channel length. Because of the relatively low supply voltage, a highly reduced transistor device that also has a low threshold voltage, therefore, similarly couples the capacitive coupling of the gate electrode to the channel region to substantially avoid the channel effect. Since it needs to increase, it suffers from a rapid increase in leakage current. Therefore, the thickness of the silicon dioxide layer is similarly reduced, and it is necessary to provide a desired capacitance between the gate and the channel region. For example, a silicon dioxide thickness in the range of about 2-3 nm is required for a channel length of 0.13 μm, and a silicon dioxide thickness of about 1.2 nm is required for a gate length of 0.08 μm. A gate dielectric made of In general, high speed transistor elements with very short channels are preferably used for high speed applications, while transistor elements with long channels are used for less important applications such as storage transistor elements. . However, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulating layer is unacceptable for performance-driven, so-called performance-driven circuits, 1-2 nm Values for oxide thicknesses in the range can be reached.

  Accordingly, materials that replace silicon dioxide are being considered as materials for forming the gate insulating layer, particularly for ultrathin silicon dioxide gate layers. Possible alternative materials may include materials that exhibit a sufficiently high dielectric constant. The term “sufficiently high” as used herein means that the thickness of the gate insulating layer formed correspondingly becomes higher than that of the silicon dioxide gate layer, while the capacitive coupling obtained by the ultrathin silicon dioxide layer. This means that the dielectric constant is high enough to obtain a value corresponding to. In general, the thickness required to achieve a specific capacitive coupling with silicon dioxide is referred to as capacitance equivalent thickness (CET). Thus, at first glance, simply replacing silicon dioxide with high-k material would be an easy way to obtain an equivalent thickness in the range of 1 nm or less. One approach in this regard is to introduce nitrogen into the silicon dioxide layer, which increases the dielectric constant. However, this technique cannot be expected so much because nitrogen is surely arranged in an extremely thin silicon dioxide layer without invading the channel region under the silicon dioxide layer. Furthermore, by introducing nitrogen into the silicon dioxide, the band gap is reduced and the gate capacitance increase will only be moderate for a given maximum leakage current.

Accordingly, it has been proposed to replace silicon dioxide with materials having a high dielectric constant, such as tantalum oxide (Ta ₂ O ₅ ) with a k value of about 25, strontium titanate with a k value of about 150. Yes. When such high dielectric materials are applied as gate dielectrics, in addition to the multiple problems involved in integrating the processing of these materials into a reliable process sequence, the carrier mobility of the channel region can be Significantly affected by high dielectric materials. Thus, although high capacitive coupling is obtained, the device performance of these transistor elements is reduced due to the reduced carrier mobility, and thus the benefits obtained by using high dielectric materials are at least partially offset. .

  Therefore, in future miniaturization of transistor elements, high capacitive coupling is required, while the carrier mobility that determines the drive current capacity of the transistor device is required not to be significantly adversely affected.

  The present invention generally provides an inventor that the high dielectric constant caused by an electron cloud of weakly bonded dielectric material can be effectively suppressed to an angular range that is substantially perpendicular to the direction of charge carrier flow in the channel region. This is based on the detection of Since the capacitive coupling between the gate electrode and the channel region is determined substantially by the electromagnetic interaction of the weakly coupled electron cloud with charge carriers, an inversion layer is effectively created. On the other hand, the lateral coupling of the electron cloud in the dielectric having charge carriers in the channel region is kept low.

According to one embodiment of the present invention, a field effect transistor has a gate insulating layer formed on an active region and having a high-k dielectric. The dielectric constant of the high-k dielectric that is perpendicular to the gate insulating layer is higher than the dielectric constant that is parallel to the gate insulating layer.

According to a further embodiment, a method of forming a high-k gate insulating layer on a substrate has a first dielectric constant along a first direction and a second dielectric higher than the first dielectric constant along a second direction. An epitaxial dielectric material having a rate is epitaxially grown. At least one process parameter is controlled to adjust a second direction that is substantially perpendicular to the surface of the substrate.

  According to another embodiment of the present invention, a method of forming a high-k dielectric gate insulating layer includes providing a substrate having an active semiconductor region formed thereon. Next, an anisotropic dielectric material is deposited to form a dielectric layer and the substrate is substantially annealed. At least one of substrate deposition and annealing to adjust the crystal orientation so that the first dielectric parallel to the dielectric layer is lower than the second dielectric constant perpendicular to the dielectric layer. At least one process parameter is controlled.

  According to yet another embodiment, a method of forming a gate insulating layer having a capacitance equivalent thickness of less than about 2 nm comprises selecting a crystalline dielectric having different dielectric constants in at least two other directions. The method further determines process parameter settings to form a crystalline dielectric on the substrate such that the direction corresponding to the direction of the higher dielectric constant is substantially perpendicular to the surface of the substrate. Including doing. Finally, the crystalline dielectric is formed according to the parameter settings.

  According to another further embodiment of the invention, the field effect transistor has a gate insulating layer with a dielectric layer having a capacitance equivalent thickness of less than 2 nm. A dielectric constant ratio perpendicular to the dielectric layer to a dielectric constant parallel to the dielectric layer is 1.2 or more.

  The present invention may be understood by the following in conjunction with the accompanying drawings, wherein like reference numerals represent like elements.

  While the invention is amenable to various modifications and alternative forms, specific embodiments described herein have been shown by way of example and are described in detail below. . It should be understood, however, that the particular embodiments illustrated are not intended to limit the invention to the particular forms disclosed, but rather to the scope of the invention as defined by the appended claims. Covers all improvements, equivalents, and variations belonging to.

  Embodiments of the present invention are described below. For simplicity, not all features in a real implementation are described herein. Of course, in the development of such real-world implementations, many specific implementation decisions are made, such as reconciliation with system and business limitations, to achieve specific goals for developers. The They vary depending on each embodiment. Further, such development efforts are naturally complex and time consuming, but nevertheless fall within the normal work for those skilled in the art having the benefit of this disclosure.

  The present invention will be described with reference to the accompanying drawings. The various structures and implant regions of the semiconductor device are depicted in each drawing with very precise, sharp shapes and profiles, but those skilled in the art will be able to see how accurately these regions and structures are actually shown in the drawings. You will recognize that it is not. In addition, the various features depicted in the drawings and the relative size of the implant regions are exaggerated or reduced compared to the features and region sizes of the devices being manufactured. However, the attached drawings are attached for the purpose of illustrating embodiments of the present invention. Terms and phrases used herein are understood to have a meaning consistent with words and phrases understood by those skilled in the relevant art. The consistent use of terms or phrases in this specification means definitions that are different from any particular definition of these terms or phrases, that is, from the ordinary and conventional meanings understood by those of ordinary skill in the art. Not what you want. When a term or phrase is used in a range that has a specific meaning, that is, when used in a different meaning than that understood by those skilled in the art, the specification directly and clearly identifies such words and phrases. Define.

  Hard work for materials that can replace silicon dioxide and / or silicon oxynitride to achieve the capacitance equivalent thickness of 2 nm or more required to make the channel length less than 0.1 μm Efforts have been made. So far, candidates such as zirconium oxide, hafnium oxide, and titanium oxide have been confirmed. However, despite the suggestion that the introduction of these high-k materials can achieve a capacitance equivalent thickness of less than 2 nm without increasing the leakage current, the conventional approach does not provide carrier mobility in the channel region. Does not seem to propose a solution to the fact that

  The present invention is therefore based on the concept of taking into account the direction of the dielectric constant in addition to the increasing absolute dielectric constant, so that when moving from the source region to the drain region, an electron with a dielectric material is present. Can significantly affect the interaction of charge carriers such as.

With reference to FIGS. 1a to 1c, the concept of the present invention will be explained in more detail below. In FIG. 1a, field effect transistor 100 has a substrate 101 having an active region 106, which is typically a silicon-based semiconductor material. For convenience, transistor 100 is shown as an N-channel type. The present invention is similarly applied to a P-channel transistor. Further, the source region 102 and the drain region 103 are formed in the active region 106. For example, the gate electrode 104 made of polysilicon or another conductive material is formed on the active region 106 and is separated therefrom by a gate insulating layer 105 made of an anisotropic material. This anisotropic material is a crystalline metal-containing oxide or silicate, a ferroelectric material, or an optically anisotropic material. The dielectric of the anisotropic gate insulating layer 105 has a first dielectric constant k _parallel in a direction substantially _parallel to the gate insulating layer 105 and a first dielectric constant in a direction substantially perpendicular to the gate insulating layer 105. second dielectric constant k and a _{an orthogonal,} as indicated by reference numeral 107, k _parallel is lower than k _{an orthogonal.}

In operation, a voltage is applied to the gate electrode 104 and the active region 106. For convenience, with respect to the N-channel transistor 100 shown in FIG. 1a, the source region 102 and the active region are formed such that a positive voltage causes a conductive channel 108 to be formed at the interface between the gate insulating layer 105 and the active region 106. Region 106 is coupled to a common reference potential. Due to the high dielectric constant k _orthogonal , the gate insulation layer 105 provides high capacitive coupling of the gate electrode 104 to the channel 108, while compared to a capacitance equivalent thickness of 2 nm or less, the gate insulation layer 105. However, since the thickness is physically increased, the leakage current from the channel 108 to the gate electrode 105 is maintained at an allowable level. Since the dielectric constant k _parallel is substantially lower than the dielectric constant k _orthogonal, which is perpendicular to the flow direction of the charge carriers, the electromagnetic coupling to the gate dielectric is the flow direction, as indicated by the arrow 120 in FIG. Is significantly lower. Further details on this will be explained below with reference to FIGS. 1b and 1c.

FIG. 1 b shows a simplified model of a portion of the gate electrode 105. In this model, the gate insulating layer 105 having an anisotropic dielectric is represented by a two-dimensional grid, and the lattice sites are represented by dots 111. These dots are connected to the nearest neighbor by a vertical spring 110 and by a horizontal bar 112. To avoid introducing two different types of springs with different strengths, the dielectric constant k _parallel is represented by an inelastic bar 112 for convenience. However, it can be seen that the dielectric constant k _parallel can be represented by a “strong” spring indicating low sensitivity to external electromagnetic fields. The spring 110 and bar 112 represent the corresponding abilities of interaction with the electron cloud and charged particles. When a positive voltage is applied to the gate electrode 104, the corresponding spring 110 is deformed. That is, the electron cloud is brought into an unbalanced state, and electrons are attracted to the channel region 108 and combined. When a voltage is established between the source region and the drain region, electrons move due to the influence of this electric field, and the electrons remain coupled to the vertical gate insulating layer 105 and move closer to the spring 110a. To do. Since the bar 112 cannot be deformed at least in this simplified model, substantial coupling does not occur in the horizontal direction and therefore the horizontal movement of the electrons is not substantially affected.

  FIG. 1c illustrates this situation for a substantially isotropic gate insulating layer 105a. In this case, the electrons can deform the horizontal spring 110, and the vertical spring 110 can be deformed as well, so that some coupling exists in both directions, which is the flow direction of the electrons. The result is a reduced mobility.

  Thus, by providing a dielectric material for the gate insulating layer 105 that has significant anisotropy in the parallel and vertical directions, the degradation of the charge carrier mobility in the channel region 108 is substantially reduced, and as a result, the transistor Performance is improved compared to conventional devices with isotropic dielectrics. Even if a dielectric material having the same dielectric constant is used in the conventional device, or the same material as that used in the transistor 100 is used without being appropriately adjusted in the direction of the corresponding dielectric material. Even so, the carrier mobility is smaller than that of the transistor 100.

FIG. 2 shows an example of the anisotropic conductive material. In FIG. 2, the basic structure of titanium dioxide (TiO ₂ ) is shown in the form of a so-called tetragonal system / rutile. As shown in FIG. 2, in this crystalline form, titanium dioxide has tetragonal systems with lattice constants a and c of 0.4594 nm and 0.2958 nm, respectively. Further, the dielectric constant along axis c is lower than the dielectric constant along axis a, and the ratio of the dielectric constant of axis a to the dielectric constant of axis c is about 2 at room temperature. The value of the dielectric constant k is approximately 60, and this value may depend on the specific alignment and growth parameters of the gate insulating layer 105. Typically, titanium dioxide can be deposited by chemical vapor deposition using a precursor gas such as titanium tetrakis isopropoxide (TTIP) and titanium nitride at a substrate temperature of 660 ° C. By maintaining the above, the titanium dioxide is deposited in a substantially tetragonal shape, or in another form or in addition, the substrate is annealed at a temperature in the range of about 700-900 ° C. Can be transformed into a crystal layer having a substantially tetragonal shape.

  A typical process flow for the above-described deposition scheme to form a field effect transistor 100 including a crystalline tetragonal shaped titanium dioxide layer or the like has the following steps. First, a shallow trench isolation (not shown) can be formed to form the active region 106. After an implantation sequence to form a dopant profile perpendicular to the active region 106, a gate insulating layer 105 is deposited on the substrate 101. In the above example, the gate insulating layer 105 comprises titanium dioxide, and it is advantageous to deposit a thin barrier layer to ensure the thermal stability of the titanium dioxide. For example, one or two atomic layers made of silicon dioxide or silicon nitride, zirconium silicate, or the like can be deposited on the substrate 101. Subsequently, titanium dioxide is deposited using the chemical vapor deposition method described above, etc., and the process parameters are adjusted to obtain crystalline growth with a substantially vertical axis c on the surface of the substrate 101. The The setting of the corresponding parameter is determined by the crystal direction of the substrate 101, the type of the barrier layer, the deposition state, and in some cases the annealing state. Therefore, the crystal orientation based on the growth and / or annealing of titanium dioxide is established by theory such as experiments and / or simulation calculation methods.

In other forms, the titanium dioxide can be deposited at a substantially appropriate temperature and crystallized in subsequent annealing cycles. After the deposition of titanium dioxide, depending on how the process proceeds, an annealing cycle can be performed due to the required crystallinity. In the deposition of titanium dioxide, the thickness is controlled to obtain the required capacitance equivalent thickness. As already pointed out, the effective dielectric constants k _orthogonal and k _parallel are determined by the deposition specificity and the barrier type material used, with typical values in the range of 20-70. Subsequently, a polysilicon layer is deposited and imitated by known photolithography and etch techniques to form the gate electrode 104. Thereafter, the field effect transistor 100 can be completed by well-known implantation, spacer, and annealing techniques.

  FIG. 3 shows a schematic cross-sectional view of a further example of a field effect transistor 300. The field effect transistor 300 has an anisotropic high-k material layer 305 and a barrier layer 315 in the form of an ultrathin silicon dioxide layer formed on a silicon substrate 301. The transistor 300 further includes a gate electrode 304 and a sidewall spacer 309 formed on the anisotropic dielectric layer 305. Source and drain regions are formed in the substrate 301. The combined thickness of layer 305 and layer 315 is selected to correspond to a capacitance equivalent thickness in the range of about 1-1.5 nm. Since barrier 315 has already "consumed" a portion of the capacitance equivalent thickness, typically about 0.5 nm for one or two atomic layers, the effective thickness of anisotropic dielectric layer 305 is , In the range of about 3-5 nm, resulting in a leakage current substantially corresponding to a silicon dioxide layer of 2 nm or more. Thus, the transistor element 300 can scale gate lengths significantly greater than 0.1 μm while maintaining leakage current at the current state-of-the-art device level. Due to the anisotropic nature of dielectric layer 305, carrier mobility can be comparable to silicon dioxide based devices. By providing a barrier layer 315 of silicon dioxide, the transistor element 300 is reliable. This is because the silicon / silicon dioxide interface and their manufacturing process are highly compatible with currently established process technologies.

As a result, the present invention provides an advanced transistor element having a gate length of less than 0.1 μm by giving the gate insulating layer different dielectric constants in parallel or vertical directions. Preferably, the ratio of k _{orthogonal to} k _parallel is 1.2 or more, in order to achieve a significant effect on improving the charge carrier mobility with respect to increased capacitance and reduced leakage. Preferably, the anisotropy of the dielectric gate material is selected according to the desired target CET (capacitance equivalent thickness) and process requirements. For example, the need for a barrier layer is to determine the minimum k value to achieve the targeted CET, and the anisotropy needs to meet operational requirements. For example, high performance applications require high anisotropy to optimize carrier mobility. On the other hand, the leakage current has an extremely high value of about 100, but is within reasonable limits due to a moderate dielectric constant such as titanium dioxide as compared to a material that does not have a clear anisotropy.

  Furthermore, the crystallinity of the high-k dielectric can be adjusted to obtain the required direction. Preferably, the deposition kinetics, the type of barrier layer, and optionally the crystal structure of the substrate are taken into account to adjust the physical thickness according to the target capacitance equivalent thickness, for example by imitation and / or experimentation. sell. In another form, the orientation and / or crystal structure can be tailored by providing one or more sublayers of one or more different materials. For example, to guide in the required direction, it is necessary to provide a suitable crystal structure for depositing high-k materials. Thus, one or more “transition” layers are then provided, and finally a deposition base is provided to obtain the desired “bulk” material with high-k values.

  It will be apparent to those skilled in the art who are able to benefit from the present invention that various modifications and implementations are possible within the equivalent scope of the present invention, so that the individual embodiments described above are exemplary. It's just a thing. For example, the execution order of each step in the above-described method can be changed. Further, the details of the configuration or the design described above are not intended to limit the present invention at all, and are limited only to the description of the claims. Thus, it will be apparent that the particular embodiments described above can be varied and modified and such variations are within the spirit and scope of the invention. Accordingly, the protection of the present invention is limited only by the scope of the claims.

1 is a schematic cross-sectional view of a field effect transistor including an anisotropic gate dielectric. It is explanatory drawing of the schematic simple model of an anisotropic dielectric material. It is explanatory drawing of the simple model of the conventional substantial anisotropic dielectric material. It is explanatory drawing of the basic structure of a titanium dioxide crystal. FIG. 6 is a schematic illustration of a field effect transistor having a gate dielectric according to a further embodiment of the present invention.

Claims (18)

  A field effect transistor 300 formed on an active region and having a gate insulating layer having a high-k dielectric 305, wherein the dielectric constant of the high-k dielectric perpendicular to the gate insulating layer is the gate insulation A field effect transistor 300 having a higher dielectric constant parallel to the layers.   The field effect transistor according to claim 1, wherein a ratio of the dielectric constant perpendicular to the gate insulating layer to the dielectric constant parallel to the gate insulating layer is higher than 1.2.   The field effect transistor 300 of claim 1, wherein a capacitance equivalent thickness of the gate insulating layer is less than 2 nm.   The field effect transistor of claim 1, wherein the gate insulating layer comprises at least one metal oxide, metal silicate, and a ferroelectric material.   The field effect transistor of claim 4, wherein the gate insulating layer comprises titanium dioxide.   The field effect transistor according to claim 6, wherein the titanium dioxide has a tetragonal shape.   The field effect transistor according to claim 1, wherein the gate insulating layer includes a barrier layer 315 provided between the active region and the high-k dielectric 305.   The field effect transistor of claim 7, wherein the barrier layer (315) comprises at least one of silicon dioxide, silicon nitride, or zirconium silicate. A method of forming a high-k gate insulating layer on a substrate 301, comprising:
Epitaxially growing an anisotropic dielectric material 305 having a first dielectric constant along a first direction and a second dielectric constant higher than the first dielectric constant along a second direction;
Controlling at least one process parameter to adjust the second direction to be substantially perpendicular to the surface of the substrate.   The method of claim 9, wherein the substrate 301 is annealed to control crystallinity of the dielectric material.   The method of claim 9, wherein the metal-containing dielectric comprises titanium oxide.   The method of claim 11, wherein the anisotropic epitaxial growth with a dielectric is performed at a temperature in the range of about 700-900 degrees Celsius. A method of forming a high-k dielectric gate insulating layer, the method comprising:
Preparing a substrate 301 on which an active semiconductor region is formed;
Depositing an anisotropic dielectric material to form a dielectric layer;
Annealing the substrate and controlling at least one process parameter of at least one of deposition or annealing of the substrate 301 such that a first dielectric constant parallel to the dielectric layer is perpendicular to the dielectric layer Adjusting the crystal orientation to be lower than the second dielectric constant.   The method of claim 13, wherein the dielectric comprises titanium oxide.   The method of claim 13, wherein the deposition of the anisotropic dielectric is performed at room temperature in the range of about 700-900 ° C.   The method of claim 13, wherein the annealing is performed at a temperature in the range of 600-800 ° C. A method of forming a gate insulating layer having a capacitance equivalent thickness of less than about 2 nm, the method comprising:
Selecting a crystalline dielectric having different dielectric constants in at least two different directions;
A method for determining process parameter settings for forming the crystalline dielectric on the substrate 301 such that a direction corresponding to a high dielectric constant is substantially perpendicular to a surface of the substrate 301.   The method of claim 17, wherein the setting of process parameters includes at least one of deposition parameters or annealing parameters.

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