CN102201435B - Semiconductor structure and manufacture method thereof - Google Patents
Semiconductor structure and manufacture method thereof Download PDFInfo
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- CN102201435B CN102201435B CN201110125778.1A CN201110125778A CN102201435B CN 102201435 B CN102201435 B CN 102201435B CN 201110125778 A CN201110125778 A CN 201110125778A CN 102201435 B CN102201435 B CN 102201435B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 82
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 238000002347 injection Methods 0.000 claims abstract description 95
- 239000007924 injection Substances 0.000 claims abstract description 95
- 229910052751 metal Inorganic materials 0.000 claims abstract description 60
- 239000002184 metal Substances 0.000 claims abstract description 60
- 229910021645 metal ion Inorganic materials 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 29
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 28
- 239000001301 oxygen Substances 0.000 claims abstract description 28
- 230000001105 regulatory effect Effects 0.000 claims abstract description 3
- 239000000463 material Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 8
- 229910052688 Gadolinium Inorganic materials 0.000 claims description 7
- 229910052727 yttrium Inorganic materials 0.000 claims description 7
- 238000002425 crystallisation Methods 0.000 abstract description 5
- 230000008025 crystallization Effects 0.000 abstract description 5
- 230000009467 reduction Effects 0.000 abstract description 2
- 229940090044 injection Drugs 0.000 description 86
- 150000002500 ions Chemical class 0.000 description 21
- 125000004429 atom Chemical group 0.000 description 20
- 238000010586 diagram Methods 0.000 description 14
- 230000008859 change Effects 0.000 description 9
- 229910052691 Erbium Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 125000004430 oxygen atom Chemical group O* 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052747 lanthanoid Inorganic materials 0.000 description 2
- 150000002602 lanthanoids Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- -1 such as Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The present invention proposes a kind of semiconductor structure and manufacture method thereof, wherein, semiconductor structure includes: substrate, the gate dielectric layer of described substrate, between described substrate and described gate dielectric layer formed boundary layer, be positioned at the metal gate electrode layer on described gate dielectric layer；Injecting ion-select electrode layer with at least one of which, for regulating the work function of described semiconductor structure, and the binding ability of the metallic atom in described injection ion-select electrode layer and oxygen is higher than the binding ability of described gate dielectric layer Atom with oxygen.The present invention is by injecting metal ion in the semiconductor structure, it is achieved the adjustment of semiconductor structure work function, boundary layer thinning, the raising of gate medium crystallization temperature, the reduction of equivalent oxide thickness, the lifting of semiconductor structure performance.
Description
Technical field
The present invention relates to ic manufacturing technology field, particularly to a kind of semiconductor structure and manufacture method thereof.
Background technology
In existing CMOS technology, in order to improve the performance of device, generally use high k (dielectric constant) gate dielectric material and metal gate material.Research shows, replacement silica material has more higher dielectric constant than silicon oxide as the high-k gate dielectric material of cmos device gate medium, the size of gate capacitance can be improved in the case of not reducing physical thickness, thus in the case of not increasing electric leakage, reduce equivalent oxide thickness (EquivalentOxidethickness, EOT), device performance is improved.
But, high-k gate dielectric material and metal gate material in use exist some problems to be needed to improve, and such as, interfacial state is higher, and EOT needs to reduce further, and adjusts the problems such as work function.But, its dielectric constant ratio of the boundary layer formed in annealing process is relatively low, and thickness is typically at about 1nm, hinders the further reduction of EOT, hampers the further raising of device performance.Work function aspect, uses TiN/HfO2The demand (work function～5.2eV) of PMOS can be met, but a kind of suitably Technology is not the most proposed in the case of being added without cover layer, realize the adjustment of semiconductor structure work function so that it is meet the demand (work function～4.2eV) of NMOS.It addition, the thermal stability problems of high K medium is also the most concerned key technology.Hafnio gate medium has become as the dielectric material more generally acknowledged, but hafnium oxide is about 500 degree the most easily crystallizations, causes element leakage to increase, hydraulic performance decline.
Summary of the invention
The purpose of the present invention is intended at least solve one of above-mentioned technical problem.
To this end, one aspect of the present invention proposes a kind of semiconductor structure, including: substrate；It is positioned at the gate dielectric layer of described substrate, wherein, between described gate dielectric layer and described substrate, there is boundary layer；It is positioned at the metal gate electrode layer on described gate dielectric layer；And at least one of which injection ion-select electrode layer, for regulating the work function of described semiconductor structure, and in described injection ion-select electrode layer, the binding ability of metallic atom and oxygen is higher than the binding ability of described gate dielectric layer and described boundary layer Atom and oxygen.
In one embodiment of the invention, wherein, described injection ion-select electrode layer is formed at the bottom of described metal gate electrode layer；Or, described injection ion-select electrode layer is formed at the top of described gate dielectric layer；Or, a part for described injection ion-select electrode layer is positioned in described gate dielectric layer, and another part of described injection ion-select electrode layer is positioned in described metal gate electrode layer.
In one embodiment of the invention, the metal ion in described injection ion-select electrode layer is one or more in Er, Y, Gd.
In one embodiment of the invention, its work function of metal ion for NMOS semiconductor structure is less than the work function of metal gate electrode；Its work function of metal ion for PMOS semiconductor structure is more than the work function of metal gate electrode.
In one embodiment of the invention, wherein, the described injection ion-select electrode layer injection degree of depth on semiconductor structure horizontal direction is identical；Or, the injection depth ratio at the described injection ion-select electrode layer close source and drain two ends on the semiconductor structure horizontal direction injection degree of depth in middle part is deep；Or, the injection depth ratio at the described injection ion-select electrode layer close source and drain two ends on the semiconductor structure horizontal direction injection depth as shallow in middle part；Or, described injection ion-select electrode layer is deep in the semiconductor structure injection depth ratio near the source position injection degree of depth at other positions；Or, described injection ion-select electrode layer is in the semiconductor structure injection depth ratio near the drain terminal position injection depth as shallow at other positions.
Another aspect of the present invention also proposed the manufacture method of a kind of semiconductor structure, comprises the following steps: provides substrate；Deposit high-g value is to form gate dielectric layer over the substrate, wherein, has boundary layer between described gate dielectric layer and described substrate；Described gate dielectric layer deposits metal gate material to form metal gate electrode layer；In described metal gate electrode layer, inject metal ion be higher than the binding ability of described gate dielectric layer and described boundary layer Atom and oxygen to form the binding ability injecting ion-select electrode layer, the metallic atom in wherein said injection ion-select electrode layer and oxygen；With anneal.
In one embodiment of the invention, wherein, described injection ion-select electrode layer is positioned at the bottom of described metal gate electrode layer；Or, described injection ion-select electrode layer is positioned at the top of described gate dielectric layer；Or, a part for described injection ion-select electrode layer is positioned in described gate dielectric layer, and another part of described injection ion-select electrode layer is positioned in described metal gate electrode layer.
In one embodiment of the invention, one or more during the metal ion of described injection is Er, Y, Gd.
In one embodiment of the invention, its work function of metal ion for NMOS semiconductor structure is less than the work function of metal gate electrode；Its work function of metal ion for PMOS semiconductor structure is more than the work function of metal gate electrode.In one embodiment of the invention, wherein, the described injection ion-select electrode layer injection degree of depth on semiconductor structure horizontal direction is identical；Or, the injection depth ratio at the described injection ion-select electrode layer close source and drain two ends on the semiconductor structure horizontal direction injection degree of depth in middle part is deep；Or, the injection depth ratio at the described injection ion-select electrode layer close source and drain two ends on the semiconductor structure horizontal direction injection depth as shallow in middle part；Or, described injection ion-select electrode layer is deep in the semiconductor structure injection depth ratio near the source position injection degree of depth at other positions；Or, described injection ion-select electrode layer is in the semiconductor structure injection depth ratio near the drain terminal position injection depth as shallow at other positions.
Another aspect of the present invention also proposed the manufacture method of a kind of semiconductor structure, comprises the following steps: provides substrate；Deposit high-g value is to form gate dielectric layer over the substrate, wherein, has boundary layer between described gate dielectric layer and described substrate；In described gate dielectric layer, inject metal ion be higher than the binding ability of described gate dielectric layer and described boundary layer Atom and oxygen to form the binding ability injecting ion-select electrode layer, the metallic atom in wherein said injection ion-select electrode layer and oxygen；Described gate dielectric layer deposits metal gate material to form metal gate electrode layer；With anneal.
In one embodiment of the invention, described injection ion-select electrode layer is positioned at the top of described gate dielectric layer.
In one embodiment of the invention, one or more during the metal ion of described injection is Er, Y, Gd.
In one embodiment of the invention, its work function of metal ion for NMOS semiconductor structure is less than the work function of metal gate electrode；Its work function of metal ion for PMOS semiconductor structure is more than the work function of metal gate electrode.
In one embodiment of the invention, wherein, the described injection ion-select electrode layer injection degree of depth on semiconductor structure horizontal direction is identical；Or, the injection depth ratio at the described injection ion-select electrode layer close source and drain two ends on the semiconductor structure horizontal direction injection degree of depth in middle part is deep；Or, the injection depth ratio at the described injection ion-select electrode layer close source and drain two ends on the semiconductor structure horizontal direction injection depth as shallow in middle part；Or, described injection ion-select electrode layer is deep in the semiconductor structure injection depth ratio near the source position injection degree of depth at other positions；Or, described injection ion-select electrode layer is in the semiconductor structure injection depth ratio near the drain terminal position injection depth as shallow at other positions.
Another aspect of the invention also proposes the manufacture method of a kind of semiconductor structure, comprises the following steps: provide substrate；Deposit high-g value is to form gate dielectric layer over the substrate；In described gate dielectric layer, inject metal ion be higher than the binding ability of described gate dielectric layer and described boundary layer Atom and oxygen to form the binding ability injecting ion-select electrode layer, the metallic atom in wherein said injection ion-select electrode layer and oxygen；Described gate dielectric layer deposits metal gate material to form metal gate electrode layer；With anneal.
The present invention is by injecting metal ion in semiconductor structure, it is achieved the regulation of semiconductor structure work function, simultaneously can thinning boundary layer, improve the crystallization temperature of gate medium, reduce EOT, promote the performance of semiconductor structure.
Aspect and advantage that the present invention adds will part be given in the following description, and part will become apparent from the description below, or is recognized by the practice of the present invention.
Accompanying drawing explanation
The present invention above-mentioned and/or that add aspect and advantage will be apparent from easy to understand, wherein from the following description of the accompanying drawings of embodiments:
Fig. 1 is the schematic diagram of the semiconductor structure of first embodiment of the invention；
Fig. 2 is the schematic diagram of the semiconductor structure of second embodiment of the invention；
Fig. 3 is the schematic diagram of the semiconductor structure of third embodiment of the invention；
Fig. 4 to Fig. 7 is respectively the schematic diagram that the metal ion injection degree of depth on the horizontal direction of semiconductor structure is different；
Fig. 8 is the flow chart of the manufacture method of the semiconductor structure of one embodiment of the invention；
Fig. 9 is the ion distribution figure after injecting Er ion；
Figure 10 is work function and the graph of a relation injected between ion；
Figure 11 is the schematic diagram of remotely oxygen uptake after annealing；
Figure 12 a is the schematic diagram after the semiconductor structure annealing of injection ion；
Figure 12 b is the schematic diagram after the semiconductor structure annealing of unimplanted ion；And
Figure 13 is the flow chart of the manufacture method of the semiconductor structure of another embodiment of the present invention.
Detailed description of the invention
Embodiments of the invention are described below in detail, and the example of described embodiment is shown in the drawings, and the most same or similar label represents same or similar element or has the element of same or like function.The embodiment described below with reference to accompanying drawing is exemplary, is only used for explaining the present invention, and is not construed as limiting the claims.
In describing the invention, it will be appreciated that, term " longitudinally ", " laterally ", " on ", D score, "front", "rear", "left", "right", " vertically ", " level ", " top ", " end " " interior ", the orientation of the instruction such as " outward " or position relationship be based on orientation shown in the drawings or position relationship, it is for only for ease of the description present invention and simplifies description, rather than instruction or hint indication device or element must have specific orientation, with specific azimuth configuration and operation, be therefore not considered as limiting the invention.
Embodiment 1
It is illustrated in figure 1 the schematic diagram of the semiconductor structure of first embodiment of the invention, this semiconductor structure includes from substrate 1 the most successively: with boundary layer 10, gate dielectric layer 20, the metal gate electrode layer 30 of substrate contact and be formed entirely in metal gate electrode layer 30 and be positioned at the injection ion-select electrode layer 41 bottom metal gate electrode layer 30, to regulate the work function of described semiconductor structure.Wherein, in one embodiment of the invention, the realization of gate dielectric layer or Metal gate layer can be the conventional techniques such as ald (ALD), physical vapour deposition (PVD) (PVD), chemical gaseous phase deposition (CVD), for the sake of simple, repeats no more." bottom " of so-called metal gate electrode layer 30 is the metal gate electrode layer 30 side near gate dielectric layer 20.It is entirely located in metal gate electrode layer 30 it is to say, inject ion-select electrode layer 41 and connects with gate dielectric layer 20.Inject the binding ability of metallic atom and oxygen in ion-select electrode layer 41 and be higher than the binding ability of gate dielectric layer 20 and boundary layer 10 Atom and oxygen, such as, the metal ions such as Er, Y, Gd can be injected.So, it is higher than the binding ability of gate dielectric layer Atom and oxygen owing to injecting the binding ability of metallic atom and oxygen in ion-select electrode layer 41, and the binding ability of gate dielectric layer Atom and oxygen is higher than the binding ability of boundary layer Atom with oxygen, therefore, oxygen atom migrates to gate dielectric layer from boundary layer, and the oxygen atom in gate dielectric layer migrates to inject ion-select electrode layer, the oxide of formation injection ion, thus thinning boundary layer.
In the present embodiment, the method that low energy ion arc can be used to inject is injected metal ion in metal gate electrode layer 30 and is formed injection ion-select electrode layer 41.
Should be understood that and can inject one or more metal ions in metal gate electrode layer 30, thus one or more layers injection ion-select electrode layer 41 can be formed.
In addition, owing to NMOS and PMOS is for the difference of work function demand, the work function injecting the metal ion in the semiconductor structure of NMOS should be different from the work function of the metal ion of the semiconductor structure injecting PMOS, especially, in the present embodiment, the metal ion injected in the semiconductor structure of NMOS is the relatively low metal of work function, such as one or more in lanthanide series metal, thus meets the work function demand of NMOS.
Embodiment 2
It is illustrated in figure 2 the schematic diagram of the semiconductor structure of second embodiment of the invention, includes the most successively from substrate 1: boundary layer 10, gate dielectric layer 20, metal gate electrode layer 30 and injection ion-select electrode layer 42.Injecting arranging of ion-select electrode layer 42 in the present embodiment similar to Example 1, for the sake of simple, repeat no more, except for the difference that, the ion-select electrode layer 42 that injects in the present embodiment is formed at the top of gate dielectric layer 20." top " of so-called gate dielectric layer 20 is the gate dielectric layer 20 side near metal gate electrode layer 30.It is entirely located in gate dielectric layer 20 it is to say, inject ion-select electrode layer 42 and connects with metal gate electrode layer 30.
Embodiment 3
It is illustrated in figure 3 the schematic diagram of the semiconductor structure of third embodiment of the invention, includes the most successively from substrate 1: boundary layer 10, gate dielectric layer 20, metal gate electrode layer 30 and injection ion-select electrode layer 43.The present embodiment injects arranging of ion-select electrode layer 43 similar to Example 1, for the sake of simple, repeat no more, except for the difference that, the part injecting ion-select electrode layer 43 in the present embodiment is positioned in metal gate electrode layer 30, and another part is positioned in gate dielectric layer 20.
It should be noted that the metal ion injection degree of depth on the horizontal direction of semiconductor structure can be identical, it is also possible to different.Inject the degree of depth by changing, thus it is possible to vary equivalent oxide thickness, and then the semiconductor structure control ability to raceway groove can be changed.
As Fig. 4 to Fig. 7 is respectively the schematic diagram that the metal ion injection degree of depth on the horizontal direction of semiconductor structure is different, it should be noted that among Fig. 4-Fig. 7, inject that ion-select electrode layer can be located in boundary layer 10, gate dielectric layer 20, metal gate electrode layer 30 one or more among.
As shown in Figure 4, the injection depth ratio at the injection ion-select electrode layer 44 two ends on the horizontal direction A (arrow in such as Fig. 4) of the semiconductor structure injection degree of depth in middle part is deep, so, the two ends of boundary layer 10 are thinning more, boundary layer 10 thick middle formed, both sides are thin, and then realize the change of horizontal gate capacitance.Especially, grid structure is thicker near the interfacial layer thickness at source and drain two ends in this embodiment, then weaken the control ability of raceway groove, weakens further the grid impact on source and drain, thus alleviates drain-induced barrier and reduce (DIBL) effect, reduces electric leakage.
As shown in Figure 5, the injection depth ratio of the injection ion-select electrode layer 45 middle part on the horizontal direction A (arrow in such as Fig. 5) of the semiconductor structure injection degree of depth at two ends is deep, so, the two ends of boundary layer 10 are thinning less, boundary layer 10 intermediate thin formed, both sides are thick, and then realize the change of horizontal gate capacitance.
The ion implanting depth ratio of the middle part on semiconductor structure horizontal direction near source, leakage two ends the ion implanting degree of depth deep, thus gate junction structure near source, leakage two ends interfacial layer thickness relatively thin, then stronger to the control ability of raceway groove, when adding gate voltage, grid structure near source, leakage two ends be more easily implemented carrier inject, can be implemented as multidigit storage a kind of method.
As shown in Figure 6, injecting the ion-select electrode layer 46 injection degree of depth at other positions of injection depth ratio at the position near source deep, so, the position of the close source of boundary layer 10 is thinning more, and then realizes the change of horizontal gate capacitance.In this embodiment, grid structure is relatively thin near the interfacial layer thickness of source, therefore relatively strong to the control ability of raceway groove, for tunneling transistor, is conducive to promoting the tunnelling probability of carrier in source raceway groove, and then improves driving electric current.
As it is shown in fig. 7, inject the ion-select electrode layer 47 injection depth as shallow at other positions of injection depth ratio at the position near drain terminal, so, the position of the close drain terminal of boundary layer 10 is thinning more, and then realizes the change of horizontal gate capacitance.In this embodiment, grid structure is thicker near the interfacial layer thickness of drain terminal, then weaken the control ability of raceway groove, alleviates drain-induced barrier and reduces (DIBL) effect, reduces electric leakage.
It should be understood that; embodiment shown in above-mentioned Fig. 4 to Fig. 7 is only schematic example; being not limited to the present invention, those skilled in the art can change the injection degree of depth of metal ion according to actual needs, and these change and change should be included in protection scope of the present invention.
For realizing above-described embodiment, the present invention also proposes the manufacture method of a kind of semiconductor structure.It is illustrated in figure 8 the flow chart of the manufacture method of the semiconductor structure of one embodiment of the invention, comprises the following steps:
Step S801, it is provided that substrate.
Step S802, on substrate, deposit high-g value is to form gate dielectric layer, wherein, has boundary layer between gate dielectric layer and substrate.
Step S803, deposits metal gate material to form metal gate electrode layer on gate dielectric layer.
Above-mentioned steps S801, to step S803, can use prior art to realize, and for the sake of simple, is not described in detail.
Step S804, injects metal ion in metal gate electrode layer and injects ion-select electrode layer to be formed.
Specifically, by the method that low energy ion arc injects, metal ion implantation metal gate electrode layer can be injected ion-select electrode layer to be formed.
Inject the metallic atom of ion-select electrode layer with the binding ability of oxygen higher than the binding ability of gate dielectric layer Atom with oxygen, such as, Er, Y, Gd etc. can be injected.Additionally, a metal ion species or many kinds of metal ions can be injected, thus form one or more layers injection ion-select electrode layer in the semiconductor structure.
Furthermore, it is to be understood that the position of the metal ion injected is different, the size of work function and equivalent oxide thickness (EOT) also can change.Such as, in one embodiment, inject ion-select electrode layer and be positioned at the bottom of metal gate electrode layer；In another embodiment, inject ion-select electrode layer and be positioned at the top of gate dielectric layer；In yet another embodiment, the part injecting ion-select electrode layer is positioned in metal gate electrode layer, and another part is positioned in gate dielectric layer.
Fig. 9 is the ion distribution figure after the embodiment of the present invention injects Er ion, and as seen from Figure 9, Er ion has been injected in gate dielectric layer.
Figure 10 is embodiment of the present invention work function and the graph of a relation injected between ion.As seen from Figure 10, when TiN layer thickness is 68nm, work function moves to right relatively big, when TiN layer thickness is 34nm, is the situation of 68nm compared to TiN layer thickness, and work function moves to left.
And, for different devices, the injection ion of selection also can be different.Such as, for NMOS and PMOS, the injection ion that work function is different is selected.It is commonly used for its work function of the metal ion work function less than metal gate electrode of NMOS semiconductor structure；Its work function of metal ion for PMOS semiconductor structure is more than the work function of metal gate electrode.Especially, in one embodiment, in the semiconductor structure of NMOS, lanthanide series metal is injected.
Additionally, the injection degree of depth that metal ion is on semiconductor structure horizontal direction also can be different.As shown in Figures 4 to 7.In one embodiment of the invention, it is achieved inject degree of depth difference and oblique angle can be used to inject, or use the methods such as injection masking layer in uneven thickness.For the sake of simple, repeat no more.
Step S805, anneals.
As shown in figure 11 for the schematic diagram of remotely oxygen uptake after annealing.Owing to injecting the binding ability binding ability higher than gate dielectric layer Atom with oxygen of the metallic atom in ion-select electrode layer and oxygen, and the binding ability of gate dielectric layer Atom and oxygen is higher than the binding ability of boundary layer Atom with oxygen, the most after annealing, oxygen atom migrates to gate dielectric layer from boundary layer, and the oxygen atom in gate dielectric layer migrates to inject ion-select electrode layer, inject ion and form oxide so that boundary layer SiOxThe most thinning.
As figure 12 a shows for injecting the schematic diagram after the semiconductor structure of ion Er is annealed；It is the schematic diagram after the semiconductor structure annealing of unimplanted ion as shown in Figure 12b.From Figure 12 a and Figure 12 b, after 1000 degree are annealed, inject the dielectric layer after ion and still keep amorphous state, and the dielectric layer of unimplanted ion is clearly visible crystalline polamer, also improves the crystallization temperature of gate medium after therefore injecting ion.And, as can be seen from the figure boundary layer is the most thinning.
For realizing above-described embodiment, the present invention also proposes the manufacture method of another kind of semiconductor structure.It is the flow chart of the manufacture method of the semiconductor structure of another embodiment of the present invention as shown in figure 13, comprises the following steps:
Step S1301, it is provided that substrate.
Step S1302, deposits high-g value to form gate dielectric layer on substrate.
Step S1303, injects metal ion in gate dielectric layer and injects ion-select electrode layer to be formed.
In one embodiment of the invention, inject ion-select electrode layer and be formed at the top of gate dielectric layer.
Step S1304, deposits metal gate material to form metal gate electrode layer on gate dielectric layer.
Step S1305, anneals.
Manufacturing process of manufacture method embodiment shown in Figure 13 and the manufacture method embodiment shown in Fig. 8 etc. can be identical, it is achieved effect the most identical, therefore do not repeat them here.Unlike Wei Yi, before forming metal gate electrode layer, by metal ion implantation gate dielectric layer.
The present invention is by injecting metal ion in semiconductor structure, it is achieved the regulation of semiconductor structure work function, simultaneously can thinning boundary layer, improve the crystallization temperature of gate medium, reduce EOT, improve the performance of semiconductor structure.
Although an embodiment of the present invention has been shown and described, for the ordinary skill in the art, being appreciated that and these embodiments can carry out multiple change without departing from the principles and spirit of the present invention, revise, replace and modification, the scope of the present invention is limited by claims and equivalent thereof.
Claims (2)
1. a semiconductor structure, it is characterised in that including:
Substrate；
It is positioned at the gate dielectric layer of described substrate, wherein, between described gate dielectric layer and described substrate, there is boundary layer；
It is positioned at the metal gate electrode layer on described gate dielectric layer；And
At least one of which injects ion-select electrode layer, and for regulating the work function of described semiconductor structure, and the binding ability of the metallic atom in described injection ion-select electrode layer and oxygen is higher than the binding ability of described gate dielectric layer and described boundary layer Atom and oxygen,
Wherein, a part for described injection ion-select electrode layer is positioned in described gate dielectric layer, and another part of described injection ion-select electrode layer is positioned in described metal gate electrode layer, and wherein, the metal ion in described injection ion-select electrode layer is one or more in Y, Gd,
Wherein, its work function of metal ion for NMOS semiconductor structure is less than the work function of described metal gate electrode；Its work function of metal ion for PMOS semiconductor structure is more than the work function of described metal gate electrode.
2. the manufacture method of a semiconductor structure, it is characterised in that comprise the following steps:
Substrate is provided；
Deposit high-g value is to form gate dielectric layer over the substrate, wherein, has boundary layer between described gate dielectric layer and described substrate；
Described gate dielectric layer deposits metal gate material to form metal gate electrode layer；
Bottom described metal gate electrode layer and/or described gate dielectric layer top is injected metal ion and injected ion-select electrode layer to be formed, the binding ability of the metallic atom in wherein said injection ion-select electrode layer and oxygen is higher than the binding ability of described gate dielectric layer and described boundary layer Atom with oxygen；With
Annealing, wherein, a part for described injection ion-select electrode layer is positioned in described gate dielectric layer, and another part of described injection ion-select electrode layer is positioned in described metal gate electrode layer wherein, and the metal ion of described injection is one or more in Y, Gd,
Wherein, its work function of metal ion for NMOS semiconductor structure is less than the work function of described metal gate electrode；Its work function of metal ion for PMOS semiconductor structure is more than the work function of described metal gate electrode.
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| CN201110125778.1A CN102201435B (en) | 2011-05-16 | 2011-05-16 | Semiconductor structure and manufacture method thereof |
| US13/202,411 US8860143B2 (en) | 2011-05-16 | 2011-08-02 | High-K gate dielectric with work function adjustment metal layer |
| PCT/CN2011/077934 WO2012155392A1 (en) | 2011-05-16 | 2011-08-02 | Semiconductor structure and method for forming the same |
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| CN103928326B (en) * | 2013-01-10 | 2017-06-13 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN104103502B (en) * | 2013-04-02 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
| CN105513967A (en) * | 2014-09-26 | 2016-04-20 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
| US10622356B2 (en) | 2016-01-19 | 2020-04-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing the same |
| CN108122760B (en) * | 2016-11-30 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101221922A (en) * | 2007-01-10 | 2008-07-16 | 台湾积体电路制造股份有限公司 | Methods for manufacturing a cmos device with dual work function |
| CN101800196A (en) * | 2009-02-09 | 2010-08-11 | 中国科学院微电子研究所 | Adjustment method of bimetal gate work function |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101221922A (en) * | 2007-01-10 | 2008-07-16 | 台湾积体电路制造股份有限公司 | Methods for manufacturing a cmos device with dual work function |
| CN101800196A (en) * | 2009-02-09 | 2010-08-11 | 中国科学院微电子研究所 | Adjustment method of bimetal gate work function |
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