CN102201435A - Semiconductor structure and production method thereof - Google Patents
Semiconductor structure and production method thereof Download PDFInfo
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- CN102201435A CN102201435A CN2011101257781A CN201110125778A CN102201435A CN 102201435 A CN102201435 A CN 102201435A CN 2011101257781 A CN2011101257781 A CN 2011101257781A CN 201110125778 A CN201110125778 A CN 201110125778A CN 102201435 A CN102201435 A CN 102201435A
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Abstract
The invention raises a semiconductor structure and a production method thereof, wherein the semiconductor structure comprises a substrate, a grid dielectric layer located on the substrate, an interface layer formed between the substrate and the grid dielectric layer, a metal grid electrode layer located on the grid dielectric layer, and at least one injection ion regulating layer for regulating the power function of the semiconductor structure, wherein the combination capacity between metal atoms in the injection ion regulating layer and oxygen is higher than that between atoms in the grid dielectric layer and oxygen. The metal ions are injected in the semiconductor structure to realize the regulation of the power function of the semiconductor structure, the thinning of the interlayer layer, the increment of the crystallization temperature of a grid dielectric, the decrement of the thickness of the equivalent oxidization layer and the improvement of the performance of the semiconductor structure.
Description
Technical field
The present invention relates to the ic manufacturing technology field, particularly a kind of semiconductor structure and manufacture method thereof.
Background technology
In existing C MOS technology,, use high k (dielectric constant) gate dielectric material and metal gate material usually in order to improve the performance of device.Studies show that, alternative silica material has the higher dielectric constant of ratio silicon oxide as the high-k gate dielectric material of cmos device gate medium, can under the situation that does not reduce physical thickness, improve the size of gate capacitance, thereby under the situation that does not increase electric leakage, reduce equivalent oxide thickness (Equivalent Oxide thickness, EOT), improve device performance.
But high-k gate dielectric material and metal gate material in use exist some problems to need to improve, and for example, interfacial state is higher, and EOT need further reduce, and adjust problem such as work function.But its dielectric constant of formed boundary layer is lower in the annealing process, and thickness hindered further reducing of EOT generally about 1nm, has hindered the further raising of device performance.TiN/HfO is used in the work function aspect
2(work function～5.2eV), but also not proposing a kind of suitable technology is not adding under the tectal situation, realizes the adjustment of semiconductor structure work function makes its demand that satisfies NMOS (work function～4.2eV) can to satisfy the demand of PMOS.In addition, the thermal stability problems of high K medium also is the key technology of always being paid close attention to.Hafnium base gate medium has become the dielectric material of comparatively generally acknowledging, but hafnium oxide just easily crystallization about 500 degree causes element leakage to increase decreased performance.
Summary of the invention
Purpose of the present invention is intended to one of solve the problems of the technologies described above at least.
For this reason, one aspect of the present invention proposes a kind of semiconductor structure, comprising: substrate; Be positioned at the gate dielectric layer on the described substrate, wherein, have boundary layer between described gate dielectric layer and the described substrate; Be positioned at the metal gate electrode layer on the described gate dielectric layer; And one deck injects the ion regulating course at least, the work function that is used to regulate described semiconductor structure, and the binding ability of described injection ion regulating course metallic atom and oxygen is higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen.
In one embodiment of the invention, wherein, described injection ion regulating course is formed at the bottom of described metal gate electrode layer; Perhaps, described injection ion regulating course is formed at the top of described gate dielectric layer; Perhaps, the part of described injection ion regulating course is arranged in described gate dielectric layer, and another part of described injection ion regulating course is arranged in described metal gate electrode layer.
In one embodiment of the invention, the metal ion of described injection ion regulating course is one or more of Er, Y, Gd.
In one embodiment of the invention, be used for the work function of its work function of metal ion of NMOS semiconductor structure less than metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than metal gate electrode.
In one embodiment of the invention, wherein, described injection ion regulating course is identical in the semiconductor structure injection degree of depth in a lateral direction; Perhaps, described injection ion regulating course is dark in the injection degree of depth of middle part in the injection depth ratio at semiconductor structure leakage two ends, close source in a lateral direction; Perhaps, described injection ion regulating course leaks the injection depth as shallow of the injection depth ratio at two ends in the middle part in semiconductor structure close source in a lateral direction; Perhaps, described injection ion regulating course is dark in the injection degree of depth at other positions near the injection depth ratio of position, end, source at semiconductor structure; Perhaps, described injection ion regulating course at semiconductor structure near the injection depth ratio at drain terminal position injection depth as shallow at other positions.
The present invention has also proposed a kind of manufacture method of semiconductor structure on the other hand, may further comprise the steps: substrate is provided; The high k material of deposit wherein, has boundary layer between described gate dielectric layer and the described substrate to form gate dielectric layer on described substrate; The depositing metal grid material is to form metal gate electrode layer on described gate dielectric layer; Inject metal ion and inject the ion regulating course to form in described metal gate electrode layer, the metallic atom of wherein said injection ion regulating course and the binding ability of oxygen are higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen; With anneal.
In one embodiment of the invention, wherein, described injection ion regulating course is positioned at the bottom of described metal gate electrode layer; Perhaps, described injection ion regulating course is positioned at the top of described gate dielectric layer; Perhaps, the part of described injection ion regulating course is arranged in described gate dielectric layer, and another part of described injection ion regulating course is arranged in described metal gate electrode layer.
In one embodiment of the invention, the metal ion of described injection is one or more of Er, Y, Gd.
In one embodiment of the invention, be used for the work function of its work function of metal ion of NMOS semiconductor structure less than metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than metal gate electrode.In one embodiment of the invention, wherein, described injection ion regulating course is identical in the semiconductor structure injection degree of depth in a lateral direction; Perhaps, described injection ion regulating course is dark in the injection degree of depth of middle part in the injection depth ratio at semiconductor structure leakage two ends, close source in a lateral direction; Perhaps, described injection ion regulating course leaks the injection depth as shallow of the injection depth ratio at two ends in the middle part in semiconductor structure close source in a lateral direction; Perhaps, described injection ion regulating course is dark in the injection degree of depth at other positions near the injection depth ratio of position, end, source at semiconductor structure; Perhaps, described injection ion regulating course at semiconductor structure near the injection depth ratio at drain terminal position injection depth as shallow at other positions.
The present invention has also proposed a kind of manufacture method of semiconductor structure on the other hand, may further comprise the steps: substrate is provided; The high k material of deposit wherein, has boundary layer between described gate dielectric layer and the described substrate to form gate dielectric layer on described substrate; Inject metal ion and inject the ion regulating course to form in described gate dielectric layer, the metallic atom of wherein said injection ion regulating course and the binding ability of oxygen are higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen; The depositing metal grid material is to form metal gate electrode layer on described gate dielectric layer; With anneal.
In one embodiment of the invention, described injection ion regulating course is positioned at the top of described gate dielectric layer.
In one embodiment of the invention, the metal ion of described injection is one or more of Er, Y, Gd.
In one embodiment of the invention, be used for the work function of its work function of metal ion of NMOS semiconductor structure less than metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than metal gate electrode.
In one embodiment of the invention, wherein, described injection ion regulating course is identical in the semiconductor structure injection degree of depth in a lateral direction; Perhaps, described injection ion regulating course is dark in the injection degree of depth of middle part in the injection depth ratio at semiconductor structure leakage two ends, close source in a lateral direction; Perhaps, described injection ion regulating course leaks the injection depth as shallow of the injection depth ratio at two ends in the middle part in semiconductor structure close source in a lateral direction; Perhaps, described injection ion regulating course is dark in the injection degree of depth at other positions near the injection depth ratio of position, end, source at semiconductor structure; Perhaps, described injection ion regulating course at semiconductor structure near the injection depth ratio at drain terminal position injection depth as shallow at other positions.
Another aspect of the invention also proposes a kind of manufacture method of semiconductor structure, may further comprise the steps: substrate is provided; The high k material of deposit is to form gate dielectric layer on described substrate; Inject metal ion and inject the ion regulating course to form in described gate dielectric layer, the metallic atom of wherein said injection ion regulating course and the binding ability of oxygen are higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen; The depositing metal grid material is to form metal gate electrode layer on described gate dielectric layer; With anneal.
The present invention realizes the adjusting of semiconductor structure work function by injecting metal ion in semiconductor structure, simultaneously can the attenuate boundary layer, improve the crystallization temperature of gate medium, and reduce EOT, promote the performance of semiconductor structure.
Aspect that the present invention adds and advantage part in the following description provide, and part will become obviously from the following description, or recognize by practice of the present invention.
Description of drawings
Above-mentioned and/or additional aspect of the present invention and advantage are from obviously and easily understanding becoming the description of embodiment below in conjunction with accompanying drawing, wherein:
Fig. 1 is the schematic diagram of the semiconductor structure of first embodiment of the invention;
Fig. 2 is the schematic diagram of the semiconductor structure of second embodiment of the invention;
Fig. 3 is the schematic diagram of the semiconductor structure of third embodiment of the invention;
Fig. 4 to Fig. 7 is respectively in a lateral direction the injection degree of depth different schematic diagram of metal ion at semiconductor structure;
Fig. 8 is the flow chart of manufacture method of the semiconductor structure of one embodiment of the invention;
Fig. 9 is the ion distribution figure behind the injection Er ion;
Figure 10 is the graph of a relation between work function and the injection ion;
Figure 11 is the schematic diagram of the annealing long-range oxygen uptake in back;
Figure 12 a is the schematic diagram after the semiconductor structure of injection ion is annealed;
The schematic diagram of Figure 12 b after for the semiconductor structure annealing of not injecting ion; And
Figure 13 is the flow chart of manufacture method of the semiconductor structure of another embodiment of the present invention.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein identical from start to finish or similar label is represented identical or similar elements or the element with identical or similar functions.Below by the embodiment that is described with reference to the drawings is exemplary, only is used to explain the present invention, and can not be interpreted as limitation of the present invention.
In description of the invention, it will be appreciated that, term " vertically ", " laterally ", " on ", close the orientation of indications such as D score, " preceding ", " back ", " left side ", " right side ", " vertically ", " level ", " top ", " end " " interior ", " outward " or position is based on orientation shown in the drawings or position relation, only be that the present invention for convenience of description and simplification are described, rather than indication or the hint device of indication or element must have specific orientation, with specific orientation structure and operation, therefore can not be interpreted as limitation of the present invention.
Embodiment 1
Be illustrated in figure 1 as the schematic diagram of the semiconductor structure of first embodiment of the invention, this semiconductor structure upwards comprises successively from substrate 1: the boundary layer 10 that contacts with substrate, gate dielectric layer 20, metal gate electrode layer 30 and all be formed at the metal gate electrode layer 30 and be positioned at the injection ion regulating course 41 of metal gate electrode layer 30 bottoms, and to regulate the work function of described semiconductor structure.Wherein, in one embodiment of the invention, the realization of gate dielectric layer or metal gate layer can be a conventional technology such as ald (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), herein for simplicity, repeats no more." bottom " of so-called metal gate electrode layer 30 is the side of metal gate electrode layer 30 near gate dielectric layer 20.That is to say that injection ion regulating course 41 all is arranged in metal gate electrode layer 30 and joins with gate dielectric layer 20.The binding ability of injecting ion regulating course 41 metallic atoms and oxygen is higher than the binding ability of gate dielectric layer 20 and boundary layer 10 atoms and oxygen, for example, can inject metal ions such as Er, Y, Gd.Like this, because the binding ability of injecting ion regulating course 41 metallic atoms and oxygen is higher than the binding ability of gate dielectric layer atom and oxygen, and the binding ability of atom and oxygen is higher than the binding ability of atom and oxygen in the boundary layer in the gate dielectric layer, therefore, oxygen atom migrates to gate dielectric layer from boundary layer, and the oxygen atom in the gate dielectric layer migrates to injection ion regulating course, forms the oxide that injects ion, thus the attenuate boundary layer.
In the present embodiment, the method that can adopt the low energy ion arc to inject is injected metal ion and is formed injection ion regulating course 41 to metal gate electrode layer 30.
Should be understood that and in metal gate electrode layer 30, to inject one or more metal ions, thereby can form one or more layers injection ion regulating course 41.
In addition, because NMOS and PMOS are different for the work function demand, the work function of metal ion of injecting the semiconductor structure of NMOS should be different with the work function of the metal ion of the semiconductor structure that injects PMOS, especially, in the present embodiment, the metal ion that injects in the semiconductor structure of NMOS is the lower metal of work function, as in the lanthanide series metal one or more, thereby satisfies the work function demand of NMOS.
Embodiment 2
Be illustrated in figure 2 as the schematic diagram of the semiconductor structure of second embodiment of the invention, upwards comprise successively: boundary layer 10, gate dielectric layer 20, metal gate electrode layer 30 and injection ion regulating course 42 from substrate 1.It is similar to Example 1 to inject being provided with of ion regulating course 42 in the present embodiment, herein for simplicity, repeats no more, and different is that the injection ion regulating course 42 in the present embodiment is formed at the top of gate dielectric layer 20." top " of so-called gate dielectric layer 20 is the side of gate dielectric layer 20 near metal gate electrode layer 30.That is to say that injection ion regulating course 42 all is arranged in gate dielectric layer 20 and joins with metal gate electrode layer 30.
Embodiment 3
Be illustrated in figure 3 as the schematic diagram of the semiconductor structure of third embodiment of the invention, upwards comprise successively: boundary layer 10, gate dielectric layer 20, metal gate electrode layer 30 and injection ion regulating course 43 from substrate 1.It is similar to Example 1 to inject being provided with of ion regulating course 43 in the present embodiment, herein for simplicity, repeat no more, different is, the part of the injection ion regulating course 43 in the present embodiment is arranged in metal gate electrode layer 30, and another part is arranged in gate dielectric layer 20.
It should be noted that metal ion can be identical in the injection degree of depth in a lateral direction of semiconductor structure, also can be different.Inject the degree of depth by changing, can change equivalent oxide thickness, and then can change the control ability of semiconductor structure raceway groove.
Be respectively in a lateral direction the injection degree of depth different schematic diagram of metal ion as Fig. 4 to Fig. 7, need to prove injecting the ion regulating course among Fig. 4-Fig. 7 can be arranged among boundary layer 10, gate dielectric layer 20, metal gate electrode layer 30 one or more at semiconductor structure.
As shown in Figure 4, the injection depth ratio of injecting the two ends of ion regulating course 44 on the horizontal direction A of semiconductor structure (as the arrow of Fig. 4) is dark in the injection degree of depth of middle part, like this, the two ends attenuate of boundary layer 10 is more, boundary layer 10 thick middle that form, both sides are thin, and then realize the change of horizontal gate capacitance.Especially, the grid structure is thicker near the interfacial layer thickness at leakage two ends, source in this embodiment, and then the control ability to raceway groove weakens, and further weakens the influence that grid are leaked the source, reduces (DIBL) effect thereby alleviate drain-induced barrier, reduces electric leakage.
As shown in Figure 5, the injection depth ratio of injecting the middle part of ion regulating course 45 on the horizontal direction A of semiconductor structure (as the arrow of Fig. 5) is dark in the injection degree of depth at two ends, like this, the two ends attenuate of boundary layer 10 is less, boundary layer 10 intermediate thin that form, both sides are thick, and then realize the change of horizontal gate capacitance.
It is dark near the ion injection degree of depth at source, leakage two ends that ion in semiconductor structure middle part in a lateral direction injects depth ratio, thereby the gate junction structure is thinner near the interfacial layer thickness at source, leakage two ends, then the control ability to raceway groove is stronger, when adding gate voltage, grid structure is easier to realize that near source, leakage two ends charge carrier injects, and can be used as a kind of method that realizes the multidigit storage.
As shown in Figure 6, it is dark in the injection degree of depth at other positions of injection depth ratio at the position of close source end to inject ion regulating course 46, and like this, the position attenuate of the close source end of boundary layer 10 is more, and then realizes the change of horizontal gate capacitance.In this embodiment, grid structure is thinner near the interfacial layer thickness of source end, and is therefore stronger to the control ability of raceway groove, for tunneling transistor, helps promoting the tunnelling probability of charge carrier in the end raceway groove of source, and then improves drive current.
As shown in Figure 7, inject the injection depth as shallow of ion regulating course 47 at other positions of injection depth ratio at the position of close drain terminal, like this, the position attenuate of the close drain terminal of boundary layer 10 is more, and then realizes the change of horizontal gate capacitance.In this embodiment, the grid structure is thicker near the interfacial layer thickness of drain terminal, and then the control ability to raceway groove weakens, and alleviates drain-induced barrier and reduces (DIBL) effect, reduces electric leakage.
Should understand; above-mentioned Fig. 4 extremely embodiment shown in Figure 7 only is schematic example; be not limited to the present invention, those skilled in the art can change the injection degree of depth of metal ion according to actual needs, and these changes and variation all should be included in protection scope of the present invention.
For realizing the foregoing description, the present invention also proposes a kind of manufacture method of semiconductor structure.Be illustrated in figure 8 as the flow chart of manufacture method of the semiconductor structure of one embodiment of the invention, may further comprise the steps:
Step S801 provides substrate.
Step S802, the high k material of deposit wherein, has boundary layer to form gate dielectric layer between gate dielectric layer and substrate on substrate.
Step S803, the depositing metal grid material is to form metal gate electrode layer on gate dielectric layer.
Above-mentioned steps S801 can adopt existing techniques in realizing to step S803, herein for simplicity, is not described in detail.
Step S804 injects metal ion and injects the ion regulating course to form in metal gate electrode layer.
Particularly, can metal ion be injected metal gate electrode layer by the method that the low energy ion arc injects and inject the ion regulating course to form.
The metallic atom of injection ion regulating course and the binding ability of oxygen are higher than the binding ability of gate dielectric layer atom and oxygen, for example, can inject Er, Y, Gd etc.In addition, can inject a metal ion species or multiple metal ion, thereby in semiconductor structure, form one or more layers injection ion regulating course.
And, should be understood that the position difference of the metal ion of injection, the size of work function and equivalent oxide thickness (EOT) also can change.For example, in one embodiment, inject the bottom that the ion regulating course is positioned at metal gate electrode layer; In another embodiment, inject the top that the ion regulating course is positioned at gate dielectric layer; In yet another embodiment, a part of injecting the ion regulating course is arranged in metal gate electrode layer, and another part is arranged in gate dielectric layer.
Fig. 9 injects ion distribution figure behind the Er ion for the embodiment of the invention, and as seen from Figure 9, the Er ion is injected in the gate dielectric layer.
Figure 10 is the graph of a relation between embodiment of the invention work function and the injection ion.As seen from Figure 10, when the TiN layer thickness was 68nm, work function moved to right bigger, when the TiN layer thickness is 34nm, was the situation of 68nm compared to the TiN layer thickness, and work function moves to left.
And for different devices, the injection ion of selection also can be different.For example, for NMOS and PMOS, select the different injection ion of work function.Usually, be used for the work function of its work function of metal ion of NMOS semiconductor structure less than metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than metal gate electrode.Especially, in one embodiment, in the semiconductor structure of NMOS, inject lanthanide series metal.
In addition, metal ion also can be different in the semiconductor structure injection degree of depth in a lateral direction.Extremely shown in Figure 7 as Fig. 4.In one embodiment of the invention, realize injecting degree of depth difference and can adopt the oblique angle to inject, perhaps adopt methods such as injection masking layer in uneven thickness.Herein for simplicity, repeat no more.
Step S805 anneals.
Be the schematic diagram of the annealing long-range oxygen uptake in back as shown in figure 11.Because the metallic atom of injection ion regulating course and the binding ability of oxygen are higher than the binding ability of gate dielectric layer atom and oxygen, and the binding ability of atom and oxygen is higher than the binding ability of atom and oxygen in the boundary layer in the gate dielectric layer, therefore after annealing, oxygen atom migrates to gate dielectric layer from boundary layer, and the oxygen atom in the gate dielectric layer migrates to injection ion regulating course, inject ion and form oxide, make boundary layer SiO
xObviously attenuation.
Be depicted as the schematic diagram after the semiconductor structure annealing of injecting ion Er as Figure 12 a; Be depicted as the schematic diagram after the semiconductor structure annealing of not injecting ion as Figure 12 b.By Figure 12 a and Figure 12 b as seen, after 1000 degree annealing, the dielectric layer that injects behind the ion still keeps amorphous state, and the dielectric layer that does not inject ion is obviously seen crystalline polamer, therefore injects the crystallization temperature that has also improved gate medium behind the ion.And, the as can be seen from the figure obvious attenuate of boundary layer.
For realizing the foregoing description, the present invention also proposes the manufacture method of another kind of semiconductor structure.Be the flow chart of manufacture method of the semiconductor structure of another embodiment of the present invention as shown in figure 13, may further comprise the steps:
Step S1301 provides substrate.
Step S1302, the high k material of deposit is to form gate dielectric layer on substrate.
Step S1303 injects metal ion and injects the ion regulating course to form in gate dielectric layer.
In one embodiment of the invention, inject the top that the ion regulating course is formed on gate dielectric layer.
Step S1304, the depositing metal grid material is to form metal gate electrode layer on gate dielectric layer.
Step S1305 anneals.
The manufacturing process of manufacture method embodiment shown in Figure 13 and manufacture method embodiment shown in Figure 8 etc. can be identical, and the effect of realization is also identical, therefore do not repeat them here.Uniquely different be, before forming metal gate electrode layer, in metal ion injection grid dielectric layer.
The present invention realizes the adjusting of semiconductor structure work function by injecting metal ion in semiconductor structure, simultaneously can the attenuate boundary layer, improve the crystallization temperature of gate medium, and reduce EOT, improve the performance of semiconductor structure.
Although illustrated and described embodiments of the invention, for the ordinary skill in the art, be appreciated that without departing from the principles and spirit of the present invention and can carry out multiple variation, modification, replacement and modification that scope of the present invention is by claims and be equal to and limit to these embodiment.
Claims (15)
1. a semiconductor structure is characterized in that, comprising:
Substrate;
Be positioned at the gate dielectric layer on the described substrate, wherein, have boundary layer between described gate dielectric layer and the described substrate;
Be positioned at the metal gate electrode layer on the described gate dielectric layer; And
At least one deck injects the ion regulating course, the work function that is used to regulate described semiconductor structure, and the binding ability of the metallic atom of described injection ion regulating course and oxygen is higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen.
2. semiconductor structure according to claim 1 is characterized in that, wherein,
Described injection ion regulating course is formed at the bottom of described metal gate electrode layer;
Perhaps, described injection ion regulating course is formed at the top of described gate dielectric layer;
Perhaps, the part of described injection ion regulating course is arranged in described gate dielectric layer, and another part of described injection ion regulating course is arranged in described metal gate electrode layer.
3. semiconductor structure according to claim 1 is characterized in that, the metal ion of described injection ion regulating course is one or more of Er, Y, Gd.
4. semiconductor structure according to claim 1 is characterized in that, is used for the work function of its work function of metal ion of NMOS semiconductor structure less than described metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than described metal gate electrode.
5. semiconductor structure according to claim 1 is characterized in that, wherein,
Described injection ion regulating course is identical in the semiconductor structure injection degree of depth in a lateral direction;
Perhaps, described injection ion regulating course is dark in the injection degree of depth of middle part in the injection depth ratio at semiconductor structure leakage two ends, close source in a lateral direction;
Perhaps, described injection ion regulating course leaks the injection depth as shallow of the injection depth ratio at two ends in the middle part in semiconductor structure close source in a lateral direction;
Perhaps, described injection ion regulating course is dark in the injection degree of depth at other positions near the injection depth ratio of position, end, source at semiconductor structure;
Perhaps, described injection ion regulating course at semiconductor structure near the injection depth ratio at drain terminal position injection depth as shallow at other positions.
6. the manufacture method of a semiconductor structure is characterized in that, may further comprise the steps:
Substrate is provided;
The high k material of deposit wherein, has boundary layer between described gate dielectric layer and the described substrate to form gate dielectric layer on described substrate;
The depositing metal grid material is to form metal gate electrode layer on described gate dielectric layer;
Inject metal ion and inject the ion regulating course to form in described metal gate electrode layer, the metallic atom of wherein said injection ion regulating course and the binding ability of oxygen are higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen; With
Anneal.
7. the manufacture method of semiconductor structure according to claim 6 is characterized in that, wherein,
Described injection ion regulating course is positioned at the bottom of described metal gate electrode layer;
Perhaps, described injection ion regulating course is positioned at the top of described gate dielectric layer;
Perhaps, the part of described injection ion regulating course is arranged in described gate dielectric layer, and another part of described injection ion regulating course is arranged in described metal gate electrode layer.
8. the manufacture method of semiconductor structure according to claim 6 is characterized in that, the metal ion of described injection is one or more of Er, Y, Gd.
9. the manufacture method of semiconductor structure according to claim 6 is characterized in that, is used for the work function of its work function of metal ion of NMOS semiconductor structure less than described metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than described metal gate electrode.
10. the manufacture method of semiconductor structure according to claim 6 is characterized in that, wherein,
It is identical that described injection ion regulating course injects the degree of depth at semiconductor structure ion in a lateral direction;
Perhaps, described injection ion regulating course is dark in the ion injection degree of depth of the ion injection depth ratio middle part at leakage two ends, the close in a lateral direction source of semiconductor structure;
Perhaps, described injection ion regulating course leaks the injection depth as shallow of the ion injection depth ratio middle part at two ends in a lateral direction near the source at semiconductor structure;
Perhaps, described injection ion regulating course is dark near the ion injection degree of depth at other positions of ion injection depth ratio at the position of source end at semiconductor structure;
Perhaps, described injection ion regulating course injects the ion injection depth as shallow at other positions of depth ratio near the ion at the position of drain terminal at semiconductor structure.
11. the manufacture method of a semiconductor structure is characterized in that, may further comprise the steps:
Substrate is provided;
The high k material of deposit wherein, has boundary layer between described gate dielectric layer and the described substrate to form gate dielectric layer on described substrate;
Inject metal ion and inject the ion regulating course to form in described gate dielectric layer, the metallic atom of wherein said injection ion regulating course and the binding ability of oxygen are higher than the binding ability of described gate dielectric layer and described boundary layer atom and oxygen;
The depositing metal grid material is to form metal gate electrode layer on described gate dielectric layer; With
Anneal.
12. the manufacture method of semiconductor structure according to claim 11 is characterized in that, described injection ion regulating course is positioned at the top of described gate dielectric layer.
13. the manufacture method of semiconductor structure according to claim 11 is characterized in that, the metal ion of described injection is one or more of Er, Y, Gd.
14. the manufacture method of semiconductor structure according to claim 11 is characterized in that, is used for the work function of its work function of metal ion of NMOS semiconductor structure less than described metal gate electrode; Be used for the work function of its work function of metal ion of PMOS semiconductor structure greater than described metal gate electrode.
15. the manufacture method of semiconductor structure according to claim 11 is characterized in that, wherein,
Described injection ion regulating course is identical in the semiconductor structure injection degree of depth in a lateral direction;
Perhaps, described injection ion regulating course is dark in the injection degree of depth of middle part in the injection depth ratio at semiconductor structure leakage two ends, close source in a lateral direction;
Perhaps, described injection ion regulating course leaks the injection depth as shallow of the injection depth ratio at two ends in the middle part in semiconductor structure close source in a lateral direction;
Perhaps, described injection ion regulating course is dark in the injection degree of depth at other positions near the injection depth ratio of position, end, source at semiconductor structure;
Perhaps, described injection ion regulating course at semiconductor structure near the injection depth ratio at drain terminal position injection depth as shallow at other positions.
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| US13/202,411 US8860143B2 (en) | 2011-05-16 | 2011-08-02 | High-K gate dielectric with work function adjustment metal layer |
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| CN106981488A (en) * | 2016-01-19 | 2017-07-25 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacture method |
| CN108122760A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN106981488A (en) * | 2016-01-19 | 2017-07-25 | 台湾积体电路制造股份有限公司 | Semiconductor devices and its manufacture method |
| US10622356B2 (en) | 2016-01-19 | 2020-04-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and method of manufacturing the same |
| US10991695B2 (en) | 2016-01-19 | 2021-04-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for manufacturing semiconductor device |
| US11257819B2 (en) | 2016-01-19 | 2022-02-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device |
| CN108122760A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108122760B (en) * | 2016-11-30 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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