JP2005526401A5

JP2005526401A5 -

Info

Publication number: JP2005526401A5
Application number: JP2004506086A
Authority: JP
Filing date: 2003-05-06
Publication date: 2006-01-05
Anticipated expiration: 2023-05-06

Claims

Semiconductor substrate;
A region implanted into the substrate;
A metal layer coupled to the implanted region, the metal layer appearing to be electrically coupled to the implanted region in plan view; and between the implanted region and the metal layer A provided dielectric layer, thereby insulating the metal layer from the implanted region;
A disguised circuit structure having:
When viewed in the plan view, the dielectric layer may have a dimension the dielectric layer to be at least partially hidden by the features of the circuit structure, the spoofed circuit structure between the dielectric layer and the metal layer impersonated circuit structure characterized in that it further have a installed polysilicon layer.

2. The camouflaged circuit structure of claim 1, wherein the circuit structure feature that at least partially hides the dielectric layer includes a metal plug connected to the metal layer.

It further includes a silicide layer provided so as to cover the implanted region, and the metal layer is electrically connected to the implanted region via the silicide layer and the metal plug connected to the metal layer as usual. 3. The camouflaged circuit structure of claim 2, wherein the dielectric layer is electrically coupled and the dielectric layer prevents the electrical coupling.

4. The camouflaged circuit structure according to claim 3, wherein the dielectric layer is provided between the metal layer and the silicide layer.

2. The camouflaged circuit structure according to claim 1 , wherein the semiconductor substrate is made of silicon, and the dielectric layer is made of silicon dioxide.

The circuit structure, when viewed in plan view, spoofed circuit structure according to any one of claims 1 to 4, characterized in that appears to be a field effect transistor functioning normally.

The circuit structure, when viewed in plan view, spoofed circuit structure according to any one of claims 1 to 4, characterized in that appears to be a bipolar device to function normally.

Semiconductor substrate;
An active region in the substrate;
A conductive layer connected to the active region, the conductive layer appearing to be arranged to contribute to electrical conduction through the active region by application of a control voltage in plan view;
A control electrode coupled to the conductive layer, the control electrode appearing to be electrically connected to the conductive layer in plan view; and provided between the conductive layer and the control electrode At least one dielectric layer, the dielectric layer intentionally separating the conductive layer from an electrical conduction contribution through the active region in response to application of a control voltage to the control electrode;
Have a, the spoofed circuit structure further wherein a polysilicon layer between the at least one dielectric layer and the control electrode, the at least one dielectric layer, characterized in that organic oxide layer A disguised circuit structure.

9. The camouflaged circuit structure of claim 8 , wherein the at least one dielectric layer has a dimension such that the dielectric layer is at least partially hidden by features of the circuit structure when viewed in plan view. .

The active region is a gate region, at least one dielectric layer is impersonated circuit structure according to claim 8 or 9, characterized in that to set the state of "off" the gate region electrically conductively .

Connecting at least one conductive contact to the active region; and interfering with electrical conduction between the at least one conductive contact and the active region by inserting a barrier insulating layer;
To prevent reverse engineering.

Providing at least one polysilicon layer under the one conductive contact, wherein the interfering insulating layer is between the two polysilicon layers, and at least one polysilicon layer is formed thereon; The method of claim 11 , comprising a silicide layer formed.

13. A method according to claim 11 or 12 , wherein the interfering insulating layer is silicon dioxide.

Forming a conductive layer on the substrate;
Providing a metal layer; and inserting means for preventing electrical contact between the metal layer and the conductive layer;
A method of preventing semiconductor contacts from functioning.

The method of claim 14 , wherein the means for preventing electrical contact comprises providing an oxide layer and a polysilicon layer.

16. A method according to claim 14 or 15 , further comprising the step of concealing the blocking means under the metal layer.

An active region provided in the substrate;
An insulating non-electrically conductive layer provided to cover at least part of the active region;
A polysilicon layer provided so as to cover at least part of the insulating non-electrically conductive layer provided so as to cover at least part of the active region, wherein the insulating non-electrically conductive layer includes A polysilicon layer electrically insulating the polysilicon layer from the active region; and a metal layer electrically shared with the polysilicon layer and electrically isolated from the active region;
A pseudo-transistor having
Each of the insulative non-electrically conductive layer, the polysilicon layer, and the metal layer has dimensions such that the metal layer appears to be electrically shared with the active region when viewed in plan view. A pseudo transistor characterized by that.

The metal layer has a metal plug, the metal plug has a cross section, the polysilicon layer has a cross section, and the cross section of the metal plug and the cross section of the polysilicon layer have substantially the same dimensions. The pseudo-transistor according to claim 17 , wherein the pseudo-transistor is present.

Pseudo transistor according to any one of claims 17 or 18, further comprising a first silicide layer provided so as to cover the active region.

The pseudo-transistor according to claim 19 , further comprising a second silicide layer provided to cover the polysilicon layer.

Metal layer;
A first polysilicon layer;
A second polysilicon layer provided between at least the metal layer and the first polysilicon layer; and at least provided between the first polysilicon layer and the second polysilicon layer. Insulating non-electrically conductive layer;
Having non-operational semiconductor gate contact.

The metal layer has a metal plug, the metal plug has a cross section, the second polysilicon layer has a cross section, and the cross section of the metal plug and the cross section of the second polysilicon layer are The non-operating semiconductor gate contact of claim 21 , wherein the semiconductor gate contact is essentially the same size.

The semiconductor gate contact does not work according to claim 21 or 22, characterized in that it further comprises a first silicide layer provided so as to cover at least a portion of said first polysilicon layer.

24. The non-operating semiconductor gate contact according to claim 23 , further comprising a second silicide layer provided to cover the second polysilicon layer.

The pseudo-transistor according to claim 17 or the non-operating semiconductor gate contact according to claim 21 , wherein the insulating non-electrically conductive layer comprises silicon dioxide SiO ₂ .

The pseudo-transistor of claim 17 or the non-operating semiconductor gate contact of claim 21 , wherein the insulating non-electrically conductive layer comprises silicon nitride Si ₃ N ₄ .

Forming an active region in the substrate;
Defining a dielectric layer covering at least a portion of the active region; and providing a metal layer covering the dielectric layer;
A method of manufacturing a pseudo-transistor having
A method of manufacturing a pseudo-transistor, wherein the dielectric layer prevents an electrical connection between the active region and the metal layer.

28. The method of claim 27 , wherein the step of providing the metal layer comprises forming a metal plug that at least partially hides the dielectric layer.

Forming a silicide layer covering the active region, wherein the step of forming the silicide layer is present after the step of forming the active region and before the step of defining a dielectric layer; 28. The method of claim 27 .

Forming a silicide layer covering the dielectric layer, wherein the step of forming the silicide layer is present after the step of defining the dielectric layer and before the step of providing the metal layer. 28. The method of claim 27 .

Forming a first silicide layer so as to cover the active region, wherein the step of forming the first silicide layer is after the step of forming the active region, and the metal layer is formed Existing before the step of providing; and forming a second silicide layer to cover the dielectric layer, wherein the step of forming the second silicide layer defines the dielectric layer Existing after the step and before the step of providing the metal layer;
The method of claim 27 , further comprising:

Providing a polysilicon layer overlying the dielectric layer, the providing the polysilicon layer comprising: providing the metal layer after the step of defining the dielectric layer; 28. The method of claim 27 , wherein the method is present before.

28. The method of claim 27 , wherein the step of forming the active region in a substrate is further defined by implanting the active region into a silicon substrate and the dielectric layer is comprised of silicon dioxide. .

34. A method according to any of claims 27 to 33 , wherein the dielectric layer comprises silicon nitride.

Defining an active region in the substrate;
Connecting a conductive layer to the active region;
Forming a dielectric layer overlying the conductive layer; and providing a control electrode coupled to the active region;
The reverse engineer has a method to confuse
A method of confuse a reverse engineer, characterized in that the dielectric layer interferes with the electrical conduction contribution through the active region in response to application of a control voltage to the control electrode to the conductive layer.

36. The method of claim 35 , further comprising hiding at least a portion of the dielectric layer under the control electrode.

37. The method of claim 35 or 36 , further comprising forming a polysilicon layer covering at least a portion of the dielectric layer, the dielectric layer comprising an oxide layer.