JP2005524282A - Method and device for pulse shaping a QPSK signal - Google Patents

Abstract

The baseband shaping device comprises a plurality of coefficient memories each having an input address bus, a multiplexer input and a coefficient value output. The device further comprises a plurality of shift registers each having an input, a digital / analog clock input and an output coupled to each one of the coefficient value outputs. The device includes a plurality of negative value circuits each having an input and an output coupled to each one of the outputs of the first shift register, a first input coupled to each one of the outputs of the first shift register. And a plurality of multiplexers each having a second input coupled to each one of the outputs of the plurality of negative value circuits. The device further comprises an adder having a plurality of inputs coupled to the plurality of second shift registers and the plurality of second shift registers.

Description

The present invention relates generally to modulation of RF carrier signals, and more particularly to systems and techniques for shaping baseband signals for QPSK modulation.
BACKGROUND OF THE INVENTION In communications applications, multiphase modulation techniques are often used to increase bandwidth efficiency in telephone and satellite data communications, as multi-bit symbols, and in particular quadrature phase modulation (QPSK). It is desirable to transmit value data. However, when QPSK modulation is used in a data communication terminal, there is often a demand to reduce intersymbol interference by limiting the spectrum characteristics of a radio frequency (RF) modulated signal. As is already known in the art, there are several filtering techniques that shape the baseband signal, and the digital signal is RF modulated into two data streams, also called quadrature signals: an in-phase signal and a quadrature signal Separated before.

Conventional techniques for implementing the filter include a square root raised cosine (SRRC) filter that provides an output having data samples generated at a frequency F _da equal to the clock rate of the digital / analog converter. A typical filter circuit is a tapped delay line filter with filter taps at a time interval of 1 / (F _da ). Input bits arrive at the symbol rate (Rs). Typically, the filter coefficients are selected such that the response to the impulse signal is an SRRC characteristic waveform in the time domain. The impulse signal is input to a filter, one symbol at a time, to provide a base bend signal to modulate a radio frequency (RF) carrier.

  This impulse signal consists of a few samples of value +1 (for data “0”) or −1 (for data “1”) followed by value 0. In typical filters, many multipliers are not used to multiply the coefficients by the value 0. This adds digital logic that is not necessarily required.

  In communication applications, low cost and compact size are important considerations. Digital filters such as those described above are often implemented as field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs). The cost and size of the filter can be reduced by reducing the circuit portion necessary for realizing the specific filter.

  Therefore, it is desirable to reduce the size and cost of the digital logic that implements the baseband filter, including reducing the amount of circuitry dedicated to storing the coefficient values to generate the filtered baseband signal.

SUMMARY OF THE INVENTION In accordance with the present invention, a device comprises a plurality of coefficient memories each having an input address bus, a multiplexer input, and a coefficient value output. The device also includes a plurality of first shift registers each having an input coupled to a respective one of the coefficient value outputs, a digital / analog (D / A) clock input, and an output. The device includes a plurality of negative value circuits each having an input and an output coupled to a respective one of the outputs of the first shift register, and each coupled to a respective one of the outputs of the first shift register. And a plurality of 2: 1 multiplexers having a first input and a second input coupled to each one of the plurality of negative circuit outputs. The device also includes a plurality of second shift registers each having an input coupled to a respective one of a plurality of 2: 1 multiplexer outputs, a digital / analog (D / A) clock input, and an output; And an adder having a plurality of inputs coupled to each one of the plurality of second shift registers. Such a configuration reduces the digital logic that implements the filter and the amount of circuitry dedicated to storing coefficient values that produces the filtered baseband signal.

  According to a further aspect of the present invention, a method for shaping a baseband signal includes providing a plurality of coefficient memories each having a plurality of coefficient values representing filter response waveform values, and a coefficient memory of each coefficient memory. Including determining the address. Furthermore, the method addresses each of the plurality of coefficient memories, retrieves the addressed coefficient value from each of the plurality of coefficient memories, and negative values for each of the retrieved coefficient values of the coefficient value. Providing one of a retrieved value and a negative value in response to the baseband signal, and summing the selected value from each coefficient to provide a shaped signal including. This technique can efficiently implement a square root raised cosine filter with reduced storage requirements for filter coefficients.

The above features of the present invention as well as the present invention itself can be more fully understood from the following description of the drawings.
DETAILED DESCRIPTION OF THE INVENTION Before providing a detailed description of the invention, it may be useful to define some of the terms used in the description. As used herein, two's complement logic coefficients and logic blocks refer to negative representations of digital signal values, in particular, negative values of filter coefficients. As is known, conventional logic building blocks for adders use a two's complement architecture. It will be appreciated by those skilled in the art that instead of a two's complement representation, other representations of negative coefficients, such as offset binary numbers and signed amplitude representations, may be used with the corresponding negative logic circuit.

For purposes of the present invention, as used herein, the term “coefficient” is generally used to multiply an input bit stream to implement a particular filter. Refers to the factor. The coefficients include a plurality of coefficient values that are discrete digital samples representing the filter response waveform values of a particular filter waveform. For example, C0 represents the first coefficient to be used in a particular filter. The coefficient values C0 _{0 to} C0 _N represent discrete samples of the coefficients, and these values are stored in the coefficient memory. The coefficient value is addressed by a coefficient (here C0) and sample numbers 0-N. N is determined by the relationship between the symbol rate and the D / A converter clock rate. For example, if the D / A clock rate is 16 times the symbol rate, N is equal to 15 and there are 16 samples per coefficient.

  One inventive concept of the present invention stems from the recognition that the filter coefficients are symmetrical so that the storage requirement of coefficient values can be reduced. By storing the combined coefficient values by the ability to take negative values (eg 2's complement) of the coefficient values, the coefficients are combined to halve the amount of memory required to store the baseband signal shaping filter values, for example. It is. Address generation circuitry is provided for addressing the coefficient memory and providing coefficient values in an appropriate order in response to the baseband signal.

  Referring now to FIG. 1, an exemplary QPSK modulator 100 according to the present invention includes an in-phase baseband bit shaping circuit 104I and a quadrature baseband bit shaping circuit 104Q (collectively referred to as baseband bit shaping circuit 104). ) Is coupled to the transmit data interface 102. Baseband bit shaping circuits 104I, 104Q each have an input for receiving a serial bit stream provided by a plurality of in-phase data symbols and quadrature data symbols. Baseband bit shaping circuits 104I and 104Q are timing / control circuits for timing signals and control signals including a master clock signal, a digital / analog converter (D / A) clock signal, and a symbol (SYM) clock input, respectively. From 118. Each of the circuits 104I and 104Q has a D / A output. The QPSK modulator 100 also includes a pair of digital / analog converters (D / A) 106, each coupled to the D / A output of the baseband bit shaping circuits 104I, 104Q. The D / A is coupled to the RF modulator 108, which is coupled to the upconverter 110. Upconverter 110 is coupled to power amplifier 112, which is coupled to diplexer 114, which is coupled to antenna 116 as is known.

  In one embodiment, QPSK modulator 100 comprising portions of transmit data interface 102 and baseband bit shaping circuit 104 is implemented in a field programmable gate array (FPGA) in a satellite communications modulator. The The transmit data interface 102 and the baseband bit shaping circuit 104 process the data (grouped as symbols) and provide the processed signal to the two D / A 106 as discrete digital waveform values.

  The transmit data interface 102 provides serial data to the baseband bit shaping circuit 104 and provides in-phase and quadrature waveforms to modulate the radio frequency carrier. In one embodiment, the transmit data interface 102 selects a synchronous serial interface or an asynchronous parallel interface for data transmission. When a synchronous serial interface is used, the external transmission circuit uses 2-bit data symbols (including 1-bit I and 1-bit Q at each rising edge of the clock symbol clock provided by the timing / control circuit 118). Multi-bit binary data). When using an asynchronous parallel interface, the data to be transmitted is sent as symbols through the byte width control / status bus to the transmit data interface 102 and buffered in a first in first out register (FIFO) (not shown). The FIFO is implemented as part of the transmit data interface 102 and allows an external processor (not shown) to send multiple bytes of message data to the transmit data interface 102 before transmission. The byte wide output of the FIFO is then parallel / serial converted into two bit symbols for QPSK modulation at each rising edge of the clock symbol clock. It will be appreciated that the exemplary embodiment of FIG. 1 illustrates one of several possible configurations for QPSK modulation 100.

  Baseband bit shaping circuit 104 shapes the serial data provided by the transmit data interface and digitally represents the digital waveform representing the filtered baseband signal, as further described in connection with FIGS. 2A-4D. / Supplied to the analog converter 106. Digital / analog converter 106 provides an analog waveform to RF modulator 108 to modulate the RF carrier signal, which is converted to a higher frequency by upconverter 110. The power amplifier 112 amplifies the upconverted signal, and then the diplexer 114 receives this signal. In transmit mode, diplexer 114 sends the upconverted and amplified signal to the antenna for transmission.

  2A to 2D, an in-phase baseband bit shaping circuit 200I similar to the baseband bit shaping circuit 104I (FIG. 1) includes a plurality of delay elements 203 and a plurality of taps 205. A tapped delay line 202I coupled to the in-phase data bit stream is provided. Circuit 200I further includes a plurality of stages 204a-204n (generally referred to as stage 204) each coupled to a corresponding tap 205 of delay line 202I. Each stage 204 has an output coupled to a corresponding input of adder 206I, and adder 206I has an output coupled to the input of scaler circuit 208I. Scaler 208I has an output coupled to an in-phase D / A (not shown). The orthogonal baseband bit shaping circuit 200Q includes a circuit having a similar configuration.

  A quadrature baseband bit shaping circuit 200Q, similar to the baseband bit shaping circuit 104Q (FIG. 1), has a plurality of delay elements 213 and a plurality of taps 215 coupled to an orthogonal data bit stream. A delay line 202Q is provided. Circuit 200Q further includes a plurality of stages 214a-214n (generally referred to as stage 214) each coupled to a corresponding tap 215 of delay line 202Q. Each stage 214 has an output coupled to a corresponding input of summer 206Q, and summer 206Q has an output coupled to the input of scaler circuit 208Q. Scaler 208Q has an output coupled to an in-phase D / A (not shown).

  Referring now to FIG. 2E, each stage 204 of the baseband shaping circuit 200I of FIGS. 2A-2D includes a coefficient memory 220 coupled to a coefficient address generator 228 via an address bus 230. Coefficient memory 220 includes a clock input signal 232 coupled to coefficient address generator 228. Coefficient memory 220 includes a coefficient memory output 222 coupled to a first input of multiplexer 226. The coefficient memory is also coupled to a negative value circuit 224 (here 2's complement circuit) to provide the negative value of the coefficient memory output 222 to the second input of the multiplexer 226. Multiplexer 226 includes a select input 234 and an output 240 coupled to a corresponding tap 205 (FIGS. 2A-2D) of delay line 202. It should be understood that a similar circuit is used for each stage 214 of circuit 200Q of FIGS. 2A-2D.

  Referring to FIGS. 2A-2E, in operation, the baseband bit shaping circuit 200 provides the digital signal processing necessary for spectrum limitation of the modulated output carrier. The coefficient address generator 228 is clocked by a D / A clock to provide a coefficient address that addresses the coefficient memory and provides waveform samples at the D / A clock frequency. In one embodiment that provides QPSK modulation, the baseband bit-shaping waveform is a square root raised cosine (SRRC) waveform with various roll-off factors. In one embodiment, the roll-off factor can be selected at 25%, 35%, 50% and 70%. The roll-off factor is kept constant in a single transmission of a series of symbols called a burst. A different set of coefficient values is stored in coefficient memory 220 for each roll-off factor. Several memory configurations, including loading different sets of coefficient values into memory 220 when different roll-off factors are selected, or having one large memory with a different section for each set of coefficient values One skilled in the art will appreciate that can be provided. After a particular set of coefficient memory values is selected for a particular burst, coefficient address generator 228 addresses the selected set of coefficient values in coefficient memory 220. A particular roll-off factor is selected for a particular burst depending on the transmission bandwidth, transmitter power amplifier 112 (FIG. 1) and receiver complexity. The lower the roll-off factor (for example 25%), the smaller the link bandwidth used, so the lower the roll-off factor, the more limited the available bandwidth is used by other links. Is advantageous. However, the lower the roll-off factor, the higher the ratio of peak transmission power to average transmission power. The higher the ratio, the more the transmitter power amplifier needs to have a higher peak power capability, which makes the transmitter more complex. Also, the lower the roll-off factor, the longer the matched filter required at the receiver that receives the transmitted waveform. This makes the receiver more complicated. The higher the roll-off factor (eg 70%), the more link bandwidth is used, so the higher the factor, the less the amount of limited bandwidth available to other links is disadvantageous . However, the higher the roll-off factor, the lower the ratio of peak transmission power to average transmission power. If the ratio is low, the transmitter power amplifier can have a low peak power capability, which reduces transmitter complexity. The lower the roll-off factor, the shorter the required matched filter at the receiver that receives the transmitted waveform. This reduces the complexity of the receiver. Although additional storage capacity may be required to provide flexibility in switching between coefficient memories, overall storage requirements are reduced by the present invention. Those skilled in the art will understand that once the coefficients are provided by the present invention, memory banks or other coefficient configurations can be selected that correspond to different roll-off factors using known techniques and the trade-offs described above. Let's do it.

Stage 204I operates as one tap of a digital filter having a tapped delay line structure (here 8 symbols long) with a predetermined set of coefficients in each tap based on the desired roll-off factor. The data is multiplied by the coefficients and the results from each tap are added in adder 206I, scaled by scaler circuit 208I, and then used to drive D / A converter 106 (FIG. 1). This structure is the same for the I and Q channels. Since stage 204I is an interpolation filter tap, there are N _INT samples in the waveform supplied to D / A converter 106 for every symbol processed by the filter. However, _INT indicates interpolation, N _INT = (D / A clock rate) / (symbol rate), N _INT = N + 1, and N indicates the number of samples described above.

The symbol bit coefficients are “multiplied” by changing or not changing their sign according to the value of each symbol (+1 or −1). In one embodiment using a two's complement operation, this operation corresponds to using a coefficient value or its “two's complement” value. Note that each symbol multiplies each coefficient only once. The effect is that the filter is an 8N _INT long tapped delay line filter (in the case of an 8-tap filter), and the input to the tapped delay line is an impulse (+1 or -1 followed by [N _INT -1] Is the same as having 0).

When the filter is implemented in analog, instead of an impulse (+1 or −1 followed by [N _INT −1] zeros) being input to the tapped delay line, +1 or −1 is N _INT times. Repeated. In the second case (repetition), the transmit spectrum of the waveform is multiplied by the [sine (fx) / (fx)] function, which is defined as “sinc (fx)”. Where f is the frequency offset from the carrier and x is a factor that depends on the symbol rate. To compensate for this, the coefficient is calculated from the inverse Fourier transform of the desired spectrum after multiplying the desired spectrum by [1 / sinc (fx)] = [(fx) / sine (fx)]. The This is so-called “inverse sinc function compensation”. Since the present invention realizes a mathematical equivalent of an impulse, this inverse sinc function compensation is unnecessary.

  Referring now to FIGS. 3A-3C, a schematic diagram of a baseband shaping circuit 300 according to a further aspect of the present invention includes a tapped delay line 302I similar to the delay line 202I of FIGS. 2A-2D, and a delay line A tapped delay line 302Q similar to 202Q is provided. Tapped delay line 302I is coupled with an in-phase data bit stream (I data), and tapped delay line 302Q is coupled with a quadrature data bit stream (Q data). Circuit 300 further includes a plurality of stages 304a-304n coupled to the corresponding taps of delay lines 302I, 302Q, respectively. Each stage 304 has an output coupled to a corresponding input of adder / scaler circuit 306I and a corresponding input of adder / scaler circuit 306Q, respectively. Adder / scaler 306I has an output coupled to an in-phase D / A (not shown) and adder / scaler 306Q has an output coupled to a quadrature D / A (not shown). Circuit 300 includes a clock input 310 coupled to the D / A sample clock, an up address output 312 coupled to a coefficient memory of the first part of stage 304, and a coefficient memory of the second part of stage 304. A common coefficient address generator 308 having a down address output 314 coupled to the. The first plurality of stages 304 is coupled to an up address bus 312 that is coupled to a coefficient address generator 308 that is clocked by a D / A clock. The coefficient address generator 308 is also coupled to a down address bus 314 that is coupled to the second plurality of stages 304. One inventive feature of the baseband shaping circuit 300 is that the same coefficients are used for each corresponding tap in the I and Q channels, so that the logic (eg, address generator and multiplexer) and coefficient memory are Take advantage of the fact that you can share on the Q channel.

  Referring now to FIG. 3D, each stage 304 of the baseband shaping circuit 300 of FIGS. 3A-3C includes a coefficient memory 320 coupled to a coefficient address generator 308 by an address bus 330. The coefficient memory 320 is coupled to the corresponding one of the up address bus 312 or the down address bus 314 by the address bus 330 as required. Coefficient memory 320 is coupled to coefficient memory output register 322, and coefficient memory output register 322 is coupled to a first input of multiplexer 236I and to a first input of multiplexer 326Q. The coefficient memory 320 is also coupled to a negative value circuit 324 (here, two's complement circuit), and the negative value of the coefficient memory output 322 is applied to the second input of the multiplexer 326I and the second input of the multiplexer 326Q. provide. Multiplexer 326I includes a select input 334I and an output 340I coupled to corresponding taps on delay line 302I (FIGS. 3A-3C). Multiplexer 326Q includes a select input 334Q and an output 340Q coupled to corresponding taps on delay line 302Q (FIGS. 3A-3C). In this embodiment of the shaping circuit 300, the address generator 308 uses the symmetry of the coefficients in reverse order to provide a symmetrically shaped waveform, thereby providing an up address output 312 (0 The coefficient memory 320 is addressed by supplying a decremented address, down address output 314 (starting from the maximum value and decrementing).

  Stage 304 operates in the same manner as stage 204 (described above in connection with FIG. 2E), with the addressed coefficient values and negative coefficient values clocked into the I and Q data streams by the D / A clock. With additional features offered at different rates.

  Referring now to FIGS. 4A-4D, an exemplary baseband shaping circuit 400 according to yet another aspect of the present invention provides an inventive coefficient storage technique. Circuit 400 includes an address bus and a plurality of multiplexer most significant bit (MSB) outputs coupled to a corresponding multiplexer (MSB) input of a plurality of coefficient memories 420a-420n (generally referred to as coefficient memory 420). A coefficient address generator 416 is provided. The outputs of the plurality of coefficient memories 420a-420n are coupled to a corresponding plurality of stages 418a-418n (each stage generally referred to as stage 418), each having an in-phase (I) output and a quadrature (Q) output. The in-phase (I) output is coupled to a corresponding stage of adders 450I, 452I whose output is coupled to a scale format converter 470I having an output coupled to an ID / A converter (not shown). The quadrature (Q) outputs are coupled to corresponding stages of adders 450Q, 452Q, whose outputs are coupled to a scale format converter 470Q having an output coupled to a Q D / A converter (not shown).

The coefficient address generator 416 includes a plurality of multiplexers 402 _{07 to} 402 ₃₄ (generally referred to as a multiplexer 402), and each multiplexer 402 has two-stage I channel input data (symbol) shift register 440 I and two-stage Q channel input data. (Symbol)-has I and Q inputs coupled to corresponding outputs with shift register 440Q. Two-stage shift registers 440I and 440Q are coupled in series and parallel, respectively, to provide I channel data and Q channel data clocked by a symbol clock and a D / A clock, respectively, as shown in FIG. 4C. Shift registers 442I, 444I, 442Q, and 444Q. The overall operation and signal flow of circuit 400 begins with I-channel shift register 440I and Q-channel shift register 440Q, respectively, in FIG. 4C. Eight individual registers 442Ia-442Ig, 442Qa-442Qg for each channel each represent eight taps of the delay line in the filter. The symbol data is clocked at the symbol clock rate and enters the “delay line”. There are multiple D / A clock cycles in each symbol clock cycle, where there are a minimum of 2 D / A clock cycles and a maximum of 64. The outputs of these registers 442 feed the multiplexer 402 in the address generator 416 of FIGS. 4A-4B and remain constant throughout the symbol period. The same coefficient memory 420 is used to generate I channel and Q channel coefficients during each D / A clock cycle. I channel coefficients are generated in the first half of the D / A clock cycle, and then Q channel coefficients are generated in the second half of the D / A clock cycle. Also, the outputs of these registers 422 provide inputs to the corresponding inputs of registers 444Ia-444Ig, 444Qa-444Qg (generally referred to as register 444). The output of register 444 provides outputs I0D-I7D, Q0D-Q7D as inputs to a digital logic circuit that implements the truth table shown in Table 2 that supplies SELI07-SELQ07, SELI16, SERQ16, etc. The I0D-I7D output signal and the Q0D-Q7D output signal are the I0-I7 signal and the Q0-Q7 signal delayed by one D / A clock cycle to provide the correct timing relationship for the output of the coefficient memory 420. is there.

Referring now to one of the four combined coefficient sets C0 and C7, during the first half of the D / A clock cycle, the I0 and I7 outputs of registers 442a, 442g are SELI / Q Depending on the state, it passes through multiplexer 402 ₀₇ to the input of XOR gate 404 ₀₇ . Similarly, also the second half period of the D / A clock cycle, Q0 output and Q7 output of the register 442 is selected, leading to XOR gate _{404 07} passes through the multiplexer _{402 07.} The output of the XOR gate 404 ₀₇ forms the most significant bit of the address to the coefficient memory, as described in Table 1 below. Referring now to the I channel, the XOR gate determines whether the symbol bits I0 and I7 have the same value. The same value means the same sign, positive or negative. If the symbol bits I0 and I7 have the same value, the coefficient value to be selected from the coefficient memory 420a is the I0 + I7 coefficient. If the symbol bits I0 and I7 have different values (opposite signs), the I0-I7 coefficient is selected. Next, the desired coefficient is accessed in the coefficient memory 420a, and the desired coefficient is stored in the register 430 at the rising edge of the D / A clock. A register 430 with rising clock edge storage and positive (digital “1”) enable (EN) is shown in FIG. 4A. The I coefficient is stored in register 430I when SELI / Q is high (first half of D / A clock cycle) and providing a rising clock edge. When SELI / Q is low (the second half of the D / A clock cycle) and is providing a falling clock edge (the clock and EN inputs to register 430Q are inverted), the Q factor is register 430Q. Is remembered. In this way, the I and Q coefficients are accessed in one D / A clock cycle.

信号４３４Ｉ ＳＥＬＩ０７が、以下の表２に記す真理値表を実施する論理によって生成される。信号４３４Ｉに応答して、マルチプレクサ４２６はレジスタ４３０の真の出力を現在のシンボルに対するサンプルの前半に対して供給する（例えば、シンボル毎に８個のＤ／Ａサンプルがある場合、前半はサンプル０、１、２、３であり、後半は４、５、６、７である）。マルチプレクサ４２６はサンプルの後半に対してレジスタ４３０の負の（２の補数の）出力４２４を供給する。ＸＯＲゲート４０４_０７の出力に依存して、係数メモリ４２０は係数値Ｉ０＋Ｉ７又はＩ０−Ｉ７を提供する。次いで、信号４３４Ｉ ＳＥＬＩ０７が、２つの残りの係数の組み合わせ、即ち−（Ｉ０＋Ｉ７）又は（Ｉ７−Ｉ０）を選択的に提供する。アドレス・カウンタ最上位ビット（ＡＣＣＭＳＢ）信号は、シンボルの前半のサンプルから後半のサンプルに遷移するときに２値デジタル論理「１」から「０」に変化する。該出力はレジスタ４３２に記憶され、レジスタ４３２は係数値を図４Ｄの一連の加算器４６０への入力として提供する。

Signal 434I SELI07 is generated by logic that implements the truth table set forth in Table 2 below. In response to signal 434I, multiplexer 426 provides the true output of register 430 for the first half of the samples for the current symbol (eg, if there are 8 D / A samples per symbol, the first half is sample 0). , 1, 2, 3 and the second half is 4, 5, 6, 7). Multiplexer 426 provides the negative (2's complement) output 424 of register 430 for the second half of the sample. Depending on the output of the XOR gate 404 ₀₇ , the coefficient memory 420 provides a coefficient value I0 + I7 or I0-I7. Signal 434I SELI07 then selectively provides a combination of the two remaining coefficients, ie,-(I0 + I7) or (I7-I0). The address counter most significant bit (ACCMSB) signal changes from binary digital logic “1” to “0” when transitioning from the first half sample of the symbol to the second half sample. The output is stored in register 432, which provides the coefficient value as input to the series of adders 460 of FIG. 4D.

  Note that because symmetric coefficient pairs are combined in the programming of coefficient memory 420, only four inputs are added to each channel even when there are eight taps in the filter. A further point to note about the address generator 416 is that the address generator 416 always counts up to the same “rollover” point in binary with a 6-bit count (6 bits count from 0 to 63). And then go back to 0 and start again). The increment of the count stored in register 406 is changed based on the number of D / A samples per symbol (eg, if 8 samples per symbol are desired, the number 8 is stored in register 406, If 4 samples per symbol are desired, the number 16 is stored in register 406).

Each of the multiplexers 402 has two outputs coupled to the two inputs of an exclusive OR (XOR) gate 404, and the output of the logic gate 404 is connected to the multiplexer (MSB) input of the corresponding coefficient memory 420. Combined. The coefficient address generator 416 further comprises a register 406 coupled to the modulator control / status bus and having an output coupled to the input of a multi-bit adder 408 (here 6-bit adder). Adder 408 has an output coupled to register 410, which has a clock input coupled to the D / A clock. Register 410 has a first output that is the sum generated by the adder, and each of its lower bits (here lower 5 bits) is coupled to a first input of XOR gate array 412. Register 410 has a second output that is the most significant bit generated by adder 408 and is coupled to the second input of XOR gate array 412 and the second input of adder 408. XOR gate array 412 has a multi-bit output coupled to the address bus input of the corresponding coefficient memory 420. Each lower bit in the output of the adder 408 is exclusive ORed with the most significant bit generated by the adder 408. Equivalent to Table 1, XOR gate array 412 translates the address to a corresponding new address, which is combined with the output of, for example, XOR gate 404 ₀₇ to provide a memory address that addresses coefficient memory 420. To do.

  Each stage 418, similar to stage 304 (FIGS. 3A-3C), includes a pair of registers 430I, 430Q, each register being a coefficient input coupled to a corresponding coefficient memory 420, a clock coupled to a D / A clock. An input and an enable input coupled to the SELIQ. The clock input to register 430Q is inverted by inverter 427. Each of the pair of registers 430I, 430Q has an output coupled to a first input of each of multiplexer 426I and multiplexer 426Q. The outputs of registers 430I and 430Q are also coupled to a negative value circuit 424 (here, two's complement circuit), and the negative value of the coefficient in registers 430I and 430Q is sent to the second input of each of multiplexer 426I and multiplexer 426Q. Provided as output. Multiplexer 426I has a select input 434I coupled to the SELI / Q XY signal and has a COEFF IXY output. Each multiplexer 426Q includes a select input 434Q and a COEFF Q XY output coupled to the SELI / Q XY signal.

  The register 414 of the coefficient address generator 416 has an input coupled to the most significant bit generated by the adder 408 and a clock input coupled to the D / A clock, and the signal ACCMBD (related to Table 2). The truth table is provided to provide logic to implement the SELI / Q XY signal.

  The first adder stage 450I includes a plurality of adders 460 having a pair of inputs coupled to the corresponding COEFF I / Q XY output pair from stage 418 and an output coupled to the pipeline register 462. Prepare. Register 462 has an output coupled to the input of adder 460 in second adder stage 452I. Those skilled in the art will appreciate that the number and configuration of adder stages 450I, 452I can be provided in several equivalent configurations.

  Similarly, the first adder stage 450Q also has a plurality of additions having a pair of inputs coupled to the corresponding COEFF I / Q XY output pair from stage 418 and an output coupled to pipeline register 462. A container 460. Register 462 has an output coupled to the input of adder 460 in second adder stage 452Q. Those skilled in the art will appreciate that the number and configuration of adder stages 450Q, 452Q can be provided in several equivalent configurations. After the adder stages 450I, 452I, 450Q, 452Q add the pipelined coefficient values, each scale format converter 470I, 470Q scales and formats the waveform output samples for D / A conversion.

  Further improvements in reducing coefficient storage requirements are achieved by adding some complexity to the circuit 400. For example, in one embodiment having 8 coefficients corresponding to 8 filter taps, the circuit 400 may have a symmetry of coefficients (ie, the same set of coefficients is C0 and C7, C1 and C6, C2 and C5, Used for C3 and C4). Note that some coefficients are accessed in reverse order to provide the back of the filter waveform. By further combining coefficient pairs by storing sums and differences in coefficient memory 420 rather than individual coefficients, the coefficient storage requirement can be halved and additional adder stages can be eliminated. Table 1 shows this coefficient storage technique for 16 coefficient values for each of the 8 filter tap coefficients.

  In operation, the coefficient memory address is generated by a coefficient address generator 416 that operates as a counter that counts the desired number of D / A samples per symbol (up to a maximum of 64, where 64 is equal to the size of the coefficient memory 420). Generated. The increment of the count varies based on the number of samples per symbol divided by the maximum number 64. Register 406 is loaded with the selected increment. Thus, for a given transmission rate that generates D / A samples at a rate of 16 samples per symbol, the counter increments by 4 in each D / A clock cycle, thereby causing 4 in the coefficient memory 420. Use each coefficient value. The address counter is implemented as an adder / accumulator and the increment is provided as an input to the accumulator and the accumulated “sum” forms the actual address for the coefficient memory 420. Baseband shaping circuit 400 supports more than one transmission rate related to power consumption. The transmission rate can be selected by a combination of a selectable frequency of the D / A clock and an increment value programmed in the register 406.

  Sum and difference waveform values represented by positive coefficient values (also called true values) and two's complement (negative) coefficient values are clocked by the filter shift register 442 (symbol clock instead of D / A clock). The value of the data symbol in the 8 taps of the controlled register) and the current count of the number of D / A samples (ie, if there are 64 samples per symbol, which of the 64 samples Is currently selected) by the multiplexer 426.

  In operation, the baseband shaping circuit 400 uses symbol data bits as positive or negative multipliers (ie, data symbol bits “1” = + 1, data symbol bits “0” = − 1). Then, the sign of the coefficient of each tap (eight taps in this case) of the filter is changed. For a given set of coefficient pairs (ie, two taps from the filter, eg, C0 and C7), when multiplying by symbol bits, the following equations: C0 + C7, C0-C7, C7-C0 and C0− One of C7 is formed. Since -C0-C7 =-(C0 + C7) and C7-C0 =-(C0-C7), the ability to take the negative value of the coefficient (here 2's complement) according to the present invention gives two quantities ( Only C0 + C7 and C0-C7) need to be stored in the memory. The determination of when the coefficient value should be negated is determined by the two data bits from the tapped delay line (here, the two-stage I / Q channel input data (symbol) shift register 440) and the most significant bit of the coefficient address generator 416. And based on. This is because this most significant bit indicates the necessity of reverse pairing shown in the new pairing column of Table 1.

  The coefficient address generator 416 is a means of advancing the coefficient memory in 1, 2, 4, 8, 16 or 32 increments corresponding to 64, 32, 16, 8, 4, 2 D / A samples per symbol. provide. The most significant bit (MSB) of address counter adder 408 is used to invert the remaining counter address output bits of XOR array 412 utilizing the symmetry of the coefficients found in the center symbol (ie, If it is necessary to generate 16 D / A samples per symbol, the first 8 coefficients are referenced to the center symbol as seen with reference to the new pairing column in Table 1. As the last 8 mirror images).

Signal MSB07 is the output from XOR gate _{404 07,} and two taps (C0 filter shift register 442 combined to work for a given coefficient memory C7, C1 and C6, C2 and C5, C3 and C4) (here, for example C0 and C7) is simply a XOR of the two data symbol bits. This XOR output indicates whether the bits are the same or different. If the bits are the same, this means that the coefficient to be used is C0 + C7 or-(C0 + C7). If the bits are different, this means that the coefficient to be used is C0-C7 or-(C0-C7) (note that only C0 + C7 and C0-C7 are actually stored in memory and these coefficient values Negative form is created using digital logic).

  The truth table shown in Table 2 and implemented in the FPGA of the circuit 400 provides the SELI / Q XY signal. However, I / Q indicates which register 430I or 430Q receives a coefficient value, and XY indicates a coefficient pair.

真理値表である表２は、アドレス・カウンタ（加算器／累算器）の最上位ビットと２つのデータ・シンボル・ビットとの間の論理関係を含み、加算器段４５０、４５２に出力として提供されるのが係数メモリ値の正の値であるか、負の値であるか（即ち、Ｃ０＋Ｃ７又は−（Ｃ０＋Ｃ７））を求めるＳＥＬＩ／Ｑ ＸＹ信号（例えば、ＳＥＬＩ０７、ＳＥＬＱ０７）を生成する。

Table 2, the truth table, contains the logical relationship between the most significant bit of the address counter (adder / accumulator) and the two data symbol bits, and is output as an output to adder stages 450, 452. A SELI / Q XY signal (eg, SELI07, SELQ07) is generated that determines whether a positive or negative coefficient memory value is provided (ie, C0 + C7 or-(C0 + C7)).

  In certain embodiments, mathematical processing of a given input symbol depends on the speed of the device family (eg, FPGA device or ASIC device) used to implement the baseband shaping circuit 400 and the desired transmission rate. Cannot be executed in one system clock cycle (ie, the symbol data input to the first D / A sample protrudes), the process is divided into multiple steps each executed in one clock cycle. Divided. The implementation is then “pipelined” and a register 462 is placed at the output of each processing step to resynchronize the output to the system clock. This results in a fixed delay or latency between the input symbol and the first output D / A sample at the beginning of the transmission burst, while all other D / A samples are similarly pipelined input data. (Symbol) • Sequentially in successive clock cycles provided by shift registers 440I, 440Q.

  For clarity, Table 1 represents only the pairing of the C0 and C7 coefficient sets. Similar pairings exist for the remaining coefficient sets C1 and C6, C2 and C5, and C3 and C4. For example, replacing C0 with C1 and replacing C7 with C6 provides a pairing table of coefficient pairs for C1 and C6, and so on. For a given set of coefficient pairs, when multiplied by a symbol bit, the adder forms one of the following equations: C0 + C7, C0-C7, C7-C0 or -C0-C7.

  Furthermore, because -C0-C7 =-(C0 + C7) and C7-C0 =-(C0-C7), there are two expressions that need to be stored in a memory that has the ability to provide negative values: For example, only (C0 + C7) and (C0-C7). Here, the determination of when to negate the coefficient value using the negative value circuit 424 is based on the two data bits from the tapped delay line and the most significant bit of the base address generator. This is because the most significant bit indicates the necessity of reverse pairing shown in the new pairing column of Table 1.

As shown in Table 1, each coefficient, eg C0, includes a set of coefficient values C0 ₀ -C0 _n , where n is equal to the number of samples provided at the D / A clock rate in a given symbol period. . The values in Table 1 are provided for the case of n = 15 providing 16 samples per symbol period.

  When data symbols are input to input data (symbol) shift registers 440I, 440Q, circuit 400 provides up to 64 discrete samples per symbol. Note that Table 1 provides an example with 16 samples per symbol for clarity. The pairing column in Table 1 represents the values used from the two coefficients C0, C7 to generate any of the 16 discrete output samples. There are similar pairings of C1 and C6, C2 and C5, and C3 and C4. The symmetry column in Table 1 shows the symmetry of the coefficients for C0 and C7. The same symmetry applies to C1 and C6, C2 and C5, and C3 and C4. The new pairing column in Table 1 replaces the C7 value with the C0 value and converts the coefficient values into a single set of 16 values (in this case the C0 value). The same pairing applies to C1 and C6, C2 and C5, and C3 and C4. The new address column in Table 1 is repeated in the first column based on the new pairing because the coefficient values in the new pairing column are repeated (ie, each pairing is used twice). Indicates that the first required address range shown is halved.

  The memory address column and the memory content column in Table 1 represent the physical address scheme implemented in circuit 400 and two of the four possible combinations of coefficient values (C0x + C0y or C0x-C0y). Represents the contents of the provided memory. The remaining two possible values are obtained by taking negative values, here for example 2's complement (-C0x-C0y or -C0x + C07).

  The logic shown in the truth table of Table 2 represents a look-up table and coefficient value implementation based on the memory address column and the memory content column of Table 1. In Table 2, ACCMSBD represents the output signal of register 414, I / Q XD represents the corresponding output of shift register 444I of two-stage I-channel input data (symbol) shift register 440I, and I / Q YD is Represents the corresponding output of the shift register 444Q of the two stage I channel input data (symbol) shift register 440Q The logic in the truth table includes a combination of I channel and Q channel lookups in a single set of four coefficient tables instead of one each (ie, the coefficient memory is time-shared between the two channels). ) After the coefficient address generator 416 counts to the middle range value (in Table 1, the middle range is 8 counting from 0 to 7), the XOR array 412 of the coefficient address generator 416 counts the most significant bits and the current address count. And an exclusive OR operation is performed, and then the address is counted in reverse. This is because only 32 values (8 values in Table 1) are required for each coefficient. 5 bits in circuit 400 designed to have 64 samples per symbol bit (3 bits in the example of Table 1 were designed to have 16 samples per symbol bit) The additional bits coupled to are control bits that select the desired pair of coefficient values (ie, C0x + C0y or C0x-C0y) from memory based on whether the data symbol for I0 is the same as or different from I7. Represent. If the I0 data symbol is the same as I7, C0x + C0y is selected, and if the I0 data symbol is different from I7, C0x-C0y is selected. The SELI07 or SERQ07 determined by the truth table logic of Table 2 is then used to select positive or negative coefficient values for the I channel or Q channel. Baseband bit shaping techniques can also be used for digital low-pass filters with symmetric coefficients.

  All publications and references cited herein are each expressly incorporated herein by reference in their entirety. Having described preferred embodiments of the invention, it will be apparent to those skilled in the art that other embodiments incorporating the concepts of the preferred embodiments may also be used. Accordingly, these embodiments should not be limited to the disclosed embodiments, but should be limited only by the spirit and scope of the appended claims.

1 is a block diagram of a data path processing circuit for QPSK modulation according to the present invention. FIG. 1 is a schematic diagram of a baseband shaping circuit according to the present invention. 1 is a schematic diagram of a baseband shaping circuit according to the present invention. 1 is a schematic diagram of a baseband shaping circuit according to the present invention. 1 is a schematic diagram of a baseband shaping circuit according to the present invention. 2B is a schematic diagram of one stage of the baseband shaping circuit of FIGS. 2A to 2D. FIG. FIG. 6 is a schematic diagram of a baseband shaping circuit according to a further aspect of the present invention. FIG. 6 is a schematic diagram of a baseband shaping circuit according to a further aspect of the present invention. FIG. 6 is a schematic diagram of a baseband shaping circuit according to a further aspect of the present invention. FIG. 4 is a schematic diagram of one stage of the baseband shaping circuit of FIG. 3. FIG. 6 is a schematic diagram of a baseband shaping circuit according to yet another aspect of the present invention. FIG. 6 is a schematic diagram of a baseband shaping circuit according to yet another aspect of the present invention. FIG. 6 is a schematic diagram of a baseband shaping circuit according to yet another aspect of the present invention. FIG. 6 is a schematic diagram of a baseband shaping circuit according to yet another aspect of the present invention.

Claims (23)

A method of shaping a baseband signal,
Providing a plurality of coefficient memories each having a plurality of coefficient values representing filter response waveform values;
Determining a coefficient memory address for each of the coefficient memories;
Addressing each of the plurality of coefficient memories;
Retrieving the addressed coefficient value from each of the plurality of coefficient memories;
Providing a negative value for each of the retrieved coefficient values of the plurality of coefficient values;
Selecting one of the retrieved coefficient value and the negative value in response to the baseband signal; and
Summing the values selected from each coefficient memory to provide a shaped signal;
Including methods.   The method of claim 1, further comprising sharing the plurality of coefficient memories to shape an in-phase baseband signal and a quadrature baseband signal. Sharing the plurality of memories includes
Retrieving one of the coefficient values corresponding to the in-phase baseband signal at a first edge of a clock signal; and
Retrieving one of the coefficient values corresponding to the orthogonal baseband signal at a different second edge of the clock signal;
The method of claim 2 comprising:   4. The method of claim 3, wherein the clock signal comprises a digital / analog converter clock signal. Determining the coefficient memory address is
Determining an increment that provides a predetermined number of samples for each of a plurality of symbols comprising the baseband signal; and
Incrementing an address counter in response to the predetermined number of samples of each symbol and a predetermined coefficient memory size;
The method of claim 1 comprising: The baseband signal includes an in-phase signal and a quadrature signal,
Selecting the coefficient value includes selecting an in-phase value in response to the in-phase signal and selecting an orthogonal value in response to the quadrature signal;
Summing the selected values includes summing the in-phase values selected from each coefficient memory to provide a shaped in-phase signal, and summing the quadrature values selected from each coefficient memory The method of claim 1 including providing a shaped quadrature signal.   The method of claim 1, wherein the negative value comprises at least one of a two's complement value, an offset binary value, and a signed amplitude value.   The method of claim 1, wherein providing a plurality of coefficient memories includes combining at least two filter coefficients to form the plurality of coefficient values such that coefficient memory storage capacity is minimized.   The method of claim 1, wherein providing a plurality of coefficient memories further comprises providing a coefficient memory corresponding to a plurality of roll-off factors.   The method of claim 1, wherein the plurality of coefficient memories further includes one of a sum and a difference of a first filter response value and a second filter response value.   The method of claim 10, wherein the first filter response and the second filter response are symmetric. Searching for coefficient values
Providing an address counter having a plurality of logic outputs for addressing the coefficient memory; and
Determining whether to search for the sum or the difference in response to a logic output selected from the logic outputs;
The method of claim 10 comprising: A logic having a first input coupled to the logic output of the address counter, a second input coupled to the in-phase data symbol bits, and a third input coupled to the quadrature data symbol bits Providing a circuit; and
Determining whether to select the retrieved value or the negative value in response to the output of the logic circuit;
The method of claim 12, further comprising: Summing the selected values is
Providing a plurality of adder stages, each coupled to a pipeline register;
Clocking the pipeline register at a digital / analog converter (D / A) rate; and
Scaling and formatting the sum after the final adder stage;
The method of claim 10 comprising:   The baseband signal is clocked at the symbol rate such that the number of searches per coefficient is equal to the digital / analog (D / A) rate divided by the symbol rate, and the search for the coefficient is the D / 11. The method of claim 10, wherein the method is clocked at an A rate.   The method of claim 10, wherein the filter waveform comprises a raised cosine.   The method of claim 10, wherein the filter waveform comprises a square root raised cosine. A method of shaping a baseband signal,
Providing a plurality of digital words each indicating a coefficient value at a certain moment;
In response to the baseband signal, selecting one of the digital word and a corresponding negative value of the digital word; and
Summing the selected digital words to provide a baseband shaped signal;
Including methods.   The method of claim 18, wherein providing a plurality of digital words includes combining at least two filter coefficients to form the plurality of coefficient values such that the storage capacity of the coefficient memory is minimized. A plurality of coefficient memories each having an input address bus, a multiplexer input, and a coefficient value output;
A plurality of first registers each having an input and a digital / analog (D / A) clock input and output coupled to each one of the coefficient value outputs;
A plurality of negative value circuits each having an input and an output coupled to a respective one of the outputs of the first register;
A plurality of inputs each having a first input coupled to a respective one of the outputs of the first register and a second input coupled to a respective one of the outputs of the plurality of negative value circuits; A 2: 1 multiplexer,
A plurality of second registers each having an input coupled to a respective one of the outputs of the plurality of 2: 1 multiplexers and a digital / analog (D / A) clock input and output;
An adder having a plurality of inputs coupled to each one of the plurality of second registers;
A device comprising:   21. The device of claim 20, wherein each of the plurality of negative value circuits comprises at least one of two's complement logic elements, offset binary logic elements, and signed amplitude logic elements.   21. The device of claim 20, further comprising a coefficient address generator having an output coupled to an input address bus of a coefficient memory, the input address having a plurality of address lines. The coefficient address generator is
An adder having a plurality of address output lines;
An address register coupled to the plurality of address output lines and having a clocked address line output and an address counter most significant bit output;
An address input coupled to the clocked address line output; an address counter most significant bit input coupled to the address counter most significant bit output; and a plurality of address lines of the coefficient memory address bus. An exclusive OR gate (XOR) array having outputs coupled to corresponding address lines therein,
An XOR multiplexer having an input coupled to a pair of baseband bit signals and an output coupled to one of the plurality of address lines of the coefficient memory address bus;
23. The device of claim 22, further comprising:

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