JP2005509315A - High frequency VCXO structure - Google Patents

Abstract

  A frequency adjustable oscillator adapted for digital signal clock synchronization, a crystal oscillator circuit having a voltage variable control input for generating a drive signal and adjusting a frequency of the drive signal, and a phase detector circuit for generating a phase offset signal A filter that operates based on the phase offset signal and generates a VCO control signal; and a voltage controlled oscillator circuit that is operatively coupled to the filter and generates an analog control frequency signal in response to the VCO control signal; A frequency divider circuit operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generating a reduced frequency feedback signal in response to the control frequency signal. The frequency tunable oscillator further comprises a double sided package including the pedestal having a central portion and the outer portion having sidewalls extending substantially above and substantially downward from the outer portion of the pedestal. Prepare. The upwardly extending side wall and the pedestal form a first cavity adapted to receive and electrically connect the crystal resonator. The downwardly extending side wall and the pedestal receive at least one electronic component and form a second cavity adapted to be electrically connected. A cover is coupled to the first cavity to define an independent environment for housing the crystal resonator.

Description

  The present invention relates to a US patent application with application number 09 / 829,129, filed April 9, 2001 entitled "Controllable Crystal Oscillator", and more particularly to a voltage controlled crystal oscillator, particularly a relatively high frequency voltage. The present invention relates to a low cost circuit configuration for a controlled crystal oscillator.

  Large capacity data networks require signal repeaters and sensitive receivers for low error data transmission. For decoding and / or unambiguous transmission of serial data signals, such network elements include elements that generate data timing signals having the same phase and frequency as the data signals. This step of generating the timing signal is referred to as “clock recovery”.

Data clock recovery requires a relatively accurate reference signal that serves as a starting point to match the clock rate of the serial data signal and a circuit for frequency adjustment. The type of technology, cost, and quality used to generate a high-precision reference signal will vary depending on the class of network application. For stationary large installations, an “atomic” clock may serve as the best reference signal source. In the case of remote or mobile systems, elements including specially configured quartz resonators have been used. As communication network technology has evolved to provide higher bandwidth interconnections to local area networks and computer workstations, the need for smaller and cheaper clock recovery technology solutions has increased.
US Pat. No. 5,987,085

  In many clock recovery applications, the reference signal generator needs to be adjustable, i.e., controllable, and operate with a precisely defined operating curve. This tunability requirement has been defined as a frequency control range (APR / Absolute Pull Range). APR is as a controllable frequency deviation (described in ± ppm) from the nominal frequency (F0) over a wide range of operating parameters including frequency tolerance, frequency stability, supply voltage, output load, and time (aging). It is prescribed. Clock recovery may require a controllable oscillator with both maximum and minimum APR.

  For higher frequency applications currently required, eg, 500 MHz and above, more conventional resonator technologies such as standard AT cut crystals do not work perfectly. The recognized upper limit of the fundamental mode of a straight blank AT cut crystal is 70 MHz. It is therefore necessary to employ some form of frequency multiplication in order to generate a higher frequency reference signal than is required. Frequency multiplication increases circuit sensitivity to phase noise, jitter, nonlinearity, and long-term stability.

  Alternatives to standard quartz / crystal resonators include the use of surface acoustic wave (SAW) resonators and special crystal blank configurations such as inverted mesas. These alternatives result in more complex manufacturing processes and thus higher costs.

  An approach to reducing the cost of the data signal clock recovery element is described in US Pat. No. 5,987,085 to Anderson. The Anderson patent describes a clock recovery circuit that was developed to eliminate the need for a crystal-based reference clock. However, the Anderson patent does not specify a target frequency and does not provide operational data.

  What is needed is a low cost voltage controlled crystal oscillator that is compatible with data signal clock recovery applications. In particular, it is desirable to provide a high frequency voltage controlled oscillator utilizing a conventional crystal resonator.

  A controllable oscillator is provided that is adapted for use in clock synchronization of digital signals. The oscillator includes a crystal oscillator circuit that generates a drive signal, a phase detector circuit, a low-pass loop filter, a voltage controlled oscillator (VCO) circuit, a divider circuit, and a sine wave-to-logic level converter circuit.

  The crystal oscillator circuit has a voltage variable control input for generating a drive signal and adjusting the frequency of the drive signal. The crystal oscillator circuit further includes a voltage variable capacitive element, such as a discrete varactor responsive to the control input, an AT cut crystal resonator operatively coupled to the varactor, and a gain stage that energizes the discrete varactor. .

  The phase detector subcircuit is configured to generate a phase offset signal. The loop filter operates to generate a control voltage that is received by a voltage controlled oscillator (VCO) subcircuit based on the phase offset signal. A voltage controlled oscillator (VCO) circuit is operatively coupled to the loop filter and generates an analog control frequency signal in response to the control voltage.

  The divider circuit has a pre-selectable divider ratio and is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit. The divider generates a reduced frequency feedback signal in response to the control frequency signal. The phase detector circuit changes the phase offset signal in response to the phase difference between the feedback signal and the drive signal in response to the feedback signal and the drive signal.

  The oscillator is also a sine wave-to-logic level converter that is operatively coupled to a voltage controlled oscillator (VCO) to produce a digital (or logic level) output signal having substantially the same frequency as the control frequency signal. Includes subcircuits.

In a preferred embodiment, the AT cut resonator is configured to resonate at a fundamental mode of about 19.44 megahertz, and the divider sub-circuit has a preselected divide ratio of about 32: 1, The oscillator operates within the region defined between the following two equations for V _control values in the range of about 0.15 volts to about 3.15 volts, with V _control being the DC voltage level of the voltage variable input: Indicates the frequency.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz

  Embodiments of the packaged oscillator of the present invention further comprise the pedestal comprising a central portion and the outer portion having sidewalls extending substantially upward and substantially downward from the outer portion of the pedestal. Has a double-sided package that includes. The upwardly extending side wall and pedestal form a first cavity configured to receive and electrically connect the crystal resonator. The downwardly extending side wall and pedestal form a second cavity that houses and electrically connects at least one electronic component. A cover is combined with the first cavity to define an airtight environment in which the crystal resonator is accommodated.

  The packaged oscillator includes a laminated substrate combined with a second cavity. The base of the package has the second cavity surface on which at least one electronic component is mounted on the second cavity surface. The multilayer substrate cover has a cavity facing surface that houses at least one electronic component, and an outer facing surface that includes terminals that facilitate surface mounting.

  Another embodiment of the invention is a frequency tunable oscillator with reduced temperature dependence. A frequency tunable oscillator includes a phase detector circuit that generates a phase offset signal, a loop filter that operates based on the phase offset signal and generates a VCO control signal, and is operatively coupled to the filter to provide a VCO control signal. A voltage-controlled oscillator circuit that generates an analog controlled frequency signal in response to and a feedback signal of reduced frequency in response to the controlled frequency signal operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit And a frequency divider circuit for generating

  The phase detector circuit changes the phase offset signal in response to the phase difference between the feedback signal and the drive signal in response to the feedback signal and the drive signal. The drive signal is generated by a crystal resonator operatively coupled to the resonator gain stage and the variable capacitance circuit. The variable capacitance circuit is coupled to the temperature compensation logic, the temperature sensor, and the control input. The temperature compensation logic generates capacitance adjustments in response to temperature changes and suppresses frequency changes caused by temperature. Through the variable capacitance circuit, the control input causes a change in the capacitive load of the resonator in order to provide accurate external control of the drive frequency.

  There are other advantages and features of the present invention as will become more apparent from the following description of the preferred embodiment of the invention, the drawings, and the appended claims.

  While the invention will vary from many different forms of embodiments, the specification and the accompanying drawings describe only the preferred forms of the invention. However, the invention is not limited to the embodiments so described. The scope of the present invention is specified by the appended claims.

  In the drawings, a single block or cell may represent a number of individual elements and / or circuits that collectively perform a single function. Similarly, a single line may indicate several signal or energy transfer paths for performing a particular operation.

  Referring to FIG. 1, a frequency controllable oscillator 10 includes a crystal oscillator circuit 12, a phase detector 14, a loop filter 16, a voltage controlled oscillator (VCO) circuit 18, a frequency divider circuit 20, and a sine wave-logic level. It has a converter circuit 22.

  Crystal oscillator circuit 10 includes a crystal resonator 24 operatively coupled to a gain stage element 26 and a variable capacitance element 28. What is referred to by the names Pierce, Colpitts, Hartley, Clap, Driscoll, Sailer, Butler, and Miller Various crystal oscillator circuit configurations can be used, including Colpitts at present. The voltage variable capacitance element 28 changes the capacitance in response to the change of the DC voltage variable control input 30. The voltage change applied to the input 30 adjusts the capacitive load of the oscillator circuit and the frequency of the output drive signal indicated by 32 in FIG.

  The input 30 is preferably voltage variable. Another possible control input is a digital number (or equivalent) input that is converted to an analog voltage signal by a known digital-analog converter.

  The voltage variable capacitance element 28 is preferably a discrete variable capacitance diode (ie, a varactor or a varactor diode), although other voltage controlled variable capacitance mechanisms are contemplated. In embodiments with increased integration on the chip, the variable capacitance element 28 is configured in parallel and is switchable with one or more transistors coupled to the control logic to selectively drive the capacitor in response to the control voltage. Includes one or more banks of sensitive capacitors. Alternatively, the variable capacitance element 28 selectively drives a transistor-switchable chip-mounted varactor element or one or more banks of a combination of capacitors and a varactor integrated in response to a control voltage and a capacitor. Control logic. A circuit providing a chip-mounted variable capacitance compatible with a temperature compensated crystal oscillator is disclosed in US Pat. No. 4,827,226 issued to Cornell et al., Hereby incorporated by reference as long as it is not inconsistent with the present invention. And U.S. Pat. No. 5,994,970 issued to Cole et al.

  The quartz resonator 24 is preferably a low cost AT configured to resonate in a fundamental mode with a frequency in the range of about 19.44194 MHz to about 20.828 MHz for loads in the range of about 6 picofarads to about 14 picofarads. Cut crystal. Crystals configured to resonate at about 19.44 MHz or about 20.828 MHz for a load of 10 picofarads each are preferred. A crystal adapted to a relatively low capacitive load is preferred in order to allow a wide range of frequency control.

  The drive signal 32 is received by the phase detector (or phase comparator) circuit 14 and compared with the reduced frequency feedback 34 signal from the divider circuit 20. The phase detector 14 generates a phase offset signal 36 having a DC voltage level that is proportional to the phase difference between the reduced frequency feedback signal 34 and the drive signal 32.

  More specifically, the phase detector 14 includes circuitry that generates a pulse that is proportional to the phase difference between the reduced frequency feedback signal 34 and the drive signal 32. This pulse is integrated by a charge pump (not shown separately) and converted into a corresponding DC voltage variable signal for controlling the voltage controlled oscillator (VCO) 18. A variety of phase detector circuit configurations are compatible with the present invention. An exemplary phase detector circuit and configuration details can be found in “Monolithic Phase-Locked Loop and Clock Recovery Circuit: Theory and Design Bezad Razavic Edit 1996” (Monolithic Phase-Locked Loop & Clock Recovery Circuits: Theory and Design). Rasatic ed., IEEE (1996)).

  A preferred phase detector circuit employs a flip-flop configured as a “digital phase / frequency detector” or “digital tri-state comparator”. This configuration has two D flip-flops whose outputs are connected to NAND gates, and the NAND is connected to the reset of each flip-flop. The output of the flip-flop is also connected to the input of the charge pump. The output signal of each flip-flop is a series of pulses with a frequency related to the input frequency of the flip-flop. When the inputs of both flip-flops are the same, the signal is synchronized in both frequency and phase. If they are different, they provide a signal to the charge pump that will charge or discharge the loop filter, or put the charge pump in a high impedance state, thereby maintaining the charge of the loop filter. Is done.

  The charge pump (not shown separately) has two transistors, one charging the loop filter 16 and one discharging the loop filter 16. The input of the charge pump is the output of the flip-flop described above. When both amplifier inputs are low, the amplifier transitions to a high impedance state, thereby maintaining the loop filter charge.

  The oscillator 10 is operatively coupled between a phase detector 14 and a voltage controlled oscillator (VCO) 18 and has a loop filter 16 for removing high frequency components from the VCO control signal.

  The voltage controlled oscillator (VCO) 18 outputs an analog control frequency signal 40 in response to changes in the DC voltage level of the filtered VCO control signal 38. Loop filter 16 accumulates the pulses received from phase detector 14 and serves to generate a control voltage for VCO control signal 38. A variety of circuit configurations are suitable for providing a VCO. Details of an exemplary high frequency adaptive VCO circuit and configuration can be found in "RF Circuit Design, Theory and Applications / Ludich. R, P. Brecco, Prentice Hall 2000" (RF Circuit Design, Theory and Applications, Ludwig, R. and P. Bretchko, Prentice Hall (2000)). Presently preferred is a tuned differential amplifier where the base and collector are cross-connected to provide positive feedback and a 360 degree phase shift. This tuning subcircuit has a tank circuit 42 located in the collector and providing an internal varactor and preferably an external inductance. The external tank circuit 42 also applies a DC bias to the VCO. Preferred here is the configuration of the internal varactor diode so that the VCO control input is inversely correlated with the output frequency.

  The analog control frequency signal 40 passes through the frequency divider subcircuit 20 before being compared with the phase / frequency drive signal 32. Divider 20 generates a corresponding reduced frequency feedback signal 34. The frequency divider 20 enables the phase detector 14 to operate with an oscillation signal having a frequency in the range of the fundamental mode frequency of the crystal resonator 24.

  Although various circuit configurations are suitable for providing the divider 20, the preferred divider circuit configuration uses a series of flip-flops with logic select inputs to preselect the divider ratio.

  The oscillator 10 preferably includes a converter sub-circuit 22 that converts an analog (ie, sinusoidal) control frequency signal 40 into a digital (or logic level) output signal 44. The converter subcircuit 22 is preferably a differential receiver that provides a digital output signal at a voltage level that conforms to positive reference emitter coupling logic (PECL), also referred to as 10K or 100K positive emitter coupling logic (PECL). Differential ECL driver). Transistor-to-transistor logic, emitter coupled logic, CMOS, MOSFET, GaAs field effect, MESFET, HEMT, or between voltage levels according to semiconductor circuit technology selected from the group essentially including PHEMT, CML, and LVDS Other digital logic level output standards are possible, including oscillating signals.

  The contour line identified by reference numeral 46 in FIG. 1 indicates which circuit elements are preferably integrated in a single semiconductor chip module. Preferably, what is not mounted on the chip are the crystal resonator 24, the voltage variable capacitor 28, the loop filter 16, and the circuit elements of the VCO tank circuit 42. The circuit elements of the sine wave-to-logic level converter 22 are implemented using integrated circuit semiconductor technology (i.e., a chip), but the converter 22 can be used to set standard digital outputs, Separated from module 46 to provide greater flexibility in changing the supply voltage.

  The controllable oscillator of the present invention is particularly adapted for operation at relatively high frequencies. For example, the circuit of FIG. 1 has a frequency control range (APR) of at least ± 50 ppm and an output of less than about 5 picoseconds at nominal operating frequencies of 622.08, 644.531, 666.514, and 666.326 megahertz. It is particularly adapted to provide an oscillator that exhibits RMS phase jitter.

  The frequency control range (APR) is controllable (in ± ppm) from the nominal frequency (F0) over a wide range of operating parameters including frequency tolerance, frequency stability, supply voltage, output load, temperature, and time (aging). Defined as frequency deviation). Controllability of output frequency exposed to a range of temperatures is an important aspect of the APR specification. In the APR setting, -40 to 80 degrees Celsius is the accepted temperature range for temperature sensitivity tests.

EXAMPLE A batch of controllable crystal oscillator 110 was made according to an example of the present invention. A simplified circuit overview of the fabricated sample is shown in FIG.

  FIG. 2 shows the following sub-circuits: crystal oscillator 112, phase detector 114, loop filter 116, voltage controlled oscillator (VCO) 118, divider 120, and sine wave-to-logic level converter 122. Yes. According to the preferred chip integration level, phase detector circuit 114, divider 120, and crystal oscillator circuit 112 and a portion of VCO 118 are incorporated into chip module 146. A presently preferred chip module is available from RF Microdevices, Inc. (Greensborough, NC) under the product number “RF2514” and is used in this example.

  The crystal oscillator circuit 112 has a Colpitts configuration, and includes a chip mounting element 148, a package crystal module 124, and a discrete varactor 128. Arranged in parallel with the discrete varactor 128 is a fixed capacitor 129 (C15) for setting the overall load capacity within an appropriate range. The bias DC voltage of the varactor 128 is set by the control input 130. According to the Colpitts configuration, the crystal oscillator circuit 112 has a feedback loop 150 comprising a capacitor 152 (C2).

  The crystal resonator 124 is a surface mount type and can be purchased from CTS Wireless Components Inc. (Bloomingdale, Ill.) As part number ATXN6034A and is designed to resonate at 19.44 MHz under a load of 10 picofarads. ing.

  The crystal oscillator circuit 112 supplies a reference output 132 to the phase detector 114 mounted on the chip. The chip module 146 has a connection part 154 (LOOP_FLT) to the loop filter 116. The loop filter 116 receives and accumulates the frequency offset signal 136 from the phase detector circuit 114. The loop filter 116 includes capacitors 156 (C11), 158 (C12), and a resistor 160 (R6).

The loop filter 116 supplies a VCO control signal 138 to a voltage controlled oscillator circuit 118 having components mounted on the chip and discrete components. The non-chip mounted is preferably a discrete component forming the tank circuit 142, three inductors 162 (L2), 164 (L3) connected through 168 (RESNTR +) and 170 (RESNTR−) of the module 146, 165 (L4) and a capacitor 166 (C14). The variable inductor 172 allows the center frequency of the VCO output to be tuned (or “tuned”) to offset the inevitable deviations of the various VCO components. The variable inductor 172 preferably takes the form of a power strip microstrip (MS1), also referred to as a “laser paddle”. The VCO circuit 118 of the module 146 receives the bias voltage through the tank circuit 142 via the connection 174 with the resistor 176 (R8).
The VCO circuit 118 includes a chip mounted output amplifier 178 that provides an independent control frequency signal 141 (TX_OUT) in response to a control frequency signal symbolically designated by reference numeral 140 in module 146.

  Divider 120 receives control frequency signal 140 and provides a reduced frequency feedback signal 134. The division ratio of the divider 120 is preselected by setting the logic input 180 (DIV_CTRL). In this example, as shown, input 180 is connected to ground to generate a logic low level to set module 146 to a division ratio of 32: 1.

  The circuit 110 has a sine wave-to-logic level converter 122 in the form of a differential receiver that receives the sine wave output signal 141. A preferred differential receiver is available from Micrel Semiconductor (San Jose, Calif.) Under the part number “SY10EP16V” and is used in this example. Another preferred one is a chip module that can be purchased from Arizona Microtech (Mesa, Arizona) under the product number “AZ100LVEL16”. The differential receiver module 122 provides a digital output signal according to 10K positive emitter coupled logic (PECL), with a logic zero in the range of about 1.49 volts to about 1.68 volts, and a logic 1 of about 2.. It is in the range of 28 volts to about 2.42 volts. These output levels are achieved when the supply voltage to the module 122 is about 3.3 volts. The PECL output is complementary and requires two terminals 144A (Q_OUTOUT), 144B (/ Q_OUTOUT).

  The frequency controllable oscillator 110 exhibits a desirable level of circuit integration. A circuit integrated configuration that includes a tank circuit 142 without an integrated voltage controlled oscillator (VCO) 118 has particular advantages. Other preferably not mounted on the chip are circuit elements forming the loop filter 116 and the varactor 128.

  The module 146 includes GND1, GND2, GND3, PD, VCC1, VCC2, MOD IN, VREF, and LD_FLT as pin connections not yet described. GND1 and GND3 are ground connections used by the analog components of the module 146. GND2 is a ground connection used for the digital elements of the phase detector and the synchronization circuit. PD is a DC voltage on-off switch. VCC1 is the DC bias of the amplifier 178. VCC2 is a DC bias input connection to the VCO 118. MOD IN is not used by the oscillator 110. VREF is not used except in embodiments that provide a high Q filter. LD_FLT is a discrete filter connection for the phase detector circuit.

  Circuit and package designs for elements having radio frequency (RF) signals include many bypass capacitors to suppress parasitic signals that may be picked up from nearby circuit elements such as transistors and power lines. The oscillator 110 includes filter capacitors such as C3, C4, C5, C8, C9, C6, C10, and C13. FIG. 3 is a circuit board layout used in this example to implement the circuit shown in FIG. The layout of FIG. 3 provides the oscillator 110 in a surface mount or pin package having a length of about 14 mm (reference 186), a width of about 9.3 mm (reference 188) and a height of at most about 2.4 mm. Enable. In the form of a package, the controllable oscillator 110 includes a variable voltage control input 130 (VC), a DC power input 182 (VCC), a digital output 144A (OUT), 144B (/ OUT), all specified in FIG. And a connection for the on-off switch connection 184 (E / D).

Connection 184 (E / D) is coupled to terminal PD of module 146. In this preferred embodiment, the minimum height limit of the package is governed by the thickness of the circuit board and the crystal subpackage 124. The controllable crystal oscillator 110 of this example is a particularly preferred embodiment of the present invention. The controllable crystal oscillator 110 includes an AT cut crystal subpackage 124 configured to operate in a 19.44 MHz fundamental mode, with a divider circuit 120 preset to divide the feedback signal 140 by 32. Specifications for selected circuit elements of FIG. 2 are shown in Table 1 below.

  The operating characteristics of the controllable crystal oscillator 110 were measured over the voltage range of the voltage variable control input 124. The results are shown in Table 2 below.

上記のデータは、負荷インピーダンス５０オームで、制御されない（ただし、実質的に室温の）温度下で、アジレントテクノロジー社（カリフォルニア州パロアルト）から購入できるＨＰ４３９６Ａネットワーク／スペクトラム分析器を使用して記録された。図３は、このデータをプロットしたもので、比較的線形の動作関係を示す。図３、表２から分かるように、出力動作周波数は、約６２２，０１８キロヘルツから約６２２，１４２キロヘルツの範囲で選択可能である。同様に、（１４４における）出力周波数の（１３０における）制御入力電圧に対する挙動は、非線形性が約１０パーセント以下の最良の直線性を示す。

The above data was recorded using a HP4396A network / spectrum analyzer available from Agilent Technologies (Palo Alto, Calif.) At an uncontrolled (but substantially room temperature) temperature with a load impedance of 50 ohms. . FIG. 3 is a plot of this data and shows a relatively linear operating relationship. As can be seen from FIG. 3 and Table 2, the output operating frequency can be selected in the range of about 622,018 kilohertz to about 622,142 kilohertz. Similarly, the behavior of the output frequency (at 144) with respect to the control input voltage (at 130) shows the best linearity with a non-linearity of about 10 percent or less.

The test results show that the operating digital output frequency of the controllable oscillator 110 is the following for a V _control value in the range of about 0.15 volts to about 3.15 volts, where V _control is the DC voltage level of the voltage variable input: Characterized by a point in the region defined between the two equations.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz

FIG. 4 includes plots of f1 _output and f2 _output . Additional test results are summarized in Table 3 below.

  The rise and / or fall time for the PECL output did not exceed about 400 picoseconds.

  The frequency controllable oscillator 110 is operatively and commonly coupled to energize both the module 146 and the sine wave-to-logic level converter 122, for example, at the same DC voltage level of about 3.3 volts. Supply DC power input 182 (VCC). Alternative embodiments include DC-DC regulators that allow module 146 and converter 122 to be powered at different voltage levels via a common voltage supply. For example, the supply DC input 182 (VCC) is approximately 5 volts, the converter 122 is approximately 5 volts, the module 146 is approximately 3.3 volts, and is powered via a regulator operating with a 5 volt supply input. Is done.

  The present invention provides several important features in the design of oscillations. The oscillator of the present invention provides a voltage adjustable, relatively high frequency (> 500 MHz) digital output signal using a low cost conventional crystal resonator. The overall package size is reduced by a combination of achievements that enhance the characteristics of the integrated circuit and discrete components.

Alternative Embodiment with Increased Temperature Tolerance Schematically illustrated in FIG. 5 is an oscillator 210 with increased tolerance to changes in operating temperature. The oscillation frequency of quartz crystal depends on temperature, and its sensitivity generally varies depending on crystal cut and crystal quality. The preferred embodiment of the present invention includes a temperature compensator so that the crystal oscillator circuit can be digitally calibrated to correct for temperature effects.

  Referring to FIG. 5, the frequency controllable oscillator 210 includes a temperature sensor 203, a temperature compensation logic unit 205, a variable capacitance circuit 207, a resonator gain stage 226, a crystal resonator 124, a phase detector circuit 214, a loop filter 216, It has a voltage controlled oscillator (VCO) circuit 218, a divider circuit 20, and a sine wave-to-logic level converter circuit 222.

  The crystal resonator 224 is given energy for oscillation by the gain stage 226. The frequency of oscillation based on this crystal resonator can be adjusted by a variable capacitance circuit 207 that adjusts the entire reactive / capacitive load. The variable capacitance circuit 207 responds to two adjustment signals of a capacitance adjustment signal 208 generated by the temperature compensation logic unit 205 and a control input 230 for external frequency control.

  The variable capacitance sub-circuit 228 is in parallel with at least one discrete variable capacitance diode (ie, varactor) operatively coupled to the control input 230, as described above with respect to the variable capacitance element 28 (for the oscillator 10). Preferably, the circuit includes a transistor switchable capacitor and a second variable capacitance element in the form of a chip mounted varactor bank. The second variable capacitance element is responsive to the capacitance adjustment signal 208.

  Other configurations of the variable capacitance circuit 228 are also conceivable. As the integration on the chip increases, both the control input and capacitance adjustment 208, together with the assignment logic, combine the transistor-switchable capacitor and / or the allocation logic to synthesize the desired capacitance adjustment from each control signal. Alternatively, it is provided by a bank of varactors mounted on a transistor-switchable chip.

  The capacity adjustment signal 208 is generated by the temperature compensation logic unit 205 including the temperature sensor 203. The temperature compensation logic unit 205 includes a memory (for example, an EEPROM) including information that characterizes the temperature dependence of the crystal resonator 224. More specifically, the temperature compensation logic unit 205 is programmed at the time of manufacture with digital data that substantially corresponds to the inverse function of the frequency deviation of the crystal resonator 224 with respect to temperature. Here, in the case of an AT cut crystal, which is considered preferable, this inverse function corresponds to a Beckmann curve that is well approximated by a cubic or higher order polynomial expansion. For additional accuracy, a fourth order expansion is preferred.

  In practice, the polynomial coefficients of the Beckman curve are calculated for each crystal resonator 224 and these values are programmed into memory. Alternatively, the memory is programmed with a table of actual frequency deviations of the crystal resonator 224 over a discrete temperature range, which is recalled and applied to the variable capacitance circuit 207.

  In the preferred embodiment, temperature sensor 203 is a string of chip integrated cascaded diodes located near crystal resonator 224, although thermistors and appropriately scaled transistors are also compatible. The temperature sensor 203 supplies a temperature instruction signal to the compensation logic unit 205, where the temperature change is converted into a capacitance adjustment necessary to suppress a frequency change related to an arbitrary temperature.

  The resulting drive signal 232 is received by the phase detector (or phase comparator) circuit 214 and compared with the reduced frequency feedback 234 signal from the divider circuit 220. Phase detector 214 generates phase offset signal 36 having a DC voltage level that is proportional to the phase difference between reduced frequency feedback signal 234 and drive signal 232.

  The above detailed description of the phase detector 14, the loop filter 16, the voltage controlled oscillator (VCO) 18, the frequency divider 20, and the converter 22 of the oscillator 10 includes the phase detector 214, the loop filter 216, the oscillator 210. The same applies to the voltage controlled oscillator (VCO) circuit 218, the frequency divider 220, and the converter 222.

  Loop filter 216 is operatively coupled between phase detector 214 and voltage controlled oscillator (VCO) 218 to remove high frequency components from the VCO control signal. Voltage controlled oscillator (VCO) 218 is responsive to changes in the DC voltage level of VCO control signal 238. VCO 218 provides the resulting analog control frequency signal 240. The loop filter 216 accumulates the pulses received from the phase detector 214 and generates a control voltage for the VCO control signal 238.

  The analog control frequency signal 240 passes through the divider circuit 220 to produce a corresponding reduced frequency feedback signal 234. Divider 220 allows phase detector 214 to operate with a transmitted signal having a frequency in the range of the fundamental mode frequency of crystal resonator 224.

  As described above for oscillator 10, oscillator 210 includes a converter subcircuit 222 that converts a sinusoidal control frequency signal 240 into a logic level output signal 244.

  As described above, many variations of the design for assigning the necessary load capacity adjustment to the external control unit 230 and the temperature compensation unit 205 can be considered here. FIG. 6 is referred to as another embodiment. The frequency controller 310 uses a packaged temperature compensated crystal oscillator module 390 that includes a discrete varactor 328 responsive to an input 330 for external frequency control and a variable capacitor for temperature compensation. The module 390 includes a crystal resonator 324 and an integrated circuit 392. The integrated circuit 392 combines the chip-mounted variable capacitance element 394, the temperature sensor 303, the temperature compensation logic unit 305, and the crystal gain stage 326.

  The resulting drive signal 332 and other elements of the oscillator 310, namely the phase detector circuit 314, the loop filter 316, the voltage controlled oscillator (VCO) circuit 318, the frequency divider 320, and the converter 322 are described above. This is the same as described above for the oscillators 10 and 210. The dashed outline 346 in FIG. 6 indicates the preferred level of integration. A phase detector element 314, a divider element 320, and a portion of a voltage controlled oscillator (VCO) 318 are integrated. What is preferably not mounted on the chip is a loop filter 316 and a VCO tank circuit 342.

Example of Oscillator with Reduced Temperature Change Referring to the simplified circuit diagram of FIG. 7, the controllable crystal oscillator 410 uses a temperature compensated crystal oscillator module 490.

  The oscillator 410 is surface mountable and includes a temperature compensated crystal oscillator subpackage (TCXO) 490, a phase detector 414, a loop filter 416, a voltage controlled oscillator (VCO) 418, a frequency divider 420, and a sine wave-logic level. A converter 422 is included. A portion of phase detector circuit 414, divider circuit 420, and VCO 418 are coupled to chip module 446. A presently preferred chip module can be purchased from RF Microdevices, Inc. (Greensborough, NC) under the product number “RF2514” and is used in this example.

  The temperature compensated crystal oscillator 490 is of the type that can be purchased from CTS Wireless Parts Inc. (Bloomingdale, Ill.) Under part number OSC1625A and is used in this example. The TCXO 490 is a surface-mountable subpackage having dimensions of 3.2 mm wide, 5.0 mm long, and 1.5 mm high. It has four surface mount connections: ground 490, output 493, supply power 495, and logic control 496. This package has additional operative links (or connections) through the side chest walls including connections 497 for direct access to the crystal resonators therein.

  Operatively coupled to the crystal via connection 497 is an additional fixed capacitor 429 (C15) and a discrete varactor 428 to set the overall load capacity in the appropriate range. The bias DC voltage of the varactor 428 is set by the control input 430. The TCXO 490 comprising the varactor 428 provides a drive signal 432 to the module 446 and the phase detector circuit 414 mounted on the chip therein. The chip module 446 has a connection part 454 (LOOP_FLT) for the loop filter 416. The loop filter 416 receives and accumulates the frequency offset signal 436 from the phase detector circuit 414. The loop filter 416 includes capacitors 456 (C11), 458 (C12), and a resistor 460 (R6).

  The loop filter 416 supplies a VCO control signal 438 to a voltage controlled oscillator circuit 418 having chip mounted components and discrete components. Preferably not mounted on the chip are three transistors 462 (L2), 464 (L3), 465 (L4) connected via 468 (RESNTR +) and 470 (RESNTR-) of the module 446, and a capacitor 446 (C14). ) Of the discrete circuit forming the tank circuit 442. The variable inductor 472 allows the center frequency of the VCO output to be tuned to cancel out unavoidable variations in various VCO components. The variable inductor 472 preferably takes the form of a transmission line microstrip (MS1). The VCO circuit 418 of the module 446 receives the bias voltage from the power supply 482 through the tank circuit 442 via the coupling 474 to the resistor 476 (R8).

  The VCO circuit 418 includes a chip-mounted output amplifier 478 that supplies an independent control frequency signal 441 (TX_OUT) in response to the control frequency signal 440.

  Divider 420 receives control frequency signal 440 and provides a reduced frequency feedback signal 434. The divider ratio of divider 420 is preselected by setting logic input 480 (DIV_CTRL). Input 480 is connected to ground in this example to generate a logic low to set module 446 to a 32: 1 divide ratio. A sine wave to logic level converter 422 (differential receiver) receives the sine wave output 441. A preferred differential receiver is available from Micrel Semiconductor (San Jose, Calif.) Under the part number “SY10EP16V” and is used in this example. The differential receiver module 422 provides a digital output signal according to the 10K positive emitter coupled logic (PECL) standard (described above). The PECL output is a complementary output and requires two terminals 444A (Q_OUTOUT) and 444B (/ Q_OUTOUT).

  As already described with reference to FIG. 2, an actual RF circuit has a bypass capacitor in order to suppress a parasitic signal that may be picked up by a nearby circuit element such as a transistor or a transmission line. The oscillator 410 has the following bypass capacitors C4, C5, C6, C8, C9, C10, and C13.

The specifications of the selected circuit elements of FIG. 7 are shown in Table 4 below.

Packaged Oscillator Embodiment FIG. 8 is a schematic cross-sectional view of a packaged oscillator embodiment of the present invention. The voltage controlled crystal oscillator 1100 includes a pedestal 1102, a wall 1106, an upper (or first) cavity 1110, a lower (or second) cavity 1108, a cover 1112, and a laminated substrate in the form of a circuit board 1170. Includes a double-sided package. The pedestal 1102 has an upper surface 1102a, a lower surface 1102b, a central portion, and an outer portion 1102c. The pedestal is configured to pass the first signal between the upper surface 1102a and the lower surface 1102b. The lower surface 1102b is configured to receive a first component such as, but not limited to, a chip module 156 (identified by reference numeral 46 in FIG. 1).

  The circuit board 1170 has an upper surface 1170a and a lower surface 1170b. The top surface 1170a is configured to receive additional components. These include, but are not limited to, a voltage variable capacitive element in the form of a discrete varactor 1158 (identified by reference numeral 28 in FIG. 1), a tank 1164 (42 in FIG. 1), and (22 in FIG. 1). A converter IC 1162 and a chip capacitor (not shown separately) are included.

  The oscillator 1100 includes a side wall (or wall portion) 1106a extending upward, a side wall (or lower portion) 1106b extending downward, a side wall bottom portion 1106c, and a side wall top portion 1106d. The upper part 1106a and the lower part 1106b are separated by a pedestal 1102. The bottom portion 1106c is configured to pass a second signal between the wall portion 1106 and the circuit board 1170. The cover 1112 is fixed to the upper portion 1106 a of the wall portion 1106.

  The lower cavity 1108 is defined by the lower surface 1102 b of the pedestal 1102, the lower portion 1106 b of the wall portion 1106, and the upper surface 1170 a of the circuit board 1170. The lower cavity 1108 is configured to receive and interconnect components. The upper cavity 1110 is defined by the upper surface 1102 a of the pedestal 1102, the upper portion 1106 a of the wall portion 1106, and the cover 1112. The upper cavity 1110 is hermetically sealed and configured to accommodate the AT-cut quartz crystal resonator 1150. The pedestal 1102 facilitates isolation of the upper and lower cavities 1108, 1110 and the components of the cavities 1108, 1110, and thus is hermetically sealed before the electronic components of the lower cavities 1108 can be separately processed. By providing the resonator 1150, the possibility of contamination is minimized.

  The oscillator 1100 has a substantially flat pedestal 1102. The pedestal 1102 has an upper surface 1102a, a lower surface 1102b, and an outer portion 1102c. Extending substantially upward and downward from the outer portion 1102 c are an upper portion 1106 a and a lower portion 1106 b of the wall portion 1106. The upper surface 1102 a of the pedestal 1102, the upper portion 1106 a of the wall 1106, and the cover 1112 form a substantially rectangular upper cavity 1110 that is configured to accommodate the resonator 1150.

  The lower surface 1102b of the pedestal, the lower portion 1106b of the wall portion 1106, and the circuit board 1170 form a lower cavity 1108. The lower cavity 1108 is configured to accommodate a plurality of electronic components.

The external shape (or shape) of the oscillator 1100 can vary widely. In one embodiment, the oscillator 1100 is substantially portable and is rectangular or square and is adapted for placement in an electronic device that occupies a small volume of the overall volume of the electronic device. Furthermore, the oscillator 1100 is suitable for mass production and miniaturization. For example, the oscillator preferably has a mounting surface of approximately 5 × 7 millimeters (mm) or less. Similarly, the oscillator 1100 preferably has a mounting surface with an area of less than about 40 square millimeters (mm ² ).

  The oscillator 1100 is preferably made of a material having substantially the same thermal expansion coefficient to minimize stress in the package. In one embodiment, the pedestal 1102 and the downwardly extending sidewalls are made of multiple layers of co-fired ceramic material such as alumina. Particularly preferred is a so-called co-fired ceramic material such as alumina, which is manufactured by various molding and pressure welding techniques and has high heat resistance and has thick and thin metallization, and is formed on the pedestal 1102 and the side wall 1106b. Suitable material. While these materials are preferred, as is the case in many manufacturing techniques, it is known in the art that there are many other manufacturing materials that will perform equally well.

  The side wall 1106a extending upward is made of an alloy of tungsten, nickel, iron, cobalt, or metal. An alloy of nickel, iron and cobalt is available from Carpenter (Leading Pennsylvania) under the trade name “KOVAR”. The coefficient of thermal expansion of KOVAR is substantially equivalent to the preferred ceramic material of the pedestal 1102 and the sidewall 1106b.

  A plurality of internal leads 1114 (shown symbolically by dashed lines in FIG. 8) are provided for interconnection between the electronic components and the resonator 1150. A plurality of leads 1114 are coupled to a plurality of respective electrical contacts located at the bottom 1106 d of the wall 1106. Preferably, the bottom 1106d of the wall 1106 is substantially flat to provide a connection to the circuit board 1170. The internal lead 1114 is formed across the base 1102 and the lower portion 1106 b of the wall portion 1106. Preferably, the bottom 1106d of the wall 1106 is substantially planar to provide contact with the circuit board 1170. The lead 1114 provides an electrical path from a component mounted on the resonator 1150 and the lower surface 1102 b of the pedestal 1102 to the bottom 1106 c of the wall 1106. The leads 1114 include, but are not limited to, metallization trace patterns on the ceramic layers that form the ceramic package and co-fired vias between the layers. The oscillator 1100 can also have a plated half-hole called the chest wall outside the downwardly extending sidewall 1106b. Such a chest wall facilitates testing and testing of the electrical connection 1122 (typically soldered) between the terminals and the circuit board 1170.

  The lower cavity 1108 is configured to receive and interconnect an ASIC (application specific integrated circuit) such as a chip module 1156 (identified by reference numeral 46 in FIG. 1) attached to the pedestal 1102. The ASIC can have a variety of structures, but preferably includes a glob top flip chip integrated circuit containing an organic underfill, or an integrated circuit configured to form a gold-gold interface. , A wire bonded integrated circuit. The ASIC is preferably a flip chip that is solder reflowed to a metallized portion near the center of the pedestal 1102 so that the solder forms an electrical and mechanical connection between the ASIC and the pedestal 1102. In the most preferred embodiment, the ASIC is a flip chip integrated circuit that also has an organic underfill to enhance the mechanical coupling of the ASIC to the pedestal 1102 and reduce the potential for contamination to the ASIC.

  FIG. 9 is a schematic view of the lower surface 1102 b in the cavity 1108. More specifically, FIG. 9 includes a view of the pedestal lower surface 1102b with no electronic components mounted thereon to show exemplary connection pads for inspection and component mounting. As preferably provided on the lower surface 1102b, the cavity 1108 includes a set of tuning contacts 1131, 1132 that are conductively coupled to the resonator 1150 for tuning. Similarly, a plurality of contacts 1133 for surface mounting of the ASIC are provided on the lower surface 1102b.

  Upper cavity 1110 is configured to receive resonator 1150. The resonator 1150 is preferably an AT-cut quartz crystal, similar to that described for FIG. The upper cavity 1110 may hold additional parts. However, isolating resonator 1150 from several other components can reduce the possibility of contamination of resonator 1150. More specifically, by isolating and physically separating the resonator 1150 of the upper cavity 1110 from the components of the lower cavity 1108, solder, organic underfill, and other undesirable contaminants can be output from the resonator 1150. The possibility of adverse effects on the frequency can be reduced.

  The cover 1112 has a complementary shape so as to be received and coupled to the side wall 1106a extending above the wall portion 1106, in particular, the side wall 1106d extending upward. The cover 1112 can be attached to the upper portion 1106a of the wall 1106 in a number of ways including, but not limited to, seam welding, solder sealing. Cover 1112 is attached to upwardly extending sidewall 1106a in a manner that provides a hermetic seal. The cover 1112 can be formed from many materials known to those skilled in the art including, but not limited to, metals and alloys such as KOVAR, with KOVAR being preferred at present.

  The resonator 1150 is located on the coupling portion 1118 and coupled. The coupling 1118 provides mechanical and electrical connection to the resonator 1150. Electrically coupled to coupling 1118 is a lead identified symbolically by reference numeral 1120. The coupling portion 1118 is, but not limited to, a conductive flexible material such as silver epoxy or silver-filled silicon. Lead 1120 is preferably, but not limited to, a tungsten filled via. The lead 1120 connects the resonator 1150 to another circuit such as a circuit in the lower cavity 1108 or a circuit mounted on the circuit board 1170. Coupling portion 1118 includes a wrap portion 1152 for operably and electrically connecting resonator 1150 to lead 1120.

  The downwardly extending sidewall 1106b is coupled to the circuit board 1170 in a variety of ways known to those skilled in the art. The side wall bottom portion 1106c is configured to facilitate installation on the circuit board 1170 or the same type of board. A plurality of contacts are appropriately connected to each lead 1114 and the metallized path on the circuit board 1170.

  The circuit board 1170 has a flat upper (or cavity facing) surface 1170a and a flat lower (or outward facing) surface 1170b. The top surface 1170a has electrical components attached thereto. The circuit board 1170 is configured to couple to the lower cavity 1108, particularly the sidewall 1106c extending downward. The circuit board 1170 can be, but is not limited to, a multilayer printed circuit board (eg, four layers). To save space, the inductor used in the tank circuit 42 (FIG. 1) can optionally be embedded between the layers of the substrate 1170. The circuit board 1170 optionally has a plated half hole, sometimes referred to as a chest wall, to provide an electrical path from or to the oscillator 1100. The bottom surface 1170b of the circuit board 1170 has conductive pads 1174 to facilitate electrical surface mount connection of the oscillator 1100 to the electronic device.

  The resonator 1100 includes: (1) forming a pedestal 1102 and a wall 1106; (2) applying silver epoxy to the center of the pedestal 1102 to receive crystals; and (3) AT on the pedestal 1102 Mounting the cut quartz crystal 1150; (4) applying silver epoxy to the top of the crystal 1150 to form the wrap connection 1152; and (5) curing the silver epoxy in a furnace for an appropriate time. (6) a step of performing tuning by adjustment by mass loading while driving the crystal 1150 through the contacts 1131 and 1132; and (7) placing and sealing the cover 1112 by seam welding. Sealing the upper cavity 1110 with (8) the lower surface 1102b of the lower cavity 1102b A step of mounting one or more electronic components such as an ASIC, and (9) a connection portion and a contact for receiving the additional component, a side wall 1106b extending downward, and a connection portion of the lower surface mounting 1174. Providing a printed circuit board 1170 having a first surface 1170a; (10) mounting additional electronic components on an upper surface 1170a of the circuit board 1170; and (11) a sidewall 1106c extending downward from the circuit board 1170. It is manufactured by attaching to the bottom portion 1106c and (15) forming a chest wall on the circuit board 1170.

  The placement of additional electronic components on the lower surface 1102b may include epoxy encapsulation of the first electronic component and / or underfill. Crystal resonator 1150 is preferably tunable. Thus, the lower cavity 1108 has accessible conductive pads 1131 and 1132 (FIG. 9) for driving the crystal 1150 during the frequency tuning step. The tuning step involves the addition of metal to the electrode (FIG. 10) (or removal of metal from the electrode).

  Many variations and modifications of the embodiments described above can be made without departing from the spirit and scope of the novel construction of the present invention. No limitation with respect to the particular system described herein is intended or suggested. Of course, the appended claims are intended to cover all such modifications as fall within the scope of the claims.

FIG. 1 is a schematic diagram of a controllable oscillator according to one embodiment of the present invention. FIG. 2 is a simplified circuit diagram according to one embodiment of the present invention. FIG. 3 is a circuit board layout for realizing the controllable oscillator shown in FIG. FIG. 4 is a graph of the operating curve of an oscillator made according to the simplified circuit diagram shown in FIG. FIG. 5 is a schematic diagram of a controllable oscillator according to another embodiment of the invention including temperature compensation. FIG. 6 is a schematic diagram of a controllable oscillator according to another temperature compensated embodiment of the present invention. FIG. 7 is a simplified circuit diagram according to another embodiment of the present invention. FIG. 8 is a schematic cross-sectional view of an embodiment of the packaged oscillator of the present invention. FIG. 9 is an exemplary schematic bottom view, partly in section, showing the lower cavity of the packaged oscillator of FIG. 8 shown with no components mounted to show exemplary connection pads. FIG. 10 is an exemplary schematic top view showing, in partial cross section, the upper cavity of the packaged oscillator of FIG. 8 shown without a cover to show details of mounting the crystal blank.

Claims (77)

A crystal oscillator circuit having a voltage variable control input for generating a drive signal and adjusting a frequency of the drive signal, a discrete varactor responsive to the control input, and an AT cut crystal operatively coupled to the varactor The crystal oscillator circuit comprising: a resonator; and a gain stage for energizing the crystal resonator;
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A divider circuit having a preselected divide ratio that is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generates a reduced frequency feedback signal in response to the control frequency signal. When,
A frequency adjustment adapted to digital signal clock synchronization comprising a sine wave-to-logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital logic output signal having substantially the same frequency as the control frequency signal. A possible oscillator,
The oscillator, wherein the phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal.   The oscillator according to claim 1, wherein the crystal resonator operates in a fundamental mode.   The oscillator of claim 1, wherein the crystal resonator operates in a fundamental mode having a frequency of about 19.44 megahertz.   The oscillator of claim 1, wherein the crystal resonator operates in a fundamental mode at a frequency of about 19.44 megahertz and the preselected divide ratio is about 32 to 1.   The oscillator of claim 1, wherein the crystal resonator operates in a fundamental mode at a frequency of about 20.828 megahertz and the preselected divide ratio is about 32.   The crystal resonator operates in a fundamental mode at a frequency of about 19.44 megahertz, the preselected divide ratio is about 32 to 1, and the digital logic output is about 622,018 kilohertz to about 622 The oscillator of claim 1, having a controllable operating frequency in the range of 142 kilohertz. The crystal resonator operates in a fundamental mode at a frequency of about 19.44 megahertz, the preselected divide ratio is about 32 to 1, and V _control is a DC voltage level of the voltage variable input, about against V _control value in the range of 0.15 volts to about 3.15 volts, claims wherein the digital logic output, and having an operating frequency in the region defined between the following two equations The oscillator according to 1.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz The V _control as DC voltage level of said voltage variable input for _{V control} value in the range of about 0.15 volts to about 3.15 volts, operation of the digital output of the region defined between the following two equations The oscillator according to claim 1, wherein the oscillator shows a frequency.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz   The oscillator according to claim 1, further comprising a crystal oscillator circuit having a Colpitts crystal oscillator configuration.   The oscillator according to claim 1, wherein the crystal oscillator circuit is configured as a Pierce crystal oscillator.   The oscillator of claim 1, wherein the converter circuit is a differential receiver adapted to generate the digital output signal at a voltage level according to positive reference emitter coupled logic (PECL).   The oscillator of claim 1, wherein the converter is a differential ECL driver.   The oscillator of claim 1, wherein the differential receiver is adapted to generate a digital output signal that oscillates between voltage levels according to 10K PECL.   The oscillator of claim 1, wherein the differential receiver is adapted to generate a digital output signal that oscillates between voltage levels according to 100K PECL.   Voltage according to a semiconductor circuit technology wherein the converter circuit is selected from the group consisting essentially of transistor-transistor logic, emitter coupled logic, CMOS, MOSFET, GaAs field effect, HCMOS, MESFET, HEMT, PHEMT, CML, and LVDS The oscillator of claim 1, wherein the oscillator is adapted to generate a digital output signal that oscillates between levels. 2. The oscillator according to claim 1, wherein the following elements are integrated on a single semiconductor chip.
The gain stage, the phase detector circuit, the voltage controlled oscillator circuit, and
The frequency divider circuit; 2. The oscillator of claim 1, wherein the voltage controlled oscillator circuit includes a tank subcircuit and the following elements are integrated on a single semiconductor chip.
-The gain stage-the phase detector circuit-the voltage-controlled oscillator circuit other than the tank sub-circuit; and
The frequency divider circuit; The oscillator according to claim 1, wherein the voltage controlled oscillator circuit includes a tank subcircuit and a differential amplifier subcircuit, and the following elements are integrated on a single semiconductor chip.
-The gain stage-the phase detector circuit-the differential amplifier-the divider circuit V _control as the DC voltage level of the voltage variable input, with a load impedance of about 50 ohms measured at a temperature in the range of about −30 degrees to about 80 degrees Celsius, The oscillator according to claim 1, wherein the oscillator shows an operating digital output frequency in a region defined between the following two equations with respect to a V _control value.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz With V _control being the DC voltage level of the voltage variable input, for a V _control value in the range of about 0.15 volts to about 3.15 volts, the operating frequency in the region defined between the following two equations is The oscillator according to claim 1, wherein the digital output has an operating RMS phase jitter of up to 8 picoseconds measured with a bandwidth of 12 kHz to 20 MHz.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz   21. The oscillator of claim 20, wherein the operating phase jitter of the digital output measured with a bandwidth of 12 kHz to 20 MHz is a maximum of 1 picosecond.   The crystal resonator operates in a fundamental mode at a frequency of about 19.44 megahertz, the preselected divide ratio is about 32 to 1, and the digital logic output is about 622,018 kilohertz to about 622 The oscillator of claim 1, wherein the oscillator is selectable in the range of 142 kilohertz and exhibits excellent linearity of 10 percent or less. A crystal oscillator circuit having a voltage variable control input for generating a drive signal and adjusting a frequency of the drive signal, the voltage variable capacitor element responsive to the control input, and an AT cut operatively coupled to the varactor A crystal oscillator circuit, comprising: a crystal resonator; and a gain stage that energizes the crystal resonator, the crystal resonator being adapted to resonate at a fundamental frequency of about 19.44 megahertz;
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A preselected divider ratio of about 32: 1 is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit to generate a reduced frequency feedback signal in response to the controlled frequency signal. Having a divider circuit;
A sine wave-to-logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital output signal having substantially the same frequency as the control frequency signal;
The phase detector circuit is frequency tunable adapted to digital signal clock synchronization responsive to the feedback signal and the drive signal to change the phase offset signal according to the phase difference between the feedback signal and the drive signal An oscillator,
With V _control being the DC voltage level of the voltage variable input, for a V _control value in the range of about 0.15 volts to about 3.15 volts, the operating frequency in the region defined between the following two equations is An oscillator characterized by showing.
f1 _output = 0.04526 (V _control ) +621.9430 MHz f2 _output = 0.04526 (V _control ) +6211.9679 MHz   The converter circuit is a differential receiver adapted to generate the digital output signal at a voltage level that compliments complementary to positive reference emitter coupling logic (PECL) / positive emitter coupling logic (PECL) /; 24. An oscillator according to claim 23, characterized in that:   The oscillator of claim 23, wherein the converter is a differential ECL driver.   24. The oscillator of claim 23, wherein the differential receiver is adapted to generate a digital output signal that oscillates between voltage levels according to 10K PECL or 100K PECL.   Between the voltage levels according to the semiconductor circuit technology in which the converter circuit is selected from the group essentially comprising transistor-transistor logic, emitter coupled logic, CMOS, MOSFET, GaAs field effect, MESFET, HEMT, PHEMT, LVDS, or CML 24. The oscillator of claim 23, wherein the oscillator is adapted to generate a digital output signal that oscillates at. 24. The oscillator according to claim 23, wherein the following elements are integrated on a single semiconductor chip.
The gain stage, the phase detector circuit, the voltage controlled oscillator circuit, and
The frequency divider circuit; 24. The oscillator of claim 23, wherein the voltage controlled oscillator circuit includes a tank subcircuit and the following elements are integrated on a single semiconductor chip.
-The gain stage-the phase detector circuit-the voltage-controlled oscillator circuit other than the tank sub-circuit; and
The frequency divider circuit; 24. The oscillator of claim 23, wherein the voltage controlled oscillator circuit includes a tank subcircuit and a differential amplifier subcircuit, wherein the following elements are integrated on a single semiconductor chip.
-The gain stage-the phase detector circuit-the differential amplifier-the divider circuit   24. The oscillator according to claim 23, wherein the voltage variable capacitance element is a discrete varactor part.   24. The oscillator of claim 23, wherein the voltage variable capacitance element includes a switchable bank of capacitors.   The oscillator according to claim 23, wherein the voltage variable capacitance element includes a bank of varactors on which a switchable chip is mounted. A variable capacity unit having a control input and providing a variable capacity load in response to the control input;
A resonator gain stage;
A crystal resonator that is operatively coupled to the gain stage and the variable capacitance unit to generate a drive signal, wherein the capacitive load and the frequency of the drive signal can be adjusted by the control input. The quartz crystal vibrator,
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
Compatible with digital signal clock synchronization comprising a frequency divider circuit operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit to generate a reduced frequency feedback signal in response to the control frequency signal A frequency adjustable oscillator,
The oscillator, wherein the phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal.   The sine wave-to-logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital logic output signal having substantially the same frequency as the control frequency signal. The oscillator described.   The variable capacitance circuit comprises a variable capacitance sub-circuit integrated on a chip operatively coupled to a temperature compensation logic unit, and a discrete varactor operatively coupled to the control input. 35. The oscillator of claim 34.   35. The oscillator of claim 34, wherein the capacitive element comprises a switchable bank of capacitors.   24. The oscillator according to claim 23, wherein the capacitive element includes a bank of varactors on which a switchable chip is mounted. With V _control being the DC voltage level of the voltage variable input, the operating digital output frequency in the region defined between the following two equations is given for a V _control value in the range of about 0.3 volts to about 3 volts: 35. The oscillator of claim 34, wherein:
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz A temperature sensor;
A temperature compensation logic unit operatively coupled to the temperature sensor to generate a capacitance adjustment;
A variable capacitance circuit comprising a control input and providing a variable capacitance load in response to the control input, wherein the variable capacitance circuit is responsive to the capacitance adjustment;
A resonator gain stage;
A crystal resonator operatively coupled to the gain stage and the variable capacitance circuit to generate a drive signal;
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A divider circuit having a preselected divide ratio that is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generates a reduced frequency feedback signal in response to the control frequency signal. A frequency tunable oscillator adapted for digital signal clock synchronization comprising:
The oscillator, wherein the phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal.   The sine wave-to-logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital logic output signal having substantially the same frequency as the control frequency signal. The oscillator described.   The variable capacitance circuit includes a variable capacitance circuit operatively coupled to the crystal resonator and a discrete varactor operatively coupled to the crystal resonator, the variable capacitance circuit responding to the capacitance adjustment. 41. The oscillator of claim 40, wherein the discrete varactor comprises the control input and is responsive to the control input.   41. The oscillator of claim 40, wherein the variable capacitance circuit has a discrete varactor part.   41. The oscillator according to claim 40, wherein the variable capacitance circuit includes a variable capacitance circuit mounted on a chip.   41. The oscillator of claim 40, wherein the variable capacitance circuit includes a switchable bank of capacitors.   41. The oscillator of claim 40, wherein the variable capacitance element includes a bank of varactors mounted on a switchable chip. The V _control as DC voltage level of said voltage variable input for _{V control} value in the range of about 0.15 volts to about 3.15 volts, the operating temperature of the oscillator in the range of about -30 degrees Celsius to about 85 degrees The oscillator according to claim 1, wherein the oscillator shows an operating digital output frequency in a region defined between the following two equations.
f1 _output = 0.04526 (V _control ) +6211.9430 megahertz f2 _output = 0.04526 (V _control ) +6211.9679 megahertz A temperature compensated oscillator module having a crystal resonator and providing a drive signal having an oscillation frequency substantially independent of operating temperature;
A discrete varactor operatively coupled to the crystal resonator of the temperature compensated oscillator module to provide a variable capacitive load;
A variable voltage control input operatively coupled to the discrete varactor;
A resonator gain stage;
A crystal resonator operatively coupled to the gain stage and the voltage variable capacitance means to generate a drive signal, wherein the voltage variable control input adjusts the frequency of the capacitive load and the drive signal. The quartz crystal vibrator,
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A divider circuit having a preselected divide ratio that is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generates a reduced frequency feedback signal in response to the control frequency signal. A frequency tunable oscillator adapted for digital signal clock synchronization comprising:
The oscillator, wherein the phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal.   49. The sine wave-to-logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital logic output signal having substantially the same frequency as the control frequency signal. The oscillator described.   49. The oscillator of claim 48, wherein the converter circuit is a differential receiver adapted to generate the digital output signal at a voltage level according to positive reference emitter coupled logic (PECL). A crystal oscillator circuit having a voltage variable control input for generating a drive signal and adjusting a frequency of the drive signal, the voltage variable capacitor element responsive to the control input, and operatively coupled to the voltage variable capacitor element A crystal oscillator circuit comprising: an AT-cut crystal resonator; and a gain stage for applying energy to the crystal resonator;
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A divider circuit having a preselected divide ratio that is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generates a reduced frequency feedback signal in response to the control frequency signal. A frequency tunable oscillator adapted for digital signal clock synchronization comprising:
The phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal;
A double-sided package comprising the pedestal having a central portion and the outer portion having sidewalls extending substantially upward and substantially downward from the outer portion of the pedestal,
The upwardly extending side wall and the pedestal form a first cavity adapted to receive and electrically connect the quartz crystal resonator, and the downwardly extending side wall and the pedestal receive at least one electronic component. Said double-sided package forming a second cavity adapted to be electrically connected;
An oscillator comprising: a cover that is coupled to the first cavity and defines an airtight environment that houses the crystal resonator.   52. The oscillator of claim 51, wherein the voltage variable capacitive element includes a discrete varactor housed in the second cavity and operatively coupled to the crystal resonator.   52. The oscillator of claim 51, wherein the voltage controlled oscillator circuit is on an electronic component housed in the first cavity.   52. The oscillator of claim 51, wherein elements of the gain stage, the phase detector circuit, a voltage controlled oscillator circuit, and the divider circuit are housed in the second cavity. 52. The oscillator of claim 51, wherein the following elements are integrated on a single semiconductor chip housed in the second cavity.
The gain stage, the phase detector circuit, the voltage controlled oscillator circuit, and
The frequency divider circuit;   52. The oscillator of claim 51, further comprising a laminated substrate coupled to the second cavity.   57. The pedestal has a second cavity surface, at least one electronic component is mounted on the second cavity surface, and at least one electronic component is mounted on the multilayer substrate. The oscillator described in 1.   57. The oscillator of claim 56, wherein the laminated substrate has a side chest wall.   57. The oscillator according to claim 56, wherein the multilayer substrate is multilayer and has an embedded inductor.   The printed circuit board further includes a printed circuit board coupled to the second cavity, the printed circuit board adapted to facilitate electrical surface mountable connection to the cavity facing surface for receiving at least one electronic component and the electronic device. 52. The oscillator of claim 51, further comprising an outwardly facing surface having a plurality of integrated contacts.   52. The oscillator of claim 51, wherein the AT-cut quartz crystal resonator is tunable and the second cavity includes a contact that is electrically coupled to the resonator for tuning.   52. The oscillator of claim 51, wherein the control digital logic output has a nominal operating frequency of about 622.08 megahertz and a frequency control range of at least 50 ppm.   52. The oscillator of claim 51, wherein the control frequency signal has a nominal operating frequency of about 644.531 megahertz and a frequency control range of at least 50 ppm.   52. The oscillator of claim 51, wherein the control frequency signal has a nominal operating frequency of about 666.514 megahertz and a frequency control range of at least 50 ppm.   52. The oscillator of claim 51, wherein the control frequency signal has a nominal operating frequency of about 669.326 megahertz and a frequency control range of at least 50 ppm.   52. The sine wave to logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital output signal having substantially the same frequency as the control frequency signal. Oscillator.   68. The oscillator of claim 66, wherein the converter circuit is a differential receiver adapted to generate the digital output signal at a voltage level according to positive reference emitter coupled logic (PECL).   52. The oscillator of claim 51 having a substantially rectangular mounting surface of about 5 millimeters by about 7 millimeters.   52. The oscillator of claim 51, having an installation surface less than about 40 square millimeters.   52. The oscillator of claim 51, wherein the crystal resonator is configured to operate in a fundamental mode.   52. The oscillator according to claim 51, wherein the crystal oscillator circuit further includes a temperature compensation unit. A double-sided package comprising the pedestal having a central portion and the outer portion having sidewalls extending substantially upward and substantially downward from the outer portion of the pedestal,
The upwardly extending side wall and the pedestal form a first cavity adapted to receive and electrically connect the quartz crystal resonator, and the downwardly extending side wall and the pedestal receive at least one electronic component. Said double-sided package forming a second cavity adapted to be electrically connected;
A crystal oscillator circuit having a voltage variable control input for generating a drive signal and adjusting a frequency of the drive signal, the voltage variable capacitance element responding to the control input, and being accommodated in the first cavity, the voltage variable The crystal oscillator circuit, comprising: an AT-cut quartz crystal resonator operatively coupled to a capacitive element; and a gain stage for energizing the crystal resonator;
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A divider circuit having a preselected divide ratio that is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generates a reduced frequency feedback signal in response to the control frequency signal. A frequency tunable oscillator adapted for digital signal clock synchronization comprising:
The phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal;
A sine wave-to-logic level converter circuit operatively coupled to the voltage controlled oscillator and generating a digital output signal having substantially the same frequency as the control frequency signal;
An oscillator comprising: a cover that is coupled to the first cavity and defines an airtight environment that houses the crystal resonator. 2. The oscillator according to claim 1, wherein the following elements are integrated in a single semiconductor chip accommodated in the second cavity.
The gain stage, the phase detector circuit, the voltage controlled oscillator circuit, and
The frequency divider circuit; A temperature sensor;
A temperature compensation logic unit operatively coupled to the temperature sensor to generate a capacitance adjustment;
A variable capacitance circuit comprising a control input and providing a variable capacitance load in response to the control input, the variable capacitance circuit also responding to the capacitance adjustment;
A resonator gain stage;
A crystal resonator operatively coupled to the gain stage and the variable capacitance circuit to generate a drive signal;
A phase detector circuit for generating a phase offset signal;
A filter that operates based on the phase offset signal and generates a VCO control signal;
A voltage controlled oscillator circuit operatively coupled to the filter and generating an analog control frequency signal in response to the VCO control signal;
A divider circuit having a preselected divide ratio that is operatively coupled between the voltage controlled frequency oscillator circuit and the phase detector circuit and generates a reduced frequency feedback signal in response to the control frequency signal. A frequency tunable oscillator adapted for digital signal clock synchronization comprising:
The phase detector circuit is responsive to the feedback signal and the drive signal to change the phase offset signal according to a phase difference between the feedback signal and the drive signal;
A double-sided package comprising the pedestal having a central portion and the outer portion having sidewalls extending substantially upward and substantially downward from the outer portion of the pedestal,
The upwardly extending sidewall and the pedestal form a first cavity adapted to receive and electrically connect the quartz resonator, and the downwardly extending sidewall and the pedestal receive at least one electronic component. Said double-sided package forming a second cavity adapted to be electrically connected;
An oscillator comprising: a cover that is coupled to the first cavity and defines an airtight environment that houses the crystal resonator. The oscillator of claim 74, wherein the following elements are integrated on a single semiconductor chip housed in the second cavity.
-The temperature sensor-the temperature compensation logic unit-the variable capacitance circuit-the gain stage-the phase detector circuit-the voltage controlled oscillator circuit, and
The frequency divider circuit;   The oscillator of claim 74, further comprising a laminated substrate coupled to the second cavity. A printed circuit board coupled to the second cavity, the printed circuit board cover being adapted to receive at least one electronic component and an electrically surface mountable connection to the electronic device 75. The oscillator of claim 74 having an outwardly facing surface having a plurality of integrated contacts adapted to facilitate operation.

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