JP2005503680A5

JP2005503680A5 -

Info

Publication number: JP2005503680A5
Application number: JP2002543290A
Authority: JP
Filing date: 2001-11-19
Publication date: 2005-05-26
Anticipated expiration: 2021-11-19

Claims

Configuration information and related information based on the customization specification, including application information including application source code and customization information including design constraints, to implement an instruction processor using reprogrammable hardware A method for generating executable code,
Generating a template for each processor style identified as a candidate for implementation;
Analyzing instruction information for each template and determining instruction optimization;
Including the instruction optimization and compiling the application source code to produce executable code;
Analyzing the architecture information for each template and determining architecture optimization;
Generating configuration information including the architecture optimization;
Generating device-specific configuration information from the configuration information including the architecture optimization;
Including the method.

Profiling the configuration information and associated code for each candidate implementation;
In response, selecting one or more optimal implementations based on predictable criteria;
The method of claim 1 further comprising:

The method according to claim 1 or 2, wherein the customization information further comprises at least one custom instruction.

Profiling the customization specification information;
Identifying at least one processor style as a candidate for implementation;
The method according to any one of claims 1 to 3, further comprising:

The method of claim 4, wherein profiling information for enabling optimization is collected in a customization specification profiling step.

The instruction information analyzing step includes:
Utilizing the profiling information in analyzing the instruction information;
Determining the instruction optimization; and
The method of claim 5 comprising:

The instruction information analyzing step includes:
Identifying candidate instruction optimizations;
Determining an instruction optimization implementation based on an estimate made based on the candidate instruction optimization instructions;
The method according to claim 1, comprising:

If the estimation provides that the reprogrammable hardware cannot be programmed to implement all instructions together during runtime, the instruction information analysis step comprises:
8. The method of claim 7, comprising grouping individual instructions in combination with a set of instructions that can be implemented by reprogramming the reprogrammable hardware.

The instruction information analyzing step includes:
Determining a plurality of implementations for different runtime states, each having instructions associated with the runtime states;
Generating decision state information associated with each implementation, the decision state information allowing selection between the implementations depending on the actual runtime state; and
9. The method according to any one of claims 1 to 8, comprising:

If the instruction optimization fails to provide an implementation that compiles with design constraints, the instruction information analysis step comprises:
Any one of claims 1-9 when dependent on claim 4, comprising the step of invoking the customization specification profiling step and reprofiling the customization specification based on the analysis information provided by the instruction information analysis step. The method according to any one of the above.

The method according to claim 1, wherein the architecture optimization includes pipeline processing.

If multiple configurations of reprogrammable hardware are required to implement the instruction processor, the instruction step comprises:
Optimizing individual configurations into groups;
Scheduling the implementation of the grouped configuration;
12. The method according to any one of claims 1 to 11, comprising:

13. A method according to any one of the preceding claims, wherein each template is generated from processor definitions and associated parameters extracted from a library containing processor definitions and associated parameters for multiple processor styles.

The compiler used in the step of compiling the application source code is generated in the instruction information analysis step, and the compiling step includes:
Annotating the application source code with customization information;
Compiling the annotated source code to provide optimized executable code;
14. The method according to any one of claims 1 to 13, comprising:

The step of compiling includes
Compiling the application source code;
Reorganizing the compiled source code to incorporate optimization to provide optimized executable code;
14. The method according to any one of claims 1 to 13, comprising:

The configuration information and associated executable code, and, where relevant, the decision state information, is at least one management for managing reconfiguration of an instruction processor implemented using reprogrammable hardware 16. A method according to any one of the preceding claims, further comprising deploying to the system.

Deploying the configuration information and associated executable code, and, if relevant, the decision state information into at least one library to allow reprogramming of the reprogrammable hardware. The method according to any one of claims 1 to 16, further comprising:

Configuration information and related based on customization specifications, including application information including application source code and customization information including design constraints, to implement an instruction processor using reprogrammable hardware A design system for generating executable code,
A template generator for generating a template for each processor style identified as a candidate for implementation;
An analyzer for analyzing instruction information for each template and determining instruction optimization;
A compiler for including the instruction optimization and for compiling the application source code to produce executable code;
An instantiator for analyzing the architecture information for each template, determining architecture optimization, and generating configuration information including the architecture optimization;
A builder for generating device specific configuration information from the configuration information including the architecture optimization;
Including the system.

A method for managing runtime reconfiguration of an instruction processor implemented in reprogrammable hardware comprising:
Providing a configuration library including configuration information for implementations of a plurality of instruction processors;
Providing a code library for including relevant executable code for the implementation;
Loading application data, and optionally configuration information and executable code into reprogrammable hardware for instruction processor implementation and execution;
Executing the executable code;
Obtaining runtime statistics regarding the operation of the instruction processor;
Loading new configuration information for the new implementation and associated executable code into the reprogrammable hardware;
Including the method.

The method of claim 19, wherein the loading is performed automatically on a scheduleable event.

21. A method according to claim 19 or 20, wherein the loading step is actuated by an external agent.

Prior to the loading step, further comprising loading the configuration information and associated executable code for a new implementation into an individual configuration library and the code library, respectively.
The loading step includes loading the configuration information and associated executable code for the appropriate implementation into the reprogrammable hardware when operated by an external agent. The method described in 1.

Providing a decision state library for including relevant decision state information for at least one of the implementations;
Profiling the decision state information for a plurality of other implementations for various runtime states of the implementation loaded in the reprogrammable hardware;
Determining whether the decision state information for any of the other implementations more closely matches the runtime statistics;
If the decision state information for one of the other implementations more closely matches the runtime statistics, the loading step comprises:
23. A method as claimed in any one of claims 19 to 22 comprising loading the configuration information and associated executable code for a relevant implementation into the reprogrammable hardware.

24. The method of any one of claims 19-23, further comprising generating one or more new implementations optimized for the runtime statistics.

23. Subordinate to any one of claims 19-22, further comprising loading the configuration information and associated executable code for each new implementation into an individual configuration library and the code library, respectively. The method of claim 24 in the case.

24. The method further comprises loading the configuration information, associated executable code, and associated decision state information for each new implementation into an individual configuration library, the code library, and the decision state library, respectively. 25. The method of claim 24 when subordinate to.

27. A method as claimed in any one of claims 19 to 26, wherein the configuration information and associated executable code for a new implementation is loaded into the reprogrammable hardware that satisfies a schedulable criterion. .

The implementation generation step includes:
Analyzing instruction information based on the runtime statistics to determine instruction optimization;
Compiling the application source code to include the instruction optimization and generating executable code;
Analyzing architecture information based on the runtime statistics to determine architecture optimization;
Generating configuration information including the architecture optimization;
Generating device specific configuration information from the configuration information including the architecture optimization;
28. A method according to any one of claims 24-27, comprising:

The implementation step includes:
Profiling the configuration information and associated code for each candidate implementation;
In response, selecting one or more optimal implementations based on predictable criteria;
30. The method of claim 28, further comprising:

The implementation generation step includes:
Profiling customization specifications and information in the runtime statistics;
Identifying at least one processor style as a candidate for implementation;
Generating a template for each processor style identified as a candidate for implementation; and
30. The method of claim 28 or 29, further comprising:

32. The method of claim 30, wherein profiling information for enabling optimization is collected in the customization specification profile step.

The instruction information analyzing step includes:
Utilizing the profiling information in analyzing the instruction information;
Determining the instruction optimization; and
32. The method of claim 31 comprising:

The instruction information analyzing step includes:
Identifying candidate instruction optimizations;
Determining an implementation of the instruction optimization based on an estimate made based on the instruction of the candidate instruction optimization;
33. A method according to any one of claims 28 to 32, comprising:

If the estimate provides that the reprogrammable hardware cannot be programmed to implement all instructions together at runtime, the instruction information analysis step comprises:
34. The method of claim 33, comprising grouping individual instructions in combination into a set of instructions that can be implemented by reprogramming the reprogrammable hardware.

The instruction information analyzing step includes:
Determining a plurality of implementations for different runtime states, each having an instruction optimization associated with the runtime state;
Generating decision state information associated with each implementation, the decision state information allowing selection between the implementations depending on the actual runtime state; and
35. The method of any one of claims 28 to 34, comprising:

If the instruction optimization cannot provide an implementation that compiles with design constraints, the instruction information analysis step comprises:
Invoking the customization specification profile step to reprofile the customization specification based on the analysis information provided by the instruction information analysis step;
36. A method according to any one of claims 28 to 35 when dependent on claim 30, comprising:

37. The method of any one of claims 28 to 36, wherein the architecture optimization includes resource replication.

Multiple configurations of reprogrammable hardware are required to implement the instruction processor, and the instantiation step comprises:
Optimizing individual configurations into groups;
Scheduling the implementation of grouped configurations; and
38. The method of any one of claims 28-37, comprising:

39. A method according to any one of claims 30 to 38, wherein each template is generated from a processor definition and associated parameters extracted from a library comprising processor definitions and associated parameters for a plurality of processor styles.

The compiler used in compiling the application source code is generated in the instruction information analysis step, and the compilation step includes:
Annotating the application source code with customization information;
Compiling the annotated source code to provide optimized executable code;
40. The method of any one of claims 28-39, comprising:

The step of compiling includes
Compiling the application source code;
Reorganizing the compiled source code to incorporate optimization to provide optimized executable code;
40. The method of any one of claims 28-39, comprising:

A management system for managing runtime reconfiguration of instruction processors implemented using reprogrammable hardware, comprising:
A configuration library containing configuration information for multiple instruction processor implementations;
A code library for including relevant executable code for the implementation;
A loader for loading application data, and optionally configuration information and associated executable code, into reprogrammable hardware for instruction processor implementation and execution;
A loader controller for loading application data and, optionally, configuration information and associated executable code into the loader and signaling to execute the executable code;
A runtime monitor for obtaining runtime statistics regarding the operation of the instruction processor;
An optimization configured to receive the runtime statistics and to instruct the loader to load new configuration information for the new implementation and associated executable code into the reprogrammable hardware Detamina,
An optimization instructor to call the optimization determiner and
Including the system.