JP2005354814A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can shorten the charging time of negative voltage to output a normal waveform in a short time after the start of operation of an output circuit, in an integrated circuit having an output circuit containing a negative power generation circuit to output positive and negative signals. <P>SOLUTION: In the semiconductor integrated circuit for generating negative power supply with a charge pump, a delay time sufficient for charging the negative voltage is provided between the start of operation of the charge pump and the start of operation of output circuit by counting a clock used in the charge pump with a counter circuit, to shorten the charging time of the negative voltage with the output of normal waveform in a short time after the start of operation of the output circuit. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit having an output circuit using a negative power source generated by a charge pump circuit and capable of outputting positive and negative.

  Conventionally, an integrated circuit that operates with a single power supply voltage and drives a resistive load uses a DC coupling capacitor in order to obtain an average voltage of 0 V at the resistive load end of the output signal. In particular, an integrated circuit having an analog video output and an audio output requires a large capacity for the DC coupling capacity in order to output a low-frequency signal. However, in recent years, with the acceleration of downsizing and weight reduction of portable devices, there has been a demand for a configuration that does not use a DC coupling capacitor that requires a large part space.

  Patent Document 1 discloses a configuration in which a single power supply voltage supply does not use an output DC coupling capacitor, but has a disadvantage that a DC current flows through a load to operate an output circuit between a positive power supply and 0V. Patent Document 2 proposes an integrated circuit that incorporates a circuit that generates a negative power supply from a single positive power supply voltage and can output a signal positively or negatively without a DC coupling capacitor.

  A conventional semiconductor integrated circuit that incorporates a negative power supply generation circuit and can output positive and negative signals will be described below.

  FIG. 3 shows a conventional semiconductor integrated circuit.

  In FIG. 3, 1 is a negative power supply generation circuit, 2 is an output circuit, 3 is negative power supply generation circuit control, 4 is output circuit control, and 10 is a semiconductor integrated circuit composed of the negative power supply generation circuit 1 and the output circuit 2. . 11 is a charging capacity, 12 is a negative power supply voltage, 13 is a resistance load, 14 is an input terminal, 15 is a positive power supply voltage, and 16 is an output terminal.

  The operation of the semiconductor integrated circuit configured as described above will be described below.

  When the negative power source generation circuit control 3 is set to ON, the negative power source generation circuit 1 starts operation and charges the charging capacitor 11 with a negative voltage. When the negative power supply generation circuit control 3 is set to OFF, the operation and charging of the negative power supply generation circuit 1 are stopped.

The output circuit 2 starts operation when the output circuit control 4 is set to ON, drives the resistance load 13, and outputs a positive / negative signal. When the output circuit control 4 is turned off, the output circuit enters a power saving state and stops its operation.
JP-A-9-148848 JP-A-7-106963

  However, in the above configuration, there is a possibility that the output circuit 2 operates after the negative power source generation circuit control 3 is turned on and before a sufficient negative voltage is charged. In this case, the current consumed by the output circuit 2 For this reason, the time until the power of the negative power source is consumed and the battery is sufficiently charged is increased, and before the battery is sufficiently charged, the malfunction of the output circuit 2 and the problem that the output signal is not normally output on the negative side occur. . In particular, when the output circuit 2 is a video 75Ω driver or an audio headphone amplifier, a charging capacity of several μF or more is used to make the negative power source low impedance up to a low frequency, and more current flows into the negative power source. Therefore, the operation of the output circuit during the negative voltage charging makes the charging time very long and causes a problem in the transient response of the output.

  FIG. 4 is a time chart of the negative power source generation circuit control 3, the output circuit control 4, the negative power source voltage 12, and the voltage at the output terminal 16 when the negative power source generation circuit control 3 and the output circuit control 4 are simultaneously turned ON. Show. Since a current flows into the negative power supply in the output circuit 2, the charging time becomes long, and a signal cannot be output below a negative voltage. Therefore, there is a problem that the signal is not normally output during the negative voltage charging.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that shortens the negative voltage charging time and outputs a normal signal from the start of operation of the output circuit 2.

  In order to achieve the above object, a semiconductor integrated circuit according to the present invention generates a negative power source in a charge pump circuit and is generated inside the charge pump circuit between the start of operation of the charge pump and the start of output circuit operation. The counter clock is counted by a counter circuit to provide a delay time.

  According to the semiconductor integrated circuit of the present invention, it is possible to realize an excellent semiconductor integrated circuit which can quickly charge a negative power source and prevent abnormal waveform output or malfunction during charging.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a configuration diagram of a semiconductor integrated circuit according to the first embodiment of the present invention.

  In FIG. 1, 2 is an output circuit, 5 is a charge pump, 6 is an oscillation circuit, 7 is a counter circuit, 3 is a negative power supply generation circuit control, and 4 is an output circuit control. Reference numeral 1 denotes a negative power supply generation circuit including a charge pump 5 and an oscillation circuit 6, and reference numeral 20 denotes a semiconductor integrated circuit including a negative power supply generation circuit 1, an output circuit 2, and a counter circuit 7. 11 is a charging capacity, 12 is a negative power supply voltage, 13 is a resistance load, 14 is an input terminal, 15 is a positive power supply voltage, and 16 is an output terminal.

  The operation of the semiconductor integrated circuit 20 configured as described above will be described below.

  When the negative power supply generation circuit control 3 is turned on, the oscillation circuit 6 starts to operate, inputs the output clock of the oscillation circuit 6 to the charge pump 5, and starts charging the charging capacitor 11 with negative voltage. The counter circuit 7 is set when the negative power generation circuit control 3 is ON, counts the output clock of the oscillation circuit 6, and sends the delayed control signal of the negative power generation circuit control 3 to the output circuit 2. This delay time is set as a time for sufficiently charging the negative voltage. When the negative power supply generation circuit control 3 is turned off, the oscillation circuit and the output circuit are stopped. The operation of the output circuit 2 is the same as that of the conventional example.

  FIG. 2 shows a time chart of the negative power supply generation circuit control 3, the output circuit control 4, the negative power supply voltage 12, and the voltage at the output terminal 16. In the figure, Δt is a time delayed by the counter circuit 7. Compared to FIG. 4, the charging time of the negative power supply voltage is faster, and the output signal that was on the lower side of the waveform before the negative voltage is sufficiently charged in FIG. 4 also operates the output circuit after sufficiently charging the negative voltage. A normal output signal can be obtained.

  As described above, the present invention is useful for a semiconductor integrated circuit that uses a negative power source generated by a charge pump circuit and has an output circuit capable of positive and negative outputs.

Configuration diagram of a semiconductor integrated circuit in an embodiment of the present invention Time chart in the embodiment of the present invention Configuration diagram of a semiconductor integrated circuit in an embodiment of a conventional example Time chart in the embodiment of the conventional example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Negative power supply generation circuit 2 Output circuit 3 Negative power supply generation circuit control 4 Output circuit control 5 Charge pump 6 Oscillation circuit 7 Counter circuit 10, 20 Semiconductor integrated circuit 11 Charging capacity 12 Negative power supply voltage 13 Resistive load 14 Input terminal 15 Positive power supply Voltage (VDD)
16 output terminals

Claims (1)

A semiconductor integrated circuit having a negative power supply in a charge pump circuit and having an output circuit capable of positive and negative outputs using the negative power supply, wherein the charge pump is operated between the start of operation of the charge pump and the start of operation of the output circuit. A semiconductor integrated circuit in which a clock generated in the pump circuit is counted by a counter circuit to provide a delay time.

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